JP2007258469A - 半導体集積回路装置 - Google Patents
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Abstract
【解決手段】半導体チップに配置された複数の電源パッド(4b、4c、4g、4h)と、半導体チップに配置されるとともに、電源パッドよりも幅が狭く構成された複数の信号パッド(4a)と、を備える。信号パッドおよび電源パッドは、複数の配線層のうち最上位配線層に配設される。IOセルと信号パッドを電気的に接続する信号配線(4d)は、最上位配線層に配設される。IOセルと第1電源パッド(4b、4c)を電気的に接続する第1電源配線(4e、4f)は、最上位配線層に配設される。内部回路と第2電源パッド(4g、4h)を電気的に接続する第2電源配線(4i、4j)は、最上位配線層に配設される。
【選択図】図2
Description
本発明の実施形態1に係る半導体集積回路装置について図面を用いて説明する。図1は、本発明の実施形態1に係る半導体集積回路装置のバンプ配設面を模式的に示した平面図である。図2は、本発明の実施形態1に係る半導体集積回路装置における図1の2点鎖線で囲まれた部位のパッド及び配線のパターンを模式的に示した部分拡大平面図である。図3は、本発明の実施形態1に係る半導体集積回路装置の最上位配線層のパターンのみを模式的に示した部分平面図である。図4は、本発明の実施形態1に係る半導体集積回路装置を模式的に示した図2のX−X´間の部分断面図である。図5は、本発明の実施形態1に係る半導体集積回路装置を模式的に示した図2のY−Y´間の部分断面図である。
1a 内部回路領域
1b IOセル領域
1c IOセル
2 バンプ
3 絶縁層
4 最上位配線層
4a 信号パッド
4b 第1VDDパッド(電源パッド、第1電源パッド)
4c 第1GNDパッド(電源パッド、第1電源パッド)
4d 信号配線
4e 第1VDD配線(第1電源配線)
4f 第1GND配線(第1電源配線)
4g 第2VDDパッド(電源パッド、第2電源パッド)
4h 第2GNDパッド(電源パッド、第2電源パッド)
4i 第2VDD配線(第2電源配線)
4j 第2GND配線(第2電源配線)
5 絶縁層
6a ビア
6b ビア
7 配線層
7a 第1信号配線(信号配線)
7b 第1GND配線(第1電源配線)
8 絶縁層
9a ビア
9b ビア
10 半導体基板
10a 信号端子(拡散層)
10b 第1VDD端子
10c 第1GND端子(拡散層)
10d 第2VDD端子
10e 第2GND端子
Claims (15)
- 半導体チップに配置された複数の電源パッドと、
前記半導体チップに配置されるとともに、前記電源パッドよりも幅が狭く構成された複数の信号パッドと、
を備えることを特徴とする半導体集積回路装置。 - 前記電源パッドは、正方形のパッドであり、
前記信号パッドは、長方形のパッドであることを特徴とする請求項1記載の半導体集積回路装置。 - 前記半導体チップは、IOセルと内部回路を有し、
前記電源パッドは、前記IOセル用の第1電源パッドと、前記内部回路用の第2電源パッドを有し、
前記第1電源パッドは、前記IOセル上ないしその近傍に配置され、
前記第2電源パッドは、前記内部回路上に配置されることを特徴とする請求項1又は2記載の半導体集積回路装置。 - 前記内部回路は、前記半導体チップの中央に配置され、
前記IOセルは、前記半導体チップの外周辺の近傍に配置されることを特徴とする請求項3記載の半導体集積回路装置。 - 前記信号パッドおよび前記電源パッドは、複数の配線層のうち最上位配線層に配設されることを特徴とする請求項1乃至4のいずれか一に記載の半導体集積回路装置。
- 前記IOセルと前記信号パッドを電気的に接続する信号配線の少なくとも一部は、前記最上位配線層に配設されることを特徴とする請求項5記載の半導体集積回路装置。
- 前記IOセルと前記第1電源パッドを電気的に接続する第1電源配線の少なくとも一部は、前記最上位配線層に配設されることを特徴とする請求項5又は6記載の半導体集積回路装置。
- 前記内部回路と前記第2電源パッドを電気的に接続する第2電源配線の少なくとも一部は、前記最上位配線層に配設されることを特徴とする請求項5乃至7のいずれか一に記載の半導体集積回路装置。
- 前記信号パッドは、前記第1電源パッドを避けながら前記半導体チップの外周近傍から順に配置されることを特徴とする請求項4乃至8のいずれか一に記載の半導体集積回路装置。
- 前記電源パッドおよび前記信号パッドのそれぞれの上に配設される複数のバンプを備え、
各前記バンプは、大きさが略同一であることを特徴とする請求項1乃至9のいずれか一に記載の半導体集積回路装置。 - 前記第1電源配線のうち前記最上位配線層に配設された部分は、前記半導体チップの外周に沿って配線され、
前記信号パッドの少なくとも一部は、前記IOセル上に配置され、かつ、前記半導体チップの外周辺に直角な方向の幅が狭いパッドであることを特徴とする請求項7乃至10のいずれか一に記載の半導体集積回路装置。 - 前記第2電源配線のうち前記最上位配線層に配設された少なくとも一部は、前記半導体チップの外周辺に対して直角な方向に配線され、
前記信号パッドの少なくとも一部は、前記内部回路上であって前記第2電源配線の間に配置され、かつ、前記半導体チップの外周辺と平行な方向の幅が狭いパッドであることを特徴とする請求項8乃至11のいずれか一に記載の半導体集積回路装置。 - 前記複数の電源パッドのうち、一の電源パッドの対向する2辺の両端から同一方向に平行に配線された一対の電源配線をさらに備え、
前記複数の信号パッドは、前記一対の電源配線に挟まれて配置された第1信号パッドを含み、
前記第1信号パッドの幅は、前記一対の電源配線の間隔より狭いことを特徴とする請求項1乃至12のいずれか一に記載の半導体集積回路装置。 - 前記複数の信号パッドは、前記一対の電源配線に挟まれて配置されるとともに前記第1信号パッドと抵触しない領域に配置された第2信号パッドを含み、
前記第2信号パッドは、第2信号配線と接続され、
前記複数の電源パッド、前記第1及び第2信号パッド、前記一対の電源配線、並びに前記第2信号配線は、同一配線層を用いて配置され、
前記第2信号配線は、前記第1信号パッドと前記一対の電源配線との間を通過する配線であることを特徴とする請求項13記載の半導体集積回路装置。 - 前記一対の電源配線の間隔は、前記電源パッドの前記対向する2辺の間隔より狭いことを特徴とする請求項13又は14記載の半導体集積回路装置。
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JP2006081347A JP4993929B2 (ja) | 2006-03-23 | 2006-03-23 | 半導体集積回路装置 |
US11/723,827 US7541683B2 (en) | 2006-03-23 | 2007-03-22 | Semiconductor integrated circuit device |
CN2007100887424A CN101043033B (zh) | 2006-03-23 | 2007-03-22 | 半导体集成电路装置 |
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Publication number | Priority date | Publication date | Assignee | Title |
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JP2009302136A (ja) * | 2008-06-10 | 2009-12-24 | Panasonic Corp | 半導体集積回路 |
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JP4986114B2 (ja) * | 2006-04-17 | 2012-07-25 | ルネサスエレクトロニクス株式会社 | 半導体集積回路及び半導体集積回路の設計方法 |
US9076848B2 (en) | 2013-03-12 | 2015-07-07 | International Business Machines Corporation | Semiconductor device channels |
US9111935B2 (en) | 2013-03-12 | 2015-08-18 | International Business Machines Corporation | Multiple-patterned semiconductor device channels |
US9099471B2 (en) | 2013-03-12 | 2015-08-04 | International Business Machines Corporation | Semiconductor device channels |
CN108010898A (zh) * | 2017-11-02 | 2018-05-08 | 上海玮舟微电子科技有限公司 | 一种芯片封装结构 |
US20210287965A1 (en) * | 2020-03-13 | 2021-09-16 | Samsung Electronics Co., Ltd. | Semiconductor device |
US11688686B2 (en) | 2020-07-14 | 2023-06-27 | Samsung Electronics Co., Ltd. | Semiconductor device including an input/output circuit |
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US6674646B1 (en) * | 2001-10-05 | 2004-01-06 | Skyworks Solutions, Inc. | Voltage regulation for semiconductor dies and related structure |
DE60336993D1 (de) * | 2003-06-10 | 2011-06-16 | St Microelectronics Srl | Elektronische Halbleitervorrichtung und Verfahren zu deren Herstellung |
JP4533173B2 (ja) * | 2004-02-24 | 2010-09-01 | キヤノン株式会社 | 半導体集積回路装置 |
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Patent Citations (8)
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JPH0653413A (ja) * | 1992-07-29 | 1994-02-25 | Nec Corp | 半導体集積回路 |
JPH1145903A (ja) * | 1997-07-25 | 1999-02-16 | Oki Electric Ind Co Ltd | 半導体素子及び半導体装置 |
JP2000311917A (ja) * | 1999-04-27 | 2000-11-07 | Oki Electric Ind Co Ltd | 半導体装置 |
JP2001223335A (ja) * | 2000-02-10 | 2001-08-17 | Nec Corp | 半導体装置 |
JP2002190526A (ja) * | 2000-12-21 | 2002-07-05 | Nec Microsystems Ltd | フリップチップ型半導体装置 |
JP2004221260A (ja) * | 2003-01-14 | 2004-08-05 | Fujitsu Ltd | 半導体装置 |
JP2005093575A (ja) * | 2003-09-16 | 2005-04-07 | Nec Electronics Corp | 半導体集積回路装置と配線レイアウト方法 |
JP2005191447A (ja) * | 2003-12-26 | 2005-07-14 | Renesas Technology Corp | 半導体装置およびその製造方法 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2009302136A (ja) * | 2008-06-10 | 2009-12-24 | Panasonic Corp | 半導体集積回路 |
US8669593B2 (en) | 2008-06-10 | 2014-03-11 | Panasonic Corporation | Semiconductor integrated circuit |
Also Published As
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US7541683B2 (en) | 2009-06-02 |
JP4993929B2 (ja) | 2012-08-08 |
US20070222082A1 (en) | 2007-09-27 |
CN101043033B (zh) | 2011-12-14 |
CN101043033A (zh) | 2007-09-26 |
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