DE60336993D1 - Elektronische Halbleitervorrichtung und Verfahren zu deren Herstellung - Google Patents
Elektronische Halbleitervorrichtung und Verfahren zu deren HerstellungInfo
- Publication number
- DE60336993D1 DE60336993D1 DE60336993T DE60336993T DE60336993D1 DE 60336993 D1 DE60336993 D1 DE 60336993D1 DE 60336993 T DE60336993 T DE 60336993T DE 60336993 T DE60336993 T DE 60336993T DE 60336993 D1 DE60336993 D1 DE 60336993D1
- Authority
- DE
- Germany
- Prior art keywords
- manufacture
- semiconductor device
- electronic semiconductor
- electronic
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05075—Plural internal layers
- H01L2224/0508—Plural internal layers being stacked
- H01L2224/05083—Three-layer arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05624—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05647—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01014—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1203—Rectifying Diode
- H01L2924/12036—PN diode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP03425368A EP1487015B1 (de) | 2003-06-10 | 2003-06-10 | Elektronische Halbleitervorrichtung und Verfahren zu deren Herstellung |
Publications (1)
Publication Number | Publication Date |
---|---|
DE60336993D1 true DE60336993D1 (de) | 2011-06-16 |
Family
ID=33186023
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE60336993T Expired - Lifetime DE60336993D1 (de) | 2003-06-10 | 2003-06-10 | Elektronische Halbleitervorrichtung und Verfahren zu deren Herstellung |
Country Status (3)
Country | Link |
---|---|
US (1) | US7126230B2 (de) |
EP (1) | EP1487015B1 (de) |
DE (1) | DE60336993D1 (de) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4993929B2 (ja) * | 2006-03-23 | 2012-08-08 | ルネサスエレクトロニクス株式会社 | 半導体集積回路装置 |
US11410929B2 (en) * | 2019-09-17 | 2022-08-09 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and method of manufacture |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1993012540A1 (en) * | 1991-12-10 | 1993-06-24 | Vlsi Technology, Inc. | Integrated circuit with variable pad pitch |
US5384487A (en) * | 1993-05-05 | 1995-01-24 | Lsi Logic Corporation | Off-axis power branches for interior bond pad arrangements |
JP3577913B2 (ja) * | 1997-02-27 | 2004-10-20 | セイコーエプソン株式会社 | 半導体装置、およびこれを具備する電子機器 |
KR100230428B1 (ko) * | 1997-06-24 | 1999-11-15 | 윤종용 | 다층 도전성 패드를 구비하는 반도체장치 및 그 제조방법 |
JP3472455B2 (ja) * | 1997-09-12 | 2003-12-02 | 沖電気工業株式会社 | 半導体集積回路装置及びそのパッケージ構造 |
JP3679923B2 (ja) * | 1998-05-07 | 2005-08-03 | 株式会社東芝 | 半導体装置 |
US6246112B1 (en) * | 1998-06-11 | 2001-06-12 | Intel Corporation | Interleaved signal trace routing |
JP2000100814A (ja) * | 1998-09-18 | 2000-04-07 | Hitachi Ltd | 半導体装置 |
JP2002110805A (ja) * | 2000-09-28 | 2002-04-12 | Toshiba Corp | 半導体デバイス |
US6591410B1 (en) * | 2000-12-28 | 2003-07-08 | Lsi Logic Corporation | Six-to-one signal/power ratio bump and trace pattern for flip chip design |
JP2002299512A (ja) * | 2001-03-30 | 2002-10-11 | Nec Corp | 半導体装置及びその製造方法 |
TW511193B (en) * | 2001-12-13 | 2002-11-21 | Acer Labs Inc | Inner circuit structure of array type bonding pad chip and its manufacturing method |
JP4313544B2 (ja) * | 2002-05-15 | 2009-08-12 | 富士通マイクロエレクトロニクス株式会社 | 半導体集積回路 |
JP2005093575A (ja) * | 2003-09-16 | 2005-04-07 | Nec Electronics Corp | 半導体集積回路装置と配線レイアウト方法 |
-
2003
- 2003-06-10 DE DE60336993T patent/DE60336993D1/de not_active Expired - Lifetime
- 2003-06-10 EP EP03425368A patent/EP1487015B1/de not_active Expired - Lifetime
-
2004
- 2004-06-09 US US10/864,901 patent/US7126230B2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
EP1487015B1 (de) | 2011-05-04 |
US7126230B2 (en) | 2006-10-24 |
EP1487015A1 (de) | 2004-12-15 |
US20050035468A1 (en) | 2005-02-17 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
DE602004017675D1 (de) | Vertikale Halbleitervorrichtung und Verfahren zu deren Herstellung | |
DE602005021303D1 (de) | Elektronische Schaltungsanordnung und Verfahren zu deren Herstellung. | |
DE60313843D1 (de) | Halbleiterlaservorrichtung und Verfahren zu deren Herstellung | |
DE60324376D1 (de) | Halbleiterbauelement und Verfahren zu dessen Herstellung | |
DE60325690D1 (de) | Halbleiterbauelement und verfahren zu seiner herstellung | |
DE60038216D1 (de) | Lichtemittierende Halbleitervorrichtung und Verfahren zu deren Herstellung | |
DE602004021927D1 (de) | Halbleiterbauelement und verfahren zu seiner herstellung | |
DE60113215D1 (de) | Halbleitervorrichtung und Verfahren zu dessen Herstellung | |
DE60324755D1 (de) | Verpackungsstruktur für elektronische Bauteile und Methode zu deren Herstellung | |
DE602004015020D1 (de) | Harzverkapselter elektronischer Bauteil und Verfahren zu seiner Herstellung | |
DE602004009821D1 (de) | Halbleiterbauelement und Herstellungsverfahren dafür | |
FI20022282A0 (fi) | Menetelmä vuorovaikutuksen mahdollistamiseksi elektronisessa laitteessa ja elektroninen laite | |
DE60337036D1 (de) | Halbleiterbauelement und verfahren zu seiner herstellung | |
ATE422775T1 (de) | Verfahren und vorrichtung zur zellenverkapselung | |
DE60324868D1 (de) | Träger für elektronische Vorrichtungen, dessen Verfahren zur Herstellung, und elektronische Vorrichtung | |
FI20031201A0 (fi) | Menetelmä elektroniikkamoduulin valmistamiseksi ja elektroniikkamoduuli | |
DE60322576D1 (de) | Anbringvorrichtung und verfahren für elektronische teile | |
DE50307293D1 (de) | Halbleiterbauelement mit integrierter kapazitätsstruktur und verfahren zu dessenherstellung | |
DE60313797D1 (de) | Halbleiter-Lichtemissionsbauelement und Verfahren zu seiner Herstellung | |
DE60223746D1 (de) | Elektrooptische Vorrichtung, Verfahren zu deren Herstellung und elektronisches Gerät | |
FI20030293A (fi) | Menetelmä elektroniikkamoduulin valmistamiseksi ja elektroniikkamoduuli | |
DE60219502D1 (de) | Gerät und verfahren zur eichung und validierung von hochleistungs-stromversorgungen für testgeräte | |
DE60239493D1 (de) | Halbleiterbauelement und verfahren zu seiner herstellung | |
DE602004009841D1 (de) | Diffusionsplatte und Verfahren zu deren Herstellung | |
DE50313373D1 (de) | Optisch gepumpte strahlungsemittierende halbleitervorrichtung und verfahren zu deren herstellung |