JP2005243787A - 高周波モジュール - Google Patents
高周波モジュール Download PDFInfo
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- JP2005243787A JP2005243787A JP2004049554A JP2004049554A JP2005243787A JP 2005243787 A JP2005243787 A JP 2005243787A JP 2004049554 A JP2004049554 A JP 2004049554A JP 2004049554 A JP2004049554 A JP 2004049554A JP 2005243787 A JP2005243787 A JP 2005243787A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15192—Resurf arrangement of the internal vias
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
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- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Transceivers (AREA)
- Die Bonding (AREA)
Abstract
【解決手段】誘電体基板2表面にパワーアンプなどの半導体素子4を実装する際、粒径が20nm以下の銀粒子を300℃以下の温度で溶着した有機樹脂を含まない高熱伝導の溶融銀層15をもって実装することにより、熱抵抗を低減し、熱伝導度と放熱性を向上することが出来るため、パワーアンプの効率向上、モジュール内の温度低減を達成できる。
【選択図】図1
Description
表1に示す溶融温度の半田(SnSb=280℃、SnAgBi=235℃)をスクリーン印刷法にて塗布し、圧電体からなる表面弾性波素子のチップスケールパッケージ、およびチップコンデンサ、チップインダクタなどの表面実装部品を搭載した後、上記溶融温度の窒素雰囲気にてリフロー実装を行った。
ディスペンサーにて平均粒径が表1に示すような種々の銀粒子を準備し、この銀粒子100質量部にブタノールを30質量部の割合で添加混合してAgペースト1を調製した。
2・・・・誘電体基板
3・・・・表面実装部品
4・・・・半導体素子
5・・・・導体層 圧電体からなる表面弾性波素子
6・・・・ビア導体
9・・・・サーマルビア
13・・・・半田
15・・・・溶融銀層
Claims (10)
- 誘電体基板表面に、表面実装部品と、半導体素子を実装搭載してなる高周波モジュールであって、前記表面実装部品が半田層を介して実装され、前記半導体素子が実質的に有機分を含まない溶融銀層を介して実装されていることを特徴とする高周波モジュール。
- 前記溶融銀層は、平均粒径が20nm以下の銀粒子を溶着して形成してなる請求項1記載の高周波モジュール。
- 前記溶融銀層は、300℃以下の温度で形成したことを特徴とする請求項第1または請求項2記載の高周波モジュール。
- 前記溶融銀層の熱伝導率が200W/m・K以上であることを特徴とする請求項第1乃至請求項3のいずれか記載の高周波モジュール。
- 前記表面実装部品が、チップコンデンサ、チップインダクタ、チップ抵抗素子、表面弾性波素子、FBAR、BAWの群から選ばれる少なくとも1つであることを特徴とする請求項第1乃至請求項4のいずれか記載の高周波モジュール。
- 前記半導体素子が、パワーアンプ、スイッチ、パワーコントロール、検波、電源コントロールの群から選ばれる少なくとも1つであることを特徴とする請求項1乃至請求項5のいずれか記載の高周波モジュール。
- 前記誘電体基板表面に実装された前記表面実装部品および前記半導体素子を熱硬化性樹脂で気密封止してなることを特徴とする請求項1乃至請求項6のいずれか記載の高周波モジュール。
- 前記誘電体基板の表面およびまたは内部に、分波回路、合波回路、カプラ、バラン、フィルタの少なくとも1つの受動回路が形成されてなることを特徴とする請求項1乃至請求項7のいずれか記載の高周波モジュール。
- 前記半田層が、250℃よりも低い温度で形成されることを特徴とする請求項1乃至請求項8のいずれか記載の高周波モジュール。
- 前記半田層が、300℃以下、250℃以上の温度で形成されることを特徴とする請求項1乃至請求項8のいずれか記載の高周波モジュール。
Priority Applications (1)
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JP2004049554A JP4484544B2 (ja) | 2004-02-25 | 2004-02-25 | 高周波モジュールの製造方法 |
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JP2004049554A JP4484544B2 (ja) | 2004-02-25 | 2004-02-25 | 高周波モジュールの製造方法 |
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JP2005243787A true JP2005243787A (ja) | 2005-09-08 |
JP4484544B2 JP4484544B2 (ja) | 2010-06-16 |
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JP2004049554A Expired - Fee Related JP4484544B2 (ja) | 2004-02-25 | 2004-02-25 | 高周波モジュールの製造方法 |
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Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008135594A (ja) * | 2006-11-29 | 2008-06-12 | Kyocera Corp | 微小電子機械部品封止用基板及び複数個取り形態の微小電子機械部品封止用基板、並びに微小電子機械装置及び微小電子機械装置の製造方法 |
CN101938286A (zh) * | 2009-06-30 | 2011-01-05 | 株式会社村田制作所 | 复合电子元器件模块 |
JP2012028613A (ja) * | 2010-07-26 | 2012-02-09 | Sumitomo Electric Device Innovations Inc | 半導体装置 |
JP2012182395A (ja) * | 2011-03-02 | 2012-09-20 | Taiyo Yuden Co Ltd | 電子デバイス |
WO2019132941A1 (en) * | 2017-12-28 | 2019-07-04 | Intel Corporation | Hybrid filter having an acoustic wave resonator embedded in a cavity of a package substrate |
US11245977B2 (en) | 2014-12-09 | 2022-02-08 | Snaptrack, Inc. | Electric component with sensitive component structures and method for producing an electric component with sensitive component structures |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001119130A (ja) * | 1999-10-15 | 2001-04-27 | Ebara Corp | 電気接点の接合方法 |
JP2002126869A (ja) * | 2000-10-25 | 2002-05-08 | Harima Chem Inc | 金属間のロウ付け接合方法 |
JP2004058088A (ja) * | 2002-07-26 | 2004-02-26 | Ebara Corp | 接合方法及び接合体 |
JP2005129303A (ja) * | 2003-10-22 | 2005-05-19 | Denso Corp | 導体組成物および導体組成物を用いた実装基板ならびに実装構造 |
-
2004
- 2004-02-25 JP JP2004049554A patent/JP4484544B2/ja not_active Expired - Fee Related
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001119130A (ja) * | 1999-10-15 | 2001-04-27 | Ebara Corp | 電気接点の接合方法 |
JP2002126869A (ja) * | 2000-10-25 | 2002-05-08 | Harima Chem Inc | 金属間のロウ付け接合方法 |
JP2004058088A (ja) * | 2002-07-26 | 2004-02-26 | Ebara Corp | 接合方法及び接合体 |
JP2005129303A (ja) * | 2003-10-22 | 2005-05-19 | Denso Corp | 導体組成物および導体組成物を用いた実装基板ならびに実装構造 |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008135594A (ja) * | 2006-11-29 | 2008-06-12 | Kyocera Corp | 微小電子機械部品封止用基板及び複数個取り形態の微小電子機械部品封止用基板、並びに微小電子機械装置及び微小電子機械装置の製造方法 |
CN101938286A (zh) * | 2009-06-30 | 2011-01-05 | 株式会社村田制作所 | 复合电子元器件模块 |
JP2011014659A (ja) * | 2009-06-30 | 2011-01-20 | Murata Mfg Co Ltd | 複合電子部品モジュール |
JP2012028613A (ja) * | 2010-07-26 | 2012-02-09 | Sumitomo Electric Device Innovations Inc | 半導体装置 |
JP2012182395A (ja) * | 2011-03-02 | 2012-09-20 | Taiyo Yuden Co Ltd | 電子デバイス |
US11245977B2 (en) | 2014-12-09 | 2022-02-08 | Snaptrack, Inc. | Electric component with sensitive component structures and method for producing an electric component with sensitive component structures |
WO2019132941A1 (en) * | 2017-12-28 | 2019-07-04 | Intel Corporation | Hybrid filter having an acoustic wave resonator embedded in a cavity of a package substrate |
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JP4484544B2 (ja) | 2010-06-16 |
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