WO2019132941A1

WO2019132941A1 - Hybrid filter having an acoustic wave resonator embedded in a cavity of a package substrate

Info

Publication number: WO2019132941A1
Application number: PCT/US2017/068814
Authority: WO
Inventors: Georgios C. Dogiamis; Telesphor Kamgaing; Feras EID; Vijay K. Nair; Johanna M. Swan
Original assignee: Intel Corporation
Priority date: 2017-12-28
Filing date: 2017-12-28
Publication date: 2019-07-04

Abstract

A hybrid filter having an acoustic wave resonator embedded in a cavity of a package substrate is described. In an example, a packaged system includes a package substrate having a die side and a land side opposite the die side. An active die is physically and electrically coupled to the die side of the package substrate. An acoustic wave resonator (AWR) device is in a cavity on the die side of the package substrate, the AWR device including an acoustic wave resonator (AWR) die. The AWR die includes an acoustic wave resonator wherein the AWR device is directly electrically coupled to the active die.

Description

HYBRID FILTER HAVING AN ACOUSTIC WAVE RESONATOR EMBEDDED IN A

CAVITY OF A PACKAGE SUBSTRATE

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to hybrid filters and more particularly to a hybrid filter having an acoustic wave resonator embedded in a cavity of a package substrate.

BACKGROUND

[0002] Filters operating at microwave frequencies are important for today’s and next generation mobile and wireless communication devices and infrastructure. In 5G networks, for example, the amount of data to be generated and exchanged between user terminals and networks will increase substantially in comparison to 3G and 4G networks. The implementation of wireless access points for machine to machine communication will add to the already high number of filters that are being used in radio front end modules today. New multi-radio platforms will require the use of highly selective filters with low passband insertion loss to guarantee the required signal integrity. Additionally, the filters will need broad frequency bandwidth to enable wireless high speed data transfer. In fact, each user’s terminal device should be able to process data at speeds averaging about 1 Gigabit per second with network latency below 10 ms. Broadband radio frequency (RF) filters will be required to achieve the desired data rate without an increase in the network latency because they can enable architectures with relatively low order modulation schemes.

BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Fig. 1 is an illustration of a cross-sectional view of a packaged system in accordance with an embodiment of the present disclosure.

[0004] Fig. 2 is an illustration of a cross-sectional view of a packaged system in accordance with an embodiment of the present disclosure. [0005] Fig. 3 is an illustration of a cross-sectional view of a packaged system in accordance with an embodiment of the present disclosure.

[0006] Fig. 4 is a schematic illustration of a RF front end system or module in accordance with an embodiment of the present disclosure.

[0007] Fig. 5 is a schematic illustration of an RF hybrid circuit or filter in accordance with an embodiment of the present disclosure.

[0008] Fig. 6A and Fig. 6B illustrate various capacitors which may be integrated or embedded into a package substrate, in accordance with embodiments of the present disclosure.

[0009] Figs. 7A-7F illustrate various inductors which may be embedded into a package substrate in accordance with embodiments of the present disclosure.

[0010] Fig. 8 is a schematic block diagram illustrating a computer system that utilizes a packaged system as described herein, in accordance with an embodiment of the present disclosure.

EMBODIMENTS OF THE PRESENT DISCLOSURE

[0011] A hybrid filter having an acoustic wave resonator device embedded in a cavity of a package substrate is described. In the following description, numerous specific details are set forth, such as specific material and structural regimes, in order to provide a thorough

understanding of embodiments of the present disclosure. It will be apparent to one skilled in the art that embodiments of the present disclosure may be practiced without these specific details.

In other instances, well-known features are not described in detail in order to not unnecessarily obscure embodiments of the present disclosure. Furthermore, it is to be understood that the various embodiments shown in the Figures are illustrative representations and are not necessarily drawn to scale. In some cases, various operations will be described as multiple discrete operations, in turn, in a manner that is most helpful in understanding the present disclosure, however, the order of description should not be construed to imply that these operations are necessarily order dependent. In particular, these operations need not be performed in the order of presentation.

[0012] Certain terminology may also be used in the following description for the purpose of reference only, and thus are not intended to be limiting. For example, terms such as“upper”, “lower”,“above”,“below,”“bottom,”“top,”“over,” and“under” refer to directions in the drawings to which reference is made. Terms such as“front”,“back”,“rear”, and“side” describe the orientation and/or location of portions of the component within a consistent but arbitrary frame of reference which is made clear by reference to the text and the associated drawings describing the component under discussion. Such terminology may include the words specifically mentioned above, derivatives thereof, and words of similar import.

[0013] Embodiments of the present disclosure relate to hybrid filters including an acoustic wave resonator device located in a cavity of a package substrate. In embodiments of the present disclosure, a packaged system includes a package substrate having a die side and a land side opposite the die side. A cavity is formed in the die side of the package substrate. An acoustic wave resonator (AWR) device including an acoustic wave resonator (or resonator) may be disposed in the cavity. In an embodiment, one or more passive devices, such as resistors, capacitors, inductors and transformers, may be embedded in the package substrate. In an embodiment, a component, such as an active die or main die, may be electrically and physically coupled to the die side of the package substrate. The active die may be in direct electrical contact with the AWR device by, for example, one or more flip-chip connections, solder balls or bumps, bond wires, and/or direct metal traces. The active die may include RF active circuits, such as amplifiers, switches, and matching networks, and may also include embedded passives, such as resistors, capacitors, and inductors. In an embodiment, the AWR die in the package substrate enables shorter connections to be made between the AWR device and the active die which may reduce unwanted parasitics coming from the added interconnects needed to connect between different substrates. [0014] In an embodiment, a second component, such as an integrated passive device

(IPD) may be physically and electrically coupled to the die side of the package substrate. The IPD may include one or more high quality factor (high Q) passive devices, such as resistors, capacitors, inductors and transformers. The IPD may be electrically coupled to the AWR device by, for example, one or more flip-chip connections, solder ball connections, wire bonds, or direct metal traces. In an embodiment, the AWR device may act as a bridge to enable direct electrical connection between one component, such as an active die, and a second component, such as an IPD, without needing to route through the package substrate.

[0015] In an embodiment, the passive devices disposed in the active die and/or the IPD and/or the package substrate and the resonator of the AWR device may be electrically coupled together to create a filter, such as a hybrid filter, in a single package. In other embodiments, the filter may be coupled with active circuits in the active die to create an RF front system or module all integrated and coupled together in a single package.

[0016] Fig. 1 is an illustration of a cross-sectional view of a packaged system 100 in accordance with an embodiment of the present disclosure. Packaged system 100 includes a package substrate 102. An acoustic wave resonator (AWR) device 104 having a resonator 106 may be disposed in a cavity 108 formed in package substrate 102. In an embodiment, a first device, such as an active die or a main die 110, may be coupled to the package substrate 102 as well as to AWR device 104, as illustrated in Fig. 1. In an embodiment, a second device, such as an integrated passive device (IPD) 112, may be electrically and physically coupled to package substrate 102. In an embodiment, IPD 112 may be electrically coupled to AWR device 104. In an embodiment, AWR device provides a direct electrical connection between IPD 112 and active die 110 without routing into package substrate 102.

[0017] Package substrate 102 may be any suitable package substrate. In an embodiment, package substrate 102 is an organic multilayered printed circuit board including a dielectric material such as but not limited to silica-filled epoxy resins, fiberglass-reinforced epoxy laminates (FR4), or polyimide. In an embodiment, package substrate 102 is a ceramic substrate, such as a low temperature co-fired ceramic (LTCC) substrate. In an embodiment, package substrate 102 is a multilayered package substrate which includes a plurality of metallization layers 140, such as copper layers each comprising a plurality of electrical traces 143 or power planes. Each metallization layer 140 may be separated from adjacent metallization layers 140 by one or more dielectric layers 142. Conductive vias 144 may be disposed in dielectric layers 142 to enable electrical connection from one metallization layer to another. In an embodiment, when conductive vias 144 are formed by, for example, a process which includes laser drilling, the vias may have a conical shape as illustrated in Fig. 1.

[0018] In an embodiment, package substrate 102 includes one or more inductors 150 embedded therein as illustrated in Fig. 1. Inductor 150 may be a partial loop inductor, a single loop inductor or a multi loop inductor fabricated in a single level or multiple levels of package substrate 102 as described in more detail with respect to Figs. 7A-7F. In an embodiment, inductor 150 may consist of one or more turns of conductive material, such as copper, separated by a dielectric such as a polymer, a ceramic, a glass, or air. In one embodiment, the one or more turns of conductive material are separated by dielectric 142 of package substrate 102. In an embodiment, inductor 150 may be electrically coupled by an electrical connection to resonator 106. In an embodiment of the present disclosure, inductor 150 may be part of a network of inductors including a transformer equivalent circuit, such as a Pi-network or a T-network.

[0019] In an embodiment, package substrate 102 may include one or more capacitors 152 embedded therein. Capacitor 152 may be a parallel plate capacitor or an interdigitated capacitor and may be fabricated in a single metallization layer 140 or in multiple metallization layers 140 of package substrate 102 as described in more detail with respect to Fig. 6A and 6B. In an embodiment, capacitor 152 may be electrically coupled to resonator 106 of AWR device 104. In an embodiment, capacitor 152 may be electrically coupled by an electrical connection to inductor 150.

[0020] In an embodiment of the present disclosure, package substrate 102 includes one or more transformers 154 embedded therein. In an embodiment, transformer 154 has a first winding 156 and a second winding 158 wherein the first winding 156 and the second winding 158 are inductively coupled. In an embodiment, first winding 156 is vertically above second winding 158, as illustrated in Fig. 1. In an embodiment, first winding 156 and second winding 158 are substantially aligned with one another. In another embodiment, first winding 156 has a central axis which is slightly offset from a central axis of second winding 158 in order to reduce a coupling coefficient of transformer 154. In an embodiment, first winding 156 is a planar winding fabricated in a single metallization layer 140 of package substrate 102 and second winding 158 is a planar winding fabricated in a second different metallization layer 140 of package substrate 102. In an embodiment, first winding 156 is separated from second winding 158 by a vertical distance between 15 microns and 60 microns. In an embodiment, first winding 156 and second winding 158 may each be fabricated in multiple metal layers of package substrate 102 in order to create high quality factor (high Q) inductors for transformer 154. In an embodiment, first winding 156 may be electrically coupled to a capacitor 152 embedded within package substrate 102. In an embodiment, second winding 158 may be electrically coupled to another capacitor 152 embedded in package substrate 102. In an embodiment, transformer 154 may be a vertical transformer where first winding 156 and second winding 158 are fabricated in multiple metallization layers 140 of package substrate 102. In an embodiment, first winding 156 and second winding 158 may be interleaved with one another. In an embodiment, the vertical transformer has an implementation where a vertical axes of first winding 156 and second winding 158 are not aligned and are offset to provide a mutual coupling adjustment.

[0021] In an embodiment, package substrate 102 has a die side 164 and a land side or second level interconnect (SLI) side 166. A plurality of contact pads 168 are disposed on die side 164. In an embodiment, contacts 162, such as flip chip connections, solder balls, and/or solder bumps may electrically couple contact pads 183 on active die 110 to corresponding contact pads 168 on package substrate 102. Contacts 163, such as flip chip connections, solder balls and/or solder bumps, may electrically couple contact pads 192 on IPD 112 to corresponding contact pads 168 on package substrate 102 as, illustrated in Fig. 1. Land side 166 of package substrate 102 may include a plurality of contact pads or land pads 170. A plurality of second level contacts 172, such as solder balls or solder bumps may be disposed on contact pads 170 to enable packaged system 100 to be electrically coupled to other components, such as a mother board or main board. In an embodiment, package substrate 102 may include one or more discrete inductors and/or one or more discrete capacitors, resistors or inductors attached to die side 164 or land side 166 of package substrate 102 (not shown).

[0022] In an embodiment, AWR device 104 includes an acoustic wave resonator (AWR) die 120 and an acoustic wave resonator (AWR) cap 122. The AWR cap 122 is attached to the AWR die 120 by a seal ring or frame 121. AWR die 120 includes acoustic wave resonator (or resonator) 106. In an embodiment, the AWR die includes a substrate 124 and an interconnect structure 126 disposed on substrate 124. Substrate 124 may be any suitable substrate, such as but not limited to a semiconductor substrate, such as a silicon substrate, a group III-V semiconductor substrate, a glass substrate, or a ceramic substrate. Interconnect structure 126 may include multiple levels of metallization separated by dielectric layers and interconnected by conductive vias to enable electrical signal coupling between the AWR device 104 and other components, such as other components of a hybrid filter. In an embodiment, resonator 106 may be formed in interconnect structure 126 of AWR die 120 as illustrated in Fig. 1. In an embodiment, one or more capacitors may be embedded in interconnect structure 126. The capacitors may take the form of parallel plate capacitors, interdigitated capacitors, and metal-insulator-metal (MIM) capacitors. In an embodiment, an electrode of resonator 106 is coupled to a capacitor in interconnect structure 126. Although a single resonator 106 is illustrated in Fig. 1, it is to be appreciated that multiple resonators 106 may be fabricated in a single AWR die 120. Such multiple resonators may have a same or different resonance frequency.

[0023] Resonator 106 may be any well known acoustic wave resonator such as, but not limited to, a thin film bulk acoustic wave resonator (FBAR), a solidly mounted resonator (SMR), a countour-mode resonator (CMR), a composite longitudinal mode resonator (CLMR) or a surface acoustic wave (SAW) device. In an embodiment of the present disclosure resonator 106 is a thin film bulk acoustic resonator having a piezoelectric material 130 sandwiched between a first electrode 132 and a second electrode 134. The piezoelectric material 134 may be any suitable piezoelectric material, such as but not limited to aluminum nitride, zinc oxide, lead zirconium titanate (PZT), and sodium potassium niobate (KNN), or the like. In an embodiment, the piezoelectric material 130 may have a thickness ranging from several micrometers down to a few hundredths of a micrometer. In an embodiment, acoustic wave resonator 106 has a resonance frequency or may resonate at a frequency between 10 MHz to 10 GHz. In an embodiment, resonator 106 includes a cantilever portion and an anchored portion. In an embodiment, the cantilever portion extends under a cavity disposed in interconnect structure 126 in order to enable the cantilever portion to translate between 0.1-3 microns.

[0024] In an embodiment, cap 122 is attached to interconnect structure 126 by seal ring or frame 121. Seal ring or frame 121 completely surrounds resonator 106 and creates a hermetic seal between interconnect structure 126 and cap 122 as illustrated in Fig. 1. Seal ring or frame 121 forms a hermetic and acoustically sealed air cavity 107 around resonator 106 which protects resonator 106 from environmental conditions and interference. Seal ring or frame 121 may be made from a metal, such as but not limited to gold, copper, tin or indium. In other embodiments, seal ring or frame 121 may be made of an insulating material, such as but not limited to a glass frit, a polymer, a liquid crystal polymer or an inorganic dielectric. In an embodiment, seal ring or frame 121 may have a thickness between 0.5-10 microns. In an embodiment, seal ring or frame 121 includes a metal ring or frame disposed on the outer surface of interconnect structure 126 and a metal ring or frame on cap 122. The metal rings or frames may then be directly bonded together by, for example, diffusion bonding or may be bonded together by an intermediate solder layer, such as an eutectic solder (e.g., gold/tin). Cap 122 may be formed from a semiconductor, such as high resistivity silicon or low resistivity silicon, a ceramic, or a glass.

[0025] In an embodiment, AWR device 104 may have a thickness between 50 microns to

300 microns. In an embodiment, resonator 106 may have an x-y size between 50 micron by 50 microns to 500 microns by 500 microns. In an embodiment, cavity 108 may have a depth between 50 microns to 300 microns. In an embodiment, AWR die 120 is situated in cavity 108 and has a top surface substantially co-planar with a top surface of package substrate 102. In this way, contacts 162 connecting active die 110 to AWR device 104 and coupling active die 110 to package substrate 102 may be the same size, as illustrated in Fig. 1. Similarly, this enables contacts 163 connecting IPD 112 to AWR device 104 and coupling IPD 112 to package substrate 102 may be the same size, as illustrated in Fig. 1. In an embodiment, cap 122 extends above die side 164 of package substrate 102, as illustrated in Fig. 1. In an embodiment, a dielectric layer 138 may be disposed over AWR die 120 and between sidewalls of AWR die 120 and package substrate 102, as illustrated in Fig. 1. In an embodiment, dielectric layer 138 may seal AWR die 120 in cavity 108. In an embodiment, dielectric layer 138 is disposed on a top surface interconnect structure 126 and includes openings which expose contact pads of AWR die 120. In an embodiment, dielectric layer 138 may be a nonconductive epoxy based organic dielectric. In an embodiment, dielectric layer 138 may be applied after the AWR device 104 is placed in cavity 108.

[0026] In an embodiment of the present disclosure, the bottom of cavity 108 may contain a metal plate or metal shield 145. Metal plate or metal shield 145 may be fabricated from a metallization layer 140 of package substrate 102, as illustrated in Fig. 1. In an embodiment, metal plate 145 may be grounded to provide an electromagnetic interference (EMI) shield. In an embodiment, an adhesive may be applied to the bottom of cavity 108 to secure AWR device 104 in cavity 108.

[0027] In an embodiment, active die 110 includes a semiconductor substrate 180 and an interconnect structure 182. In an embodiment, semiconductor substrate 180 may be a semiconductor substrate, such as but not limited to a silicon substrate, a silicon carbide substrate, or a group III-V semiconductor substrate, such as but not limited to gallium nitride (GaN), gallium arsenide (GaAs), and indium phosphide (InP). In an embodiment, substrate 180 is a monocrystalline silicon substrate. In another embodiment, substrate 180 is a gallium nitride substrate.

[0028] In an embodiment, semiconductor substrate 180 includes active devices 184, such as but not limited to diodes and/or transistors, disposed in or on a front side or active side of semiconductor substrate 180. Interconnect structure 182 may electrically couple devices, such as transistors, fabricated in or on semiconductor substrate 180 into front end active circuits, such as but not limited to power amplifiers, low noise amplifiers, matching networks, and switches. Additionally, in an embodiment, semiconductor substrate 180 may include CMOS transistors interconnected together to form functional circuits, such as functional circuits of an applications processor.

[0029] Interconnect structure 182 may be disposed on the front side of substrate 180. In an embodiment, interconnect structure 182 is a multilayer interconnect structure including multiple metallization layers separated by dielectric layers. Conductive vias may electrically connect one level of metallization to another level of metallization. Each of the metallization layers may contain a plurality of metal interconnects used to route signals and power to various devices on or in active die 110. The metallization layers may be formed from any suitable metal or stack of metals, such as but not limited to copper, aluminum, gold, cobalt, titanium nitride, and tantalum nitride. Dielectric layers may be formed from any suitable dielectric or stack of dielectrics, such as but not limited to polyimide, BCB, silicon oxide, carbon doped silicon oxide, silicon oxynitride, and silicon nitride. It is to be appreciated that interconnect structure 182 may contain many metallization layers and dielectric layers, such as between 6-14 metallization layers with corresponding dielectric layers, depending upon the complexity and number of elements or devices to be coupled together. Metallization layers and conductive vias may be fabricated any well known processes, such as but not limited to damascene and dual damascene processes.

[0030] In an embodiment, one or more capacitors 186 may be disposed in interconnect structure 182. Capacitor 186 may be any suitable capacitor, such as but not limited to a parallel plate capacitor, a metal insulator metal (MIM) capacitor, an interdigitated capacitor and/or a trench capacitor. Capacitor 186 may include a capacitor dielectric which may be an organic or inorganic material, such as a silica filled epoxy, silicon nitride, silicon oxide, barium titanate, titanium oxide, or lead zirconium titanate. Capacitor 186 may have a form as described in greater detail below in association with Figs. 6A and 6B. In an embodiment, capacitor 186 is electrically coupled by an electrical connection to resonator 106.

[0031] In an embodiment, interconnect structure 182 may include one or more inductors

187. Inductor 187 may be a partial loop inductor, a single loop inductor, or a multi loop inductor fabricated in single level or multiple levels of interconnect structure 182, and as further described in more detail with respect to Figs. 7A-7F. In an embodiment, inductor 187 is electrically coupled by an electrical connection to resonator 106. In an embodiment, inductor 187 may consist of one or more turns of conductive material, such as copper, separated by a dielectric such as a polymer, a ceramic, a glass, or air. In one embodiment, the one or more turns of conductive material are separated by a dielectric layer of interconnect structure 182.

[0032] In an embodiment, interconnect structure 182 includes one or more transformers

188 embedded therein. In an embodiment, transformer 188 includes a first winding and a second winding wherein the first winding and the second winding are inductively coupled. In an embodiment, the first winding is vertically above the second winding, as illustrated in Fig. 1. In an embodiment, the first winding and the second winding are aligned with one another. In another embodiment, the first winding is slightly offset from a central axis of the second winding in order to reduce the coupling coefficient of transformer 188. In an embodiment, the first winding is fabricated in a single metallization layer of interconnect structure 182 and the second winding is a planar winding fabricated in a second different metallization layer of interconnect structure 182. In an embodiment, the first winding and second winding may each be fabricated in multiple layers of interconnect structure 182 in order to create high quality factor (high Q) inductors for transformer 188. In an embodiment, the first winding may be electrically coupled to a capacitor 186 embedded within interconnect structure 182. In an embodiment, the second winding may be electrically coupled to another capacitor 186 embedded in interconnect structure 182.

[0033] In an embodiment, IPD 112 may be bonded to contact pads 168 on die side 164 of package substrate 102 by a plurality of contacts 163, such as flip-chip connections, solder balls or bumps. IPD 112 may include one or more capacitors, resistors, or inductors disposed therein. IPD 112 may be fabricated with a process and/or materials which enabled high quality passive devices, such as inductors and capacitors to be fabricated therein. IPD 112 may be particularly beneficial when package substrate 102 is fabricated from a type of substrate, such as a high density interconnect (HDI) printed circuit board, where making high quality capacitors and inductors may be too difficult or expensive. In an embodiment, IPD 112 contains only passive devices and does not include any active devices, such as diodes and/or transistors. In an embodiment, IPD 112 contains only capacitors. In an embodiment, IPD 112 is fabricated from a glass substrate or a semiconductor substrate, such as a silicon substrate. In an embodiment, IPD 112 may include an interconnect structure disposed on the substrate.

[0034] In an embodiment, active die 110 may be directly electrically connected to AWR device 104 by one or more contacts 162, such as flip-chip connections, solder balls or solder bumps. One or more solder balls or solder bumps 162 may connect a corresponding bond pad 183 on active die 110 to a corresponding bond pad 127 on AWR device 104, as illustrated in Fig. 1. In an embodiment, active die 110 may be electrically coupled to an electrode of resonator 106, as illustrated in Fig. 1. Because AWR device 104 is recessed into cavity 108 as illustrated in Fig. 1, active die 110 may be electrically coupled to AWR device 104 by a short electrical contact which may reduce parasitics and improve performance of packaged system 100.

[0035] In an embodiment of the present disclosure, IPD 112 may be directly electrically connected to AWR die 104 by one or more contacts 163, such as flip-chip connections, solder balls or solder bumps. In an embodiment, one or more solder balls 163 electrically couples to corresponding contact pads 192 on IPD 112 to a corresponding contact pad 127 on AWR device 104. In an embodiment, IPD 112 may be electrically coupled to an electrode of resonator 106. Because AWR device 104 is recessed into cavity 108 as illustrated in Fig. 1, IPD 112 may be electrically coupled to the AWR device 104 by a short contact which may reduce parasitics and improve performance of the packaged system 100.

[0036] In an embodiment, AWR device 104 provides one or more direct electrical connections or a bridge between active die 110 and IPD 112 without routing into package substrate 102. In this way, AWR device 102 may provide a direct electrical connection between high quality passives on IPD 112 and active circuits, such as amplifiers and switches, on active die 110. Electrically connecting IPD 112 and active die 110 through AWR device 104 may enable shorter interconnection lengths to be made than if the interconnection were routed through the package substrate 102 and thereby may reduce parasitics and improve performance.

[0037] Fig. 2 is an illustration of a cross-sectional view of a packaged system 200 in accordance with an embodiment of the present disclosure. Packaged system 200 is similar to packaged system 100, as represented by, for example, like reference numerals, except that packaged system 200 may utilize or include wire bonds for making electrical connections to package substrate 102 and AWR device 104. For example, active die 110 may be attached to substrate 102 in a face-up configuration where the active side of active die 110 faces away from package substrate 102 as illustrated in Fig. 2. Packaged system 200 may include one or more wire bonds 210 which may make electrical connection between active die 110 and AWR device 104, such as between bond pads 183 and corresponding bond pads 127, as illustrated in Fig. 2. Additionally, packaged system 200 may include one or more wire bonds 212 which make electrical connection between active die 110 and package substrate 102, such as between bond pads 183 and corresponding bond pads 168. By recessing AWR device 104 into cavity 108 disposed in package substrate 102, the lateral wire length of bond wire 210 may be lower than with a traditional wire bonding architecture (e.g., AWR device 104 placed directly on package substrate 102 without a cavity). In an embodiment, the wire bond 210 to AWR device 104 may have a reduced length of, for example, 50 microns to 500 microns, which may translate up to 0.5nH total parasitic induction reduction. [0038] Additionally, in an embodiment, packaged system 200 may include one or more wire bonds 214 which make electrical connections between IPD 112 and package substrate 104, such as between bond pads 192 and corresponding bond pads 168, as illustrated in Fig. 2.

Additionally, in an embodiment, packaged system 200 may include one or more wire bonds (not shown) which directly electrically connect IPD 112 to AWR device 104. In an embodiment, package substrate 102 may include one or more common bond pads 230 to which both AWR device 104 and another component, such as active die 110 or IPD 112, may be coupled. For example, as illustrated in Fig. 2, packaged system 200 may include a wire bond 216 which electrically couples IPD 112 to common bond pad 230. Additionally, packaged system 230 may include a wire bond 218 which electrically connects AWR device 104 to common bond pad 230, as illustrated in Fig. 2. By locating AWR device 104 in cavity 108 of package substrate 102, the length of bond wire 218 may be reduced enabling a shorter coupling distance to IPD 112 as well as to package substrate 102 and passive devices, such as passive devices 150, 152, and 154, embedded therein. In this way, parasitics may be reduced and performance improved. In an embodiment, resonator 106 may be electrically coupled in parallel to inductor 150 embedded in package substrate 102. The AWR device 104 can act as a bridge to interconnect between other system components, such as IPD 112 and active die 110, however, by still using wire bonding to interconnect.

[0039] Fig. 3 is an illustration of a cross-sectional view of a packaged system 300 in accordance with an embodiment of the present disclosure. Packaged system 300 is similar to packaged systems 100 and 200 as represented by, for example, like reference numerals. In an embodiment, packaged system 300 includes one or more short lateral traces to interconnect components, such as but not limited to IPD 112 and/or active die 110 to AWR device 104. For example, as illustrated in Fig. 3, a metal trace 310, such as a copper trace, may connect IPD 112 to AWR device 104. In a specific embodiment, metal trace 310 may electrically connect a bond pad 168 on package substrate 102 to which IPD die 112 is coupled to a bond pad 127 on AWR device 104, as illustrated in Fig. 3. In an embodiment, metal trace 310 is formed over package substrate 102, AWR die 120, and over dielectric 138 between AWR die 120 and package substrate 104. Due to the cavity placement of AWR device 104, a metal trace or traces can be deposited instead of using a wire bond which may further reduce parasitics and ease assembly.

In an embodiment, metal trace 310 may electrically couple IPD 112 to resonator 106, as illustrated in Fig. 3. In an embodiment, one or more metal traces 310 may be fabricated by standard package fabrication techniques, such as electroplating, sputtering, electroless plating, printing, dispensing, and stencil printing. In an embodiment, no wire bonds are provided to AWR device 104.

[0040] Although packaged systems 100, 200 and 300 have been described with respect to utilizing an active die 110 and an IPD 112, it is to be appreciated that embodiments of the present disclosure may be practiced by coupling different components to an AWR device disposed in a cavity of a package substrate. For example, embodiments of the present disclosure need not include an active die. In embodiments, a recessed AWR device may couple only passive components together such as IPDs or discrete capacitors or discrete inductors, which may be coupled together to form a filter such as a hybrid filter. It is to be appreciated that although an AWR device is described above as being placed in a cavity, any other die type can be placed in a package cavity.

[0041] Fig. 4 is a schematic illustration of an RF front end system or module 400. RF module 400 includes passive devices 410 and active devices 420. Passive devices 410 may include an acoustic wave resonator 430 and an inductor 440 coupled together in parallel. The active devices 420 may include transistors 450, amplifiers 460 and switches 480. In an embodiment, passive devices 410 may be coupled together to form a hybrid filter or bank of hybrid filters. In an embodiment, the hybrid filter is a hybrid filter such as described below in association with Fig. 5. In an embodiment, the passive devices 410 and active devices 420 are integrated together in a single packaged system, such as one of the packaged systems 100-300 described above. [0042] Embodiments of the present disclosure relate to hybrid filters and more particularly to filters having acoustic wave resonators (AWRs), lumped component resonators, and transformers and packages therefor. Embodiments of the present disclosure relate to a radio frequency (RF) hybrid filter having a plurality of acoustic wave resonators (AWR) and a transformer based resonator. The basic principle of the embodiments of the present disclosure consist of utilizing at least one RF transformer as the core of an LC resonator and one or more acoustic wave resonators to improve the out of band rejection of the resulting hybrid filter. The use of a transformer reduces the number of components in the filter. Additionally, the broadband nature of a transformer results in low parasitics and therefore enables filters operating at high frequencies. The filter can be further implemented by using an equivalent circuit of a transformer, such as a T-network or a Pi-network. In an embodiment, the hybrid circuit includes multiple parallel acoustic wave resonators to enhance the signal rejection in the guard band and at the band edge. The hybrid filter of the present disclosure may exhibit wide band width and sharp roll off. The hybrid filter of the present disclosure may be used in next generation mobile and wireless communication devices and infrastructures which require the handling of data at high rates, such as 5G networks. In embodiments, the filters of the present disclosure may exhibit excellent roll off and out of band rejection to enable multi -radio coexistence.

[0043] In embodiments of the present disclosure the hybrid filter is a hybrid LC/AWR

(lumped component/acoustic wave resonator) filter comprising RF passive elements, such as inductors, transformers and capacitors, and acoustic wave resonators fabricated using a piezoelectric material, such as a thin film bulk acoustic resonator (FBAR to TFBAR). In an embodiment, a first winding of a transformer may be coupled to a first port and to a first acoustic wave resonator and a second acoustic wave resonator may be coupled to a second winding of the transformer and to a second port. A first capacitor may be coupled in parallel with the first winding of the inductor and a second capacitor may be coupled in parallel with a second winding of the transformer. A lumped element resonator comprising an inductor coupled in parallel with a capacitor may be disposed between the coupling of the first acoustic wave resonator and the first winding of the transformer.

[0044] Fig. 5 is a schematic illustration of an RF hybrid circuit or filter 500 in accordance with an embodiment of the present disclosure. Hybrid filter 500 includes a first acoustic wave resonator (AWR) 510, a lumped component resonator 524, a transformer (XFMR) 512 and a second acoustic wave resonator (AWR) 514. In an embodiment, first AWR 510 has a first electrode coupled to a first port or an input port 502 and has a second electrode coupled to ground. In an embodiment, an inductor 520 has a first terminal coupled to the first electrode of AWR 510 and to the input port 502 and a second terminal coupled to a first node 530. A capacitor 522 is coupled in parallel with inductor 520. The capacitor 522 and the inductor 520 create a lump element resonator 524 which forms a transmission zero either below or above the pass band region. A first coil or winding 534 of transformer 512 has a first terminal coupled to node 530 and a second terminal couple to ground. A second coil or winding 536 of transformer 512 has a first terminal coupled to a node 540 and a second terminal coupled to ground as illustrated in Fig. 5. A capacitor 550 has a first electrode or plate coupled to node 530 and in an embodiment a second electrode or plate coupled to ground. In an embodiment the second electrode of capacitor 550 is directly connected to the second terminal of first winding 534 of transformer 512. A capacitor 560 has a first electrode or plate coupled to node 540 and in an embodiment has a second electrode or plate coupled to ground. In an embodiment, the second electrode of capacitor 560 is directly connected to the second terminal of the second winding 536 of transformer 512. Although each of the second terminals of capacitor 550 and capacitor 560 are illustrated as being coupled to ground, they may each be, in an embodiment, connected to a same or different DC voltage in order to provide tuning capabilities. The poles of the filter are defined by capacitors 550 and 560 and transformer 512. In an embodiment, filter 500 has two poles and therefore may be considered a second order filter. In another embodiment, filter 500 has more than two poles and may be considered a higher order filter. [0045] Second AWR 514 has a first electrode coupled to node 540 and a second electrode coupled to a second port or output port 504. In an embodiment, hybrid filter 500 of Fig. 5 includes two acoustic wave resonators, AWR 510 and AWR 514. The acoustic wave resonators act as a transmission zero around the edge of the passband and therefore enable filter 500 to achieve strong rejection in the adjacent guard band.

[0046] In an embodiment, filter 500 may include one or more matching inductors. In an embodiment, filter 500 includes an inductor 570 having a first terminal coupled to input port 502 and a second terminal coupled to ground. In an embodiment, filter 500 may include an inductor 580 disposed between second AWR 514 and node 540. In an embodiment, inductor 580 has a first terminal coupled to node 540 and a second terminal to the first electrode of AWR 514, as illustrated in Fig. 5. In an embodiment, inductor 570 and inductor 580 are matching inductors and act as transmission zero (responsible for signal attenuation) at low and high frequencies, respectively.

[0047] In an embodiment, filter 500 may include a capacitor 590 having a first electrode or plate coupled to node 530 and a second electrode or plate coupled to node 540, as illustrated in Fig. 5. Capacitor 590 may form another transmission zero with transformer 512.

[0048] In embodiments of the present disclosure, individual ones of the inductors 520,

570, and 580 may be implemented as a series combination of two or more smaller inductors to improve the frequency range of operation, the in-band and out of band performance at a cost of inductance density and/or quality factor. Similarly, individual ones of the capacitors 522, 550, 560 and 590 may be implemented as a parallel combination of two or more smaller capacitors.

In an embodiment, the inductors may have an inductance in the range of 0.1 to 15 nanoHenrys (nH). In an embodiment, the capacitors may have a capacitance in the range of 0.1 to 15 picoFarads (pF).

[0049] First winding 534 and second winding 536 of transformer 512 may be inductively coupled together. That is, first winding 534 and second winding 536 may be sufficiently close together to provide mutual inductive coupling. In an embodiment, first winding 534 and second winding 536 have a low inductive mutual coupling coefficient of between 0.01 to 0.5. In an embodiment, first winding 534 and second winding 536 are sufficiently sized to create an inductance ratio between 1 :2-2: 1. In an embodiment first winding 534 and second winding 536 have an inductance ratio of approximately 1: 1. First winding 534 may be considered the primary coil of transformer 512 and second winding 536 may be considered the secondary winding of transformer 512.

[0050] In an embodiment, hybrid filter 500 is an RF band pass filter. Filter 500 may reject signals at both low and high frequencies. The signal transmission between input port 502 and output port 504 is maximum in the desired passband region. In an embodiment, an RF analog input signal having a frequency between 800 MHz to 8 GHz is applied to input port 502. In an embodiment, an analog signal between 3.3 to 4.2 GHz is provided to input port 502. In yet another embodiment, an input signal between 4.4 to 4.9 GHz is provided to input port 502. The input signal passes through filter 500 and a filtered analog output signal is provided on output port 504. In an embodiment, transformer 512 may be replaced with a transformer equivalent circuit such as a T-network of inductors or a Pi-network of inductors.

[0051] Fig. 6A and Fig. 6B illustrate various capacitors which may be integrated or embedded into a package substrate, into an active die, or into an AWR die, in accordance with embodiments of the present disclosure. In embodiments, capacitors are thin film resonators consisting of metal electrodes and a dielectric material between the electrodes with a defined dielectric loss tangent. The quality of the capacitors increases with decreasing loss tangent. The capacitor dielectric material may have a high dielectric constant to reduce the footprint of the capacitor. In an exemplary embodiment, Fig. 6A is a cross sectional illustration of a multilayer package substrate 600, such as a multilayer organic package substrate or a low temperature co- fired substrate. Substrate 600 includes a first side 602 and a second side 604 opposite the first side 602. A plurality of contact pads 606 may be disposed on first side 602 and a plurality of contact pads 608 may be disposed on second side 604. Multilayer substrate 600 includes a plurality of metal layers 610, such as copper layers. Each of the metal layers 610 includes a plurality of metal traces or conductors 612. A plurality of dielectric layers 620, such as silicon dioxide or silicon oxide layers, are disposed between metal layers 610 to electrically isolate the metal layers 610 from one another. Dielectric layers 620 may also be disposed between traces 612 of metal layers 610. A plurality of conductive vias 622, such as copper vias, may be disposed in dielectric layers 620 to enable electrical connections between adjacent metal layers 610.

[0052] In an embodiment, package substrate 600 may include a parallel plate capacitor

630 which includes a first electrode or plate 632 formed in one metal layer 610 and a second electrode or plate 634 formed in a second vertically adjacent metal layer 610. In an embodiment, a portion of the dielectric layers 620 between first electrode or plate 632 and second electrode or plate 634 forms the capacitor dielectric layer of capacitor 630.

[0053] In an embodiment, package substrate 600 may include one or more parallel plate capacitors 640 which includes a first electrode or plate 642 formed in one metal layer 610 and a second electrode or plate 644 disposed in a second vertically adjacent metal layer 610. Capacitor 640 may include a capacitor dielectric 646 formed of a dielectric material which is different than the dielectric material 620 used to isolate the metal layers 610 of package substrate 600. In an embodiment, dielectric 646 is a high dielectric constant material, such as a metal oxide dielectric material, e.g., aluminum oxide, zirconium oxide, hafnium oxide, barium strontium titanate (BST) or lead zirconium titanate (PZT). In an embodiment, dielectric 646 is a low loss tangent dielectric material. In this way, a high performance capacitor may be fabricated.

[0054] In an embodiment, package substrate 600 may include one or more parallel plate capacitors 650. Capacitor 650 includes a first electrode or plate 652, a second electrode or plate 654 and an intervening capacitor dielectric 656 disposed there between. In an embodiment, capacitor 650 is disposed in a single metal layer 610 of substrate 600 as illustrated in Fig. 6A. In an embodiment, capacitor dielectric 656 may be formed from a dielectric material having a high dielectric constant, such as a high k dielectric and which is different than the dielectric material 620 used to form package substrate 600. In an embodiment, dielectric 656 is a high dielectric constant material, such as a metal oxide dielectric material, e.g., aluminum oxide, zirconium oxide, hafnium oxide, BST or PZT. In an embodiment, dielectric 656 is a low loss tangent dielectric material. In this way, a high performance capacitor may be fabricated.

[0055] In an embodiment, package substrate 600 may include one or more capacitors 660 as illustrated in Fig. 6A. Capacitor 660 includes a top electrode 662 and a bottom electrode 664. Top electrode 662 includes a via portion 666. Via portion 666 is separated from bottom electrode 664 by a capacitor dielectric 668. Capacitor dielectric 668 may be deposited in a via opening prior to filling the via with a conductive material, such as copper. In an embodiment, capacitor dielectric 668 is a high k dielectric layer, such as a metal oxide, such as hafnium oxide or aluminum oxide. In an embodiment, capacitor dielectric 668 is a low loss dielectric material. In an embodiment, capacitor dielectric 668 is a different dielectric material than dielectric material 620. In an embodiment, capacitor dielectric 668 is a high dielectric constant material, such as a metal oxide dielectric material, e.g., aluminum oxide, zirconium oxide, hafnium oxide, BST or PZT. In an embodiment, capacitor dielectric 668 is a low loss tangent dielectric material. In this way, a high performance capacitor may be fabricated.

[0056] Fig. 6B illustrates a plan view of a capacitor 670 which may be embedded in package substrate 600 in accordance with embodiments of the present disclosure. Capacitor 670 includes a first electrode 672 and a second electrode 674. First electrode 672 includes a plurality of fingers 675 extending from a back bone 676 which are interleaved or interdigitated with a plurality of fingers 677 extending from a back bone 678 of second electrode 674 as illustrated in Fig. 6B. In an embodiment, first electrode 672 and second electrode 674 are disposed in a same metal layer 610 or plane of package substrate 600. Dielectric layer 620 disposed between the back bone and fingers of the electrodes may act as a capacitor dielectric. In an embodiment, dielectric material 620 disposed between the electrodes may be replaced with a different dielectric material, such as a high k dielectric material and/or a low loss tangent dielectric material, if desired. [0057] Figs. 7A-7F illustrate various inductors which may be embedded into a package substrate, an active die, or an AWR device or die, in accordance with embodiments of the present disclosure. In an exemplary embodiment, Fig. 7A is a cross-sectional illustration of package substrate 600 which in an embodiment may include one or more inductors formed from one or more metal layers 610 of package substrate 600. In an embodiment, package substrate 600 may include one or more inductors 710. In an embodiment, inductor 710 has a loop disposed in a single metal layer 610 of package substrate 600. Inductor 710 may have a partial or fractional loop, as illustrated in Fig. 7B, a full loop, as illustrated in Fig. 7C, or multiple loops, such as two or more loops as illustrated in Fig. 7D.

[0058] In an embodiment, package substrate 600 may include one or more inductors 720.

Inductor 720 may include one or more loops including a first metal portion 722 disposed in a first metal layer 610 of package substrate 600 and a second metal portion 724 disposed in a second metal layer 610 vertically adjacent to the first metal layer 610. The first metal portion 722 is electrically coupled to the second metal portion 724 by a plurality of metal vias 726, as illustrated in Fig. 7A. In this way, an inductor 720 may have a loop with a metal thickness greater than the metal thickness of a single metal layer 610 of package substrate 600 and thereby yield a high Q inductor. By increasing the thickness of the conductors of inductor 720, an inductor having a Q factor of 100 or better at the frequency of operation may be achieved.

[0059] Fig. 7E is a plan view of inductor 720 showing a top portion 722 of a loop and the underlying vias 726 electrically connected thereto. Dielectric material 620 may be disposed between conductive vias 726 and between the first metal portion 722 and a second metal portion 724. If desired, inductor 720 may include a third metal portion disposed in a third metal layer 610 and be electrically connected to second metal portion 724 by a second plurality of conductive vias. In an embodiment of the present disclosure, the plurality of conductive vias 726 and 622 may be formed by laser drilling a plurality of via openings in the dielectric layer 610 and then filling the vias with a conductive material, such as copper, when forming the metal layer 610 above. Laser drilling provides a cost effective method of creating vias 726 and 622. [0060] In an embodiment, package substrate 600 may include one or more inductors 730 as illustrated in Fig. 7A. Inductor 730 includes a first metal portion 732 disposed in a first metal layer 610 and a second metal portion 734 disposed in a second metal layer 610 vertically adjacent to the first metal layer 610. A slot via or trench via 736 may be used to connect first metal portion 732 with second metal portion 734. Trench via 734 may have a length

substantially equal to, or at least 90% of, the length of the loop or loops included in metal portions 732 and 734, as illustrated in Fig. 7F. In an embodiment, trench via 736 has a width which is less than the width of metal portions 732 and 734. Trench vias 736 may be formed by lithographically patterning a trench opening in dielectric layer 620 by, for example,

lithographically patterning a photoresist mask and then etching a trench opening in alignment with the photoresist mask. Alternatively, dielectric layer 620 may be a photo definable dielectric and may be directly photo defined to form a trench opening therein. The trench opening may be subsequently filled when forming metal layer 610 which includes metal portion 732. Inductor 730 may be able to exhibit a higher Q factor than inductor 722 because inductor 730 has a trench via which substantially or completely connects the metal portion 732 with the metal portion 734 while inductor 720 is coupled by vias and has dielectric 620 between metal portions 722 and 724, as illustrated in Fig. 7E.

[0061] It is to be appreciated that inductors such as inductors 710, 720 and 730 may be stand-alone inductors or may be combined with other inductors to fabricate windings of a transformer or a transformer-equivalent circuit.

[0062] Fig. 8 is a schematic block diagram illustrating a computer system that utilizes a packaged system as described herein, in accordance with an embodiment of the present disclosure. Fig. 8 illustrates an example of a computing device 800. Computing device 800 houses motherboard 802. Motherboard 802 may include a number of components, including but not limited to processor 804, device package 810, and at least one communication chip 806. Processor 804 is physically and electrically coupled to motherboard 802. For some

embodiments, at least one communication chip 806 is also physically and electrically coupled to motherboard 802. For other embodiments, at least one communication chip 806 is part of processor 804.

[0063] Depending on its applications, computing device 800 may include other components that may or may not be physically and electrically coupled to motherboard 802. These other components include, but are not limited to, volatile memory (e.g., DRAM), non volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).

[0064] At least one communication chip 806 enables wireless communications for the transfer of data to and from computing device 800. The term“wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. At least one communication chip 806 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. Computing device 800 may include a plurality of communication chips 806. For instance, a first communication chip 806 may be dedicated to shorter range wireless

communications such as Wi-Fi and Bluetooth and a second communication chip 806 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others. [0065] Processor 804 of computing device 800 includes an integrated circuit die packaged within processor 804. Device package 810 may be, but is not limited to, a packaging substrate and/or a printed circuit board. Note that device package 810 may be a single component, a subset of components, and/or an entire system.

[0066] For some embodiments, the integrated circuit die may be packaged with one or more devices on device package 810 that include a thermally stable RFIC and antenna for use with wireless communications. The term“processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

[0067] At least one communication chip 806 also includes an integrated circuit die packaged within the communication chip 806. For some embodiments, the integrated circuit die of the communication chip may be packaged with one or more devices on the device package 810, as described herein.

[0068] Although specific embodiments have been described above, these embodiments are not intended to limit the scope of the present disclosure, even where only a single embodiment is described with respect to a particular feature. Examples of features provided in the disclosure are intended to be illustrative rather than restrictive unless stated otherwise. The above description is intended to cover such alternatives, modifications, and equivalents as would be apparent to a person skilled in the art having the benefit of the present disclosure.

[0069] The scope of the present disclosure includes any feature or combination of features disclosed herein (either explicitly or implicitly), or any generalization thereof, whether or not it mitigates any or all of the problems addressed herein. Accordingly, new claims may be formulated during prosecution of the present application (or an application claiming priority thereto) to any such combination of features. In particular, with reference to the appended claims, features from dependent claims may be combined with those of the independent claims and features from respective independent claims may be combined in any appropriate manner and not merely in the specific combinations enumerated in the appended claims. [0070] The following examples pertain to further embodiments. The various features of the different embodiments may be variously combined with some features included and others excluded to suit a variety of different applications.

[0071] Example embodiment 1 : A packaged system includes a package substrate having a die side and a land side opposite the die side. An active die physically and electrically coupled to the die side of the package substrate. An acoustic wave resonator (AWR) device is in a cavity on the die side of the package substrate, the AWR device including an acoustic wave resonator (AWR) die wherein the AWR die includes a resonator wherein the AWR device is directly electrically coupled to the active die.

[0072] Example embodiment 2: The packaged system of example embodiment 1 further comprising an integrated passive device (IPD) physically and electrically coupled to the die side of the package substrate.

[0073] Example embodiment 3: The packaged system of example embodiment 1 or 2 wherein the AWR device further comprises a cap disposed over the resonator and coupled to the AWR die.

[0074] Example embodiment 4: The packaged system of example embodiment 3 wherein the AWR device further comprises a seal frame, the seal frame surrounding the resonator, the seal frame attaching the cap to the AWR die and creating a hermetically sealed cavity around the resonator.

[0075] Example embodiment 5: The packaged system of example embodiment 4 wherein the seal frame comprises a metal, the metal selected from the group consisting of gold, copper, tin and indium.

[0076] Example embodiment 6: The packaged system of example embodiment 4 wherein the seal frame comprises an insulator, the insulator selected from the group consisting of a glass frit, a polymer, a liquid crystal polymer, and an inorganic dielectric. [0077] Example embodiment 7: The packaged system of example embodiment 1, 2, 3, 4,

5 or 6 wherein the package substrate is a multilayer package substrate including one or more capacitors embedded therein.

[0078] Example embodiment 8: The packaged system of example embodiment 1, 2, 3, 4,

5, 6 or 7 wherein the package substrate is a multilayer package substrate including one or more inductors embedded therein.

[0079] Example embodiment 9: The packaged system of example embodiment 1, 2, 3, 4,

5, 6, 7 or 8 wherein the package substrate is a multilayered package substrate including a transformer embedded therein.

[0080] Example embodiment 10: The packaged system of example embodiment 1, 2, 3,

4, 5, 6, 7, 8 or 9 wherein the active die is coupled to the AWR device by a flip chip connection.

[0081] Example embodiment 11 : The packaged system of example embodiment 2 wherein the IPD is on the die side of the package substrate and is electrically coupled to the AWR device by a flip chip connection.

[0082] Example embodiment 12: The packaged system of example embodiment 1 wherein the active die is coupled to the AWR device by a wire bond.

[0083] Example embodiment 13: The packaged system of example embodiment 2 wherein the IPD is on the die side of the package substrate and is electrically coupled to the AWR device by a wire bond.

[0084] Example embodiment 14: The packaged system of example embodiment 2 wherein the IPD is on the die side of the package substrate and is electrically coupled to the AWR device by a bridging trace.

[0085] Example embodiment 15: The packaged system of example embodiment 1, 2, 3,

4, 5, 6, 7, 8, 9, 10, 11, 12, 13 or 14 further comprising a dielectric disposed between the AWR device and the package substrate.

[0086] Example embodiment 16: The packaged system of example embodiment 15 wherein the dielectric is a nonconductive epoxy based organic dielectric. [0087] Example embodiment 17: The packaged system of example embodiment 2 wherein the active die is electrically coupled to the IPD by an electrical connection disposed in the AWR device without routing through the package substrate.

[0088] Example embodiment 18: A packaged system includes a package substrate having a die side and a landside opposite the die side, the package substrate including one or more passive devices embedded therein. An active die is physically and electrically coupled to the die side of the package substrate, the active die including an active circuit, the active circuit selected from the group consisting of a switch, an amplifier, and a matching network. An integrated passive device (IPD) is physically and electrically coupled to the die side of the package substrate, the IPD including a plurality of high Q factor passive devices. An acoustic wave resonator (AWR) device is in a cavity on a die side of the package substrate, the AWR device including an acoustic wave resonator (AWR) die, the acoustic wave resonator (AWR) die including a resonator, wherein the AWR device is electrically coupled to the IPD and the active die.

[0089] Example embodiment 19: The packaged system of example embodiment 18 further comprising a plurality of bond pads on the land side of the package substrate.

[0090] Example embodiment 20: The packaged system of example embodiment 19 further comprising a plurality of solder balls on the plurality of bond pads on the land side of the package substrate.

[0091] Example embodiment 21: The packaged system of example embodiment 18, 19 or 20 further comprising a hybrid circuit formed from the one or more passive devices disposed in the package substrate, and the of high Q factor passive devices of the IPD.

[0092] Example embodiment 22: A packaged system includes a package substrate having a die side and a landside opposite the die side. An active die is physically and electrically coupled to the die side of the package substrate, the active die including an active circuit, the active circuit selected from the group consisting of a switch, an amplifier, and a matching network. An integrated passive device (IPD) is physically and electrically coupled to the die side of the package substrate, the IPD including a plurality of high Q factor passive devices. An acoustic wave resonator (AWR) device is in a cavity on a die side of the package substrate, the AWR device including an acoustic wave resonator (AWR) die, the acoustic wave resonator (AWR) die including a resonator, wherein the AWR device is electrically coupled to the IPD and the active die, wherein the active die is electrically coupled to the IPD by an electrical connection disposed in the AWR device without routing through the package substrate.

[0093] Example embodiment 23: The packaged system of example embodiment 22 wherein the AWR device further comprises a cap disposed over the resonator and coupled to the AWR die.

[0094] Example embodiment 24: The packaged system of example embodiment 23 wherein the AWR device further comprises a seal frame, the seal frame surrounding the resonator, the seal frame attaching the cap to the AWR die and creating a hermetically sealed cavity around the resonator.

[0095] Example embodiment 25: The packaged system of example embodiment 24 wherein the seal frame comprises one of a metal or an insulator, wherein the metal is selected from the group consisting of gold, copper, tin and indium, and wherein insulator is selected from the group consisting of a glass frit, a polymer, a liquid crystal polymer, and an inorganic dielectric.

Claims

CLAIMS What is claimed is:

1. A packaged system comprising:

a package substrate having a die side and a land side opposite the die side;

an active die physically and electrically coupled to the die side of the package substrate; an acoustic wave resonator (AWR) device in a cavity on the die side of the package substrate, the AWR device including an acoustic wave resonator (AWR) die wherein the AWR die includes a resonator wherein the AWR device is directly electrically coupled to the active die.

2. The packaged system of claim 1 further comprising an integrated passive device (IPD) physically and electrically coupled to the die side of the package substrate.

3. The packaged system of claim 1 wherein the AWR device further comprises a cap disposed over the resonator and coupled to the AWR die.

4. The packaged system of claim 3 wherein the AWR device further comprises a seal frame, the seal frame surrounding the resonator, the seal frame attaching the cap to the AWR die and creating a hermetically sealed cavity around the resonator.

5. The packaged system of claim 4 wherein the seal frame comprises a metal, the metal selected from the group consisting of gold, copper, tin and indium.

6. The packaged system of claim 4 wherein the seal frame comprises an insulator, the insulator selected from the group consisting of a glass frit, a polymer, a liquid crystal polymer, and an inorganic dielectric.

7. The packaged system of claim 1 wherein the package substrate is a multilayer package substrate including one or more capacitors embedded therein.

8. The packaged system of claim 1 wherein the package substrate is a multilayer package substrate including one or more inductors embedded therein.

9. The packaged system of claim 1 wherein the package substrate is a multilayered package substrate including a transformer embedded therein.

10. The packaged system of claim 1 wherein the active die is coupled to the AWR device by a flip chip connection.

11. The packaged system of claim 2 wherein the IPD is on the die side of the package substrate and is electrically coupled to the AWR device by a flip chip connection.

12. The packaged system of claim 1 wherein the active die is coupled to the AWR device by a wire bond.

13. The packaged system of claim 2 wherein the IPD is on the die side of the package substrate and is electrically coupled to the AWR device by a wire bond.

14. The packaged system of claim 2 wherein the IPD is on the die side of the package substrate and is electrically coupled to the AWR device by a bridging trace.

15. The packaged system of claim 1 further comprising a dielectric disposed between the

AWR device and the package substrate.

16. The packaged system of claim 15 wherein the dielectric is a nonconductive epoxy based organic dielectric.

17. The packaged system of claim 2 wherein the active die is electrically coupled to the IPD by an electrical connection disposed in the AWR device without routing through the package substrate.

18. A packaged system comprising:

a package substrate having a die side and a landside opposite the die side, the package substrate including one or more passive devices embedded therein;

an active die physically and electrically coupled to the die side of the package substrate, the active die including an active circuit, the active circuit selected from the group consisting of a switch, an amplifier, and a matching network;

an integrated passive device (IPD) physically and electrically coupled to the die side of the package substrate, the IPD including a plurality of high Q factor passive devices;

an acoustic wave resonator (AWR) device in a cavity on a die side of the package substrate, the AWR device including an acoustic wave resonator (AWR) die, the acoustic wave resonator (AWR) die including a resonator, wherein the AWR device is electrically coupled to the IPD and the active die.

19. The packaged system of claim 18 further comprising a plurality of bond pads on the land side of the package substrate.

20. The packaged system of claim 19 further comprising a plurality of solder balls on the plurality of bond pads on the land side of the package substrate.

21. The packaged system of claim 18 further comprising a hybrid circuit formed from the one or more passive devices disposed in the package substrate, and the of high Q factor passive devices of the IPD.

22. A packaged system comprising:

a package substrate having a die side and a landside opposite the die side;

an acoustic wave resonator (AWR) device in a cavity on a die side of the package substrate, the AWR device including an acoustic wave resonator (AWR) die, the acoustic wave resonator (AWR) die including a resonator, wherein the AWR device is electrically coupled to the IPD and the active die, wherein the active die is electrically coupled to the IPD by an electrical connection disposed in the AWR device without routing through the package substrate.

23. The packaged system of claim 22 wherein the AWR device further comprises a cap disposed over the resonator and coupled to the AWR die.

24. The packaged system of claim 23 wherein the AWR device further comprises a seal frame, the seal frame surrounding the resonator, the seal frame attaching the cap to the AWR die and creating a hermetically sealed cavity around the resonator.

25. The packaged system of claim 24 wherein the seal frame comprises one of a metal or an insulator, wherein the metal is selected from the group consisting of gold, copper, tin and indium, and wherein insulator is selected from the group consisting of a glass frit, a polymer, a liquid crystal polymer, and an inorganic dielectric.