JP2005026659A - フラッシュ素子のビットライン形成方法 - Google Patents
フラッシュ素子のビットライン形成方法 Download PDFInfo
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- JP2005026659A JP2005026659A JP2003416902A JP2003416902A JP2005026659A JP 2005026659 A JP2005026659 A JP 2005026659A JP 2003416902 A JP2003416902 A JP 2003416902A JP 2003416902 A JP2003416902 A JP 2003416902A JP 2005026659 A JP2005026659 A JP 2005026659A
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- 238000000034 method Methods 0.000 title claims abstract description 53
- 229910052751 metal Inorganic materials 0.000 claims abstract description 66
- 239000002184 metal Substances 0.000 claims abstract description 66
- 239000011229 interlayer Substances 0.000 claims abstract description 46
- 230000008569 process Effects 0.000 claims abstract description 39
- 238000005530 etching Methods 0.000 claims abstract description 38
- 230000004888 barrier function Effects 0.000 claims abstract description 19
- 238000004140 cleaning Methods 0.000 claims abstract description 17
- 239000004065 semiconductor Substances 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 5
- 238000000059 patterning Methods 0.000 claims abstract description 5
- 238000004544 sputter deposition Methods 0.000 claims description 6
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 6
- 229910052721 tungsten Inorganic materials 0.000 claims description 6
- 239000010937 tungsten Substances 0.000 claims description 6
- 238000005108 dry cleaning Methods 0.000 claims description 5
- 239000007769 metal material Substances 0.000 claims description 3
- 239000010410 layer Substances 0.000 abstract description 16
- 230000009467 reduction Effects 0.000 abstract description 3
- 239000010408 film Substances 0.000 description 127
- 239000000463 material Substances 0.000 description 8
- 150000004767 nitrides Chemical class 0.000 description 6
- 230000008878 coupling Effects 0.000 description 4
- 238000010168 coupling process Methods 0.000 description 4
- 238000005859 coupling reaction Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000007517 polishing process Methods 0.000 description 4
- 239000005368 silicate glass Substances 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 3
- 230000007423 decrease Effects 0.000 description 3
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- 230000002265 prevention Effects 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- GDFCWFBWQUEQIJ-UHFFFAOYSA-N [B].[P] Chemical compound [B].[P] GDFCWFBWQUEQIJ-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 150000004760 silicates Chemical class 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
【解決手段】 ビットラインコンタクトプラグが設けられた半導体基板上にバリア膜、層間絶縁膜及び金属ハードマスク膜を順次形成する段階と、前記金属ハードマスク膜をパターニングし、前記ビットラインコンタクトプラグと対応するビットライン領域を開放する金属ハードマスク膜パターンを形成する段階と、前記金属ハードマスク膜パターンをエッチングマスクとするエッチング工程によって層間絶縁膜及びバリア膜をエッチングしてビットライン用トレンチを形成する段階と、前記ビットライン用トレンチが埋め込まれるようにビットライン用金属膜を形成する段階と、平坦化工程を行い、前記層間絶縁膜上の前記ビットライン用金属膜及び前記金属ハードマスク膜パターンを除去する段階とを含む。【選択図】 図5
Description
C01、C11、C12 …インターキャパシタンス
W/L、DSL、SSL …ワードライン
M2 …金属配線
10 …基板
12 …ビットラインコンタクトプラグ
14 …バリア膜
16 …層間絶縁膜
18 …感光膜パターン
20 …ビットライン用トレンチ
30 …ビットライン
110 …半導体基板
112 …ビットライン用コンタクトプラグ
114 …第1層間絶縁膜
116 …バリア膜
118 …第2層間絶縁膜
120 …金属ハードマスク膜
122 …感光膜パターン
124 …ビットライン用トレンチ
130 …ビットライン
Claims (5)
- ビットライン用コンタクトプラグが設けられた半導体基板上にバリア膜、層間絶縁膜及び金属ハードマスク膜を順次形成する段階と、
前記金属ハードマスク膜をパターニングして、前記ビットライン用コンタクトプラグと対応するビットライン領域を開放する金属ハードマスク膜パターンを形成する段階と、
前記金属ハードマスク膜パターンをエッチングマスクとするエッチング工程によって層間絶縁膜及びバリア膜をエッチングしてビットライン用トレンチを形成する段階と、
前記ビットライン用トレンチが埋め込まれるようにビットライン用金属膜を形成する段階と、
平坦化工程を行い、前記層間絶縁膜上の前記ビットライン用金属膜及び前記金属ハードマスク膜パターンを除去する段階とを含むフラッシュ素子のビットライン形成方法。 - 前記ビットライン用トレンチを形成する段階の後、前記ビットライン用金属膜を形成する段階の前に、
プラズマを用いたドライ洗浄工程又は高周波スパッタリングによる洗浄工程を行い、前記ビットライン用トレンチの内部を洗浄する段階をさらに含む請求項1記載のフラッシュ素子のビットライン形成方法。 - 前記ドライ洗浄工程はCF4とO2との混合ガス及びNF3ガスを用いて行い、前記高周波スパッタリングによる洗浄工程はArガスを用いて行う請求項2記載のフラッシュ素子のビットライン形成方法。
- 前記金属ハードマスク膜と前記ビットライン用金属膜は同一の金属物質を用いて形成する請求項1記載のフラッシュ素子のビットライン形成方法。
- 前記金属ハードマスク膜はタングステンを用いて形成するが、後続の前記層間絶縁膜のエッチング時にエッチングバリアとして耐えられるように500〜1000Åの厚さに形成する請求項1記載のフラッシュ素子のビットライン形成方法。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020030043798A KR100568425B1 (ko) | 2003-06-30 | 2003-06-30 | 플래시 소자의 비트라인 형성 방법 |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2005026659A true JP2005026659A (ja) | 2005-01-27 |
Family
ID=33536409
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2003416902A Pending JP2005026659A (ja) | 2003-06-30 | 2003-12-15 | フラッシュ素子のビットライン形成方法 |
Country Status (5)
Country | Link |
---|---|
US (1) | US6964921B2 (ja) |
JP (1) | JP2005026659A (ja) |
KR (1) | KR100568425B1 (ja) |
DE (1) | DE10358767A1 (ja) |
TW (1) | TWI243445B (ja) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006245538A (ja) * | 2005-02-28 | 2006-09-14 | Hynix Semiconductor Inc | フラッシュメモリ素子の製造方法 |
JP2008205470A (ja) * | 2007-02-16 | 2008-09-04 | Samsung Electronics Co Ltd | 半導体素子の微細金属配線パターンの形成方法 |
KR100859006B1 (ko) * | 2007-08-22 | 2008-09-18 | 삼성전기주식회사 | 인쇄회로기판 제조방법 |
WO2008126776A1 (en) * | 2007-04-10 | 2008-10-23 | Tokyo Electron Limited | Fabrication method of a semiconductor device and a semiconductor device |
US9099285B2 (en) | 2012-10-29 | 2015-08-04 | Tokyo Electron Limited | Plasma processing method and plasma processing apparatus |
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US6706402B2 (en) | 2001-07-25 | 2004-03-16 | Nantero, Inc. | Nanotube films and articles |
US6919592B2 (en) * | 2001-07-25 | 2005-07-19 | Nantero, Inc. | Electromechanical memory array using nanotube ribbons and method for making same |
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- 2003-12-12 US US10/734,389 patent/US6964921B2/en not_active Expired - Fee Related
- 2003-12-12 DE DE10358767A patent/DE10358767A1/de not_active Ceased
- 2003-12-15 JP JP2003416902A patent/JP2005026659A/ja active Pending
- 2003-12-22 TW TW092136410A patent/TWI243445B/zh not_active IP Right Cessation
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JPH10200075A (ja) * | 1996-11-14 | 1998-07-31 | Hitachi Ltd | 半導体集積回路装置およびその製造方法 |
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JP2001284329A (ja) * | 2000-03-31 | 2001-10-12 | Toshiba Corp | 半導体装置の製造方法及び半導体装置 |
JP2002076300A (ja) * | 2000-08-24 | 2002-03-15 | Matsushita Electric Ind Co Ltd | 半導体装置およびその製造方法 |
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JP2006245538A (ja) * | 2005-02-28 | 2006-09-14 | Hynix Semiconductor Inc | フラッシュメモリ素子の製造方法 |
JP2008205470A (ja) * | 2007-02-16 | 2008-09-04 | Samsung Electronics Co Ltd | 半導体素子の微細金属配線パターンの形成方法 |
WO2008126776A1 (en) * | 2007-04-10 | 2008-10-23 | Tokyo Electron Limited | Fabrication method of a semiconductor device and a semiconductor device |
JP2008262996A (ja) * | 2007-04-10 | 2008-10-30 | Tokyo Electron Ltd | 半導体装置の製造方法及び半導体装置 |
US8124523B2 (en) | 2007-04-10 | 2012-02-28 | Tokyo Electron Limited | Fabrication method of a semiconductor device and a semiconductor device |
KR100859006B1 (ko) * | 2007-08-22 | 2008-09-18 | 삼성전기주식회사 | 인쇄회로기판 제조방법 |
US9099285B2 (en) | 2012-10-29 | 2015-08-04 | Tokyo Electron Limited | Plasma processing method and plasma processing apparatus |
Also Published As
Publication number | Publication date |
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TWI243445B (en) | 2005-11-11 |
KR100568425B1 (ko) | 2006-04-05 |
DE10358767A1 (de) | 2005-01-20 |
KR20050002420A (ko) | 2005-01-07 |
US6964921B2 (en) | 2005-11-15 |
US20040266106A1 (en) | 2004-12-30 |
TW200503155A (en) | 2005-01-16 |
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