JP2004119684A - 半導体装置 - Google Patents

半導体装置 Download PDF

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JP2004119684A
JP2004119684A JP2002280953A JP2002280953A JP2004119684A JP 2004119684 A JP2004119684 A JP 2004119684A JP 2002280953 A JP2002280953 A JP 2002280953A JP 2002280953 A JP2002280953 A JP 2002280953A JP 2004119684 A JP2004119684 A JP 2004119684A
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Prior art keywords
semiconductor element
pads
main surface
wiring
pad
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JP4031333B2 (ja
JP2004119684A5 (ja
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Kazushi Hatauchi
畑内　和士
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Renesas Technology Corp
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Renesas Technology Corp
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Priority to JP2002280953A priority Critical patent/JP4031333B2/ja
Priority to US10/376,269 priority patent/US6858920B2/en
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Publication of JP2004119684A5 publication Critical patent/JP2004119684A5/ja
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Abstract

【課題】半導体素子主面の対向する二辺に沿ってパッドを配列した半導体素子をＱＦＰ（Ｑｕａｄ　Ｆｌａｔ　Ｐａｃｋａｇｅ）にアセンブリした半導体装置を得る。
【解決手段】半導体装置１は、主面の対向する二辺に沿ってパッド４ａを配列した第一の半導体素子２ａと、第一の配線であるアルミ配線８で主面上に配列したパッド４ｂ、４ｃを電気的に接続した第二の半導体素子２ｂと、基板であるダイパッド３と、電極であるインナーリード５と、パッド４ａおよびパッド４ｃとインナーリード５とを接続する第二の配線６ａ、６ｃと、パッド４ａとパッド４ｂを接続する第三の配線６ｂを備える。第一の半導体素子２ａのパッド４ａと、第一の半導体素子２ａのパッド４ａが配列していない辺に隣接するダイパッド３の辺に沿って配列したインナーリード５との電気的接続は、第二の半導体素子２ｂに形成したアルミ配線８を経由する。
【選択図】　　　　　図１

Description

【０００１】
【発明の属する技術分野】
この発明は、対向する主面二辺に沿って配列したパッドを持つ半導体素子を、半導体素子を載置する基板主面の全ての外周辺に沿って配列した電極を持つパッケージに容易にアセンブリすることができる半導体装置に関するものである。
【０００２】
【従来の技術】
従来の積み重ねＭＣＭ構造の半導体装置においては、上側の半導体素子にダミー配線を形成し、このダミー配線を介して、下側の半導体素子の電気信号を、外部接続端子であるリードへ接続する構造にしている。これにより、下側の半導体素子の電気信号の引き回しを、上側の半導体素子で行うことができる（例えば、特許文献１参照）。
【０００３】
【特許文献１】
特開平１１−２２００９１号公報（第１−４頁、第１−６図）
【０００４】
【発明が解決しようとする課題】
近年パッド配置の最適化による半導体素子の面積縮小や、ウエハテストにおける半導体素子の多数個同測を目的としてパッドを対向する主面二辺に配列した半導体素子が製造されるようになっている。当初から主面二辺にパッドを持つように設計された半導体素子以外に、当初は主面四辺に沿ってパッドを配列するように設計および製造されＱＦＰにアセンブリされた半導体素子の中にも、半導体素子の面積縮小やウエハテストにおける多数個同測実現を目的として対向する主面２辺に沿ってパッドを配列するように設計変更されるものが現れてきた。このような半導体素子は既にＱＦＰとして出荷され回路基板に使用されているため、半導体素子のパッド配列が変わっても従来製品との互換性を維持するためにＱＦＰにアセンブリする必要がある。
【０００５】
しかし、従来の半導体装置は、下側半導体素子の電気信号の引き回しを上側の半導体素子で行うことによりアセンブリのための高価な多層基板を不要にできるが、この技術からは近年要求が高まっている対向する二辺にパッドを持つ半導体素子をＱＦＰ等の外周四辺に電極を持つパッケージに容易にアセンブリするための最適なパッドレイアウトや配線方法等を知ることはできない。
【０００６】
この発明は上記のような課題を解決するためになされたもので、対向する主面二辺に沿って配列したパッドを持つ半導体素子を、半導体素子を載置する基板主面の全ての外周辺に沿って配列した電極を持つＱＦＰ等のパッケージにアセンブリした半導体装置を得ることを目的とする。
【０００７】
【課題を解決するための手段】
第一の発明に係る半導体装置は、主面の対向する二辺に沿って配列したパッドを備える第一の半導体素子と、複数のパッドと前記複数のパッド相互を電気的に接続する第一の配線を主面に備えた第二の半導体素子と、前記第一の半導体素子および前記第二の半導体素子を載置する基板と、前記第一の半導体素子主面の前記パッドおよび前記第二の半導体素子主面の前記パッドと前記基板主面の全ての外周辺に沿って配列した電極とを電気的に接続する第二の配線と、前記第一の半導体素子主面の前記パッドと前記第二の半導体素子主面の前記パッドとを電気的に接続する第三の配線を備え、前記第一の半導体素子主面の前記パッドと前記第一の半導体素子主面の前記パッドが配列していない辺に隣接する前記基板主面の外周辺に沿って配列した前記電極との電気的接続を、前記第二の半導体素子に形成した前記第一の配線を経由して行うものである。
【０００８】
また、第二の発明に係る半導体装置は、第一の半導体素子が、前記第一の半導体素子主面の対向する二辺それぞれに、前記辺に沿って二列以上に配列したパッドを備えたものである。
【０００９】
【発明の実施の形態】
実施の形態１．
図１はこの発明の実施の形態１による半導体装置のモールド樹脂の上半分を破断して示す平面図（ａ）、及びそのＩＩ−ＩＩ断面図（ｂ）である。図において、１は半導体装置、２ａはパッド４ａを対向する主面二辺に沿って配列した第一の半導体素子、２ｂは第二の半導体素子で、第二の半導体素子２ｂは、第一の半導体素子２ａのパッド４ａと第三の配線である金線６ｂで電気的に接続されたパッド４ｂと、第一の半導体素子２ａおよび第二の半導体素子２ｂを載置する基板であるダイパッド３の外周辺に沿って配列した電極であるインナーリード５と第二の配線である金線６ｃで電気的に接続されたパッド４ｃと、パッド４ｂとパッド４ｃとを接続する第一の配線であるアルミ配線８からなる。なお、アルミ配線８はスパッタリング等により第二の半導体装置２ｂの層間膜（図示せず）中に形成したものである。６ａは、半導体素子２ａのパッド４ａとパッド４ａが配列されている半導体素子２ａの辺に隣接するダイパッド３の外周辺に沿って配列するインナーリード５とを接続する金線、７は半導体素子２ａ、２ｂや金線６ａ，６ｂを保護するためのモールド樹脂である。
【００１０】
次にこの半導体装置１のアセンブリ方法について説明する。ダイボンダー（図示せず）を使い第一の半導体素子２ａとダイパッド３を接着剤（図示せず）で接着する。次に同じくダイボンダーで半導体素子２ｂと半導体素子２ａを接着剤で接着する。次にワイヤーボンダーを使い、パッド４ａとインナーリード５、パッド４ａとパッド４ｂ、パッド４ｃとインナーリード５をそれぞれ金線６ａ、６ｂ、６ｃで接続する。次に半導体素子２ａ、２ｂを載置したダイパッド３をモールド装置の金型（図示せず）に入れ、図中のモールド樹脂注入方向と記載した方向よりモールド樹脂７を流し込み成型する。最後にインナーリード５のモールド樹脂７から突出した部分をリード加工装置（図示せず）で切断及び成型し、半導体装置１は完成する。前記のとおり、この発明の実施の形態１による半導体装置は既存のアセンブリ技術で製造することが可能である。
【００１１】
この発明の実施の形態１の半導体装置１によれば、パッド４ａと第一の半導体素子２ａ主面のパッド４ａが配列していない辺に隣接する基板３主面の外周辺に沿って配列した電極５との電気的接続を、バッド４ｂ、アルミ配線８、及びパッド４ｃを経由して行うため、パッド４ｂを接続すべきパッド４ａと接続し易い位置に配置し、パッド４ｃを接続すべき電極５と接続し易い位置に配置すれば、対向する主面二辺に沿って配列したパッド４ａを持つ半導体素子２ａを、基板３主面の全外周辺に沿って配列した電極５を持つパッケージに容易にアセンブリすることができる。なお、アルミ配線８はほとんど配線レイアウト上の制約が無いので、接続すべきパッド４ｂとパッド４ｃはどのような位置関係でも構わない。
【００１２】
なお、実施の形態１の第二の半導体素子２ｂはパッド４ｂ、４ｃおよびアルミ配線８だけを形成した専用の半導体素子としているが、他の機能を実現するための回路を持った半導体素子にパッド４ｂ、４ｃおよびアルミ配線８を形成し、第二の半導体素子２ｂとしても構わない。これにより半導体素子２ｂをより有効に利用することができる。
【００１３】
実施の形態２．
図２はこの発明の実施の形態２による半導体装置のモールド樹脂の上半分を破断して示す透視平面図である。図１と同一または相当の部分には同一符号を付してその説明を省略する。実施の形態１の半導体装置１が、第一の半導体素子２ａの上に第二の半導体素子２ｂを載置したものであるのに対し、この実施の形態２の半導体装置１は、第二の半導体素子２ｂの上に第一の半導体素子２ａを載置したものである。本構造にすることにより、第二の半導体素子２ｂの面積が第一の半導体素子２ａの面積より大きい場合にも、第二の半導体素子２ｂを経由して第一の半導体素子２ａのパッド４ａとインナーリード５との接続が実現できる。
【００１４】
実施の形態３．
図３はこの発明の実施の形態３による半導体装置のモールド樹脂の上半分を破断して示す平面図である。図１と同一または相当の部分には同一符号を付してその説明を省略する。実施の形態３の半導体装置１は、半導体素子２ａの対向する二辺にパッド４ａをそれぞれ２列配列したものである。本構造にすることによりウエハテストにおけるプロービングの容易性をそこなうことなく、より多くのパッド２ａを半導体素子上に設けることができる。なお、各辺にパッド４ａを３列以上配置しても構わず、これにより配置可能なパッド数をより増加させることができる。
【００１５】
実施の形態４．
図４はこの発明の実施の形態４による半導体装置のモールド樹脂の上半分を破断して示す透視平面図（ａ）、及びそのＩＩＩ−ＩＩＩ断面図（ｂ）である。実施の形態４は、発明の構成をＢＧＡ（Ｂａｌｌ　Ｇｒｉｄ　Ａｒｒａｙ）に適用したもので、３は半導体素子２ａ、２ｂを載置する基板であるガラスエポキシ基板、５はガラスエポキシ基板に設けられた電極、９はハンダボールである。本発明によればＢＧＡにおいても、対向する主面二辺に沿って配列したパッドを持つ半導体素子を容易にアセンブリできる。
【００１６】
【発明の効果】
第一の発明に係る半導体装置は、主面の対向する二辺に沿って配列したパッドを備える第一の半導体素子主面のパッドと第一の半導体素子主面のパッドが配列していない辺に隣接する基板主面の外周辺に沿って配列した電極との電気的接続を、複数のパッドと複数のパッド相互を電気的に接続する第一の配線を主面に備えた第二の半導体素子の第一の配線を経由して行うものであるため、対向する主面二辺に沿って配列したパッドを持つ半導体素子を、半導体素子を載置する基板主面の全外周辺に沿って配列した電極を持つパッケージに容易にアセンブリすることができる。
【００１７】
また、第二の発明に係る半導体装置は、第一の半導体素子が主面の対向する二辺それぞれに、辺に沿って二列以上に配列したパッドを備えたものであるため、半導体素子の多パッド化にも対応できる。
【図面の簡単な説明】
【図１】この発明の実施の形態１による半導体装置のモールド樹脂の上半分を破断して示す平面図（ａ）及びそのＩＩ−ＩＩＩ断面図（ｂ）である。
【図２】この発明の実施の形態２による半導体装置のモールド樹脂の上半分を破断して示す平面図である。
【図３】この発明の実施の形態３による半導体装置のモールド樹脂の上半分を破断して示す平面図である。
【図４】この発明の実施の形態４による半導体装置のモールド樹脂の上半分を破断して示す透視平面図（ａ）及びそのＩＩＩ−ＩＩＩ断面図（ｂ）である。
【符号の説明】
１　　　　　　　　　　半導体装置
２ａ　　　　　　　　　第一の半導体素子
２ｂ　　　　　　　　　第二の半導体素子
３　　　　　　　　　　基板
４ａ、４ｂ、４ｃ　　　パッド
５　　　　　　　　　　電極
６ａ、６ｃ　　　　　　第二の配線
６ｂ　　　　　　　　　第三の配線
８　　　　　　　　　　第一の配線

Claims (2)

  1. 主面の対向する二辺に沿って配列したパッドを備える第一の半導体素子と、複数のパッドとこの複数のパッド相互を電気的に接続する第一の配線を主面に備えた第二の半導体素子と、前記第一の半導体素子および前記第二の半導体素子を載置する基板と、前記第一の半導体素子主面の前記パッドおよび前記第二の半導体素子主面の前記パッドと前記基板主面の全ての外周辺に沿って配列した電極とを電気的に接続する第二の配線と、前記第一の半導体素子主面の前記パッドと前記第二の半導体素子主面の前記パッドとを電気的に接続する第三の配線を備え、前記第一の半導体素子主面の前記パッドと前記第一の半導体素子主面の前記パッドが配列していない辺に隣接する前記基板主面の外周辺に沿って配列した前記電極との電気的接続を、前記第二の半導体素子に形成した前記第一の配線を経由して行うことを特徴とする半導体装置。
  2. 第一の半導体素子が、前記第一の半導体素子主面の対向する二辺それぞれに、前記辺に沿って二列以上に配列したパッドを備えたことを特徴とする、請求項１記載の半導体装置。
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JP2015153985A (ja) * 2014-02-18 2015-08-24 株式会社デンソー 半導体パッケージ
US9293399B2 (en) 2013-09-27 2016-03-22 Rohm Co., Ltd. Semiconductor device and electronic unit provided with the same

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TWI233674B (en) * 2003-07-29 2005-06-01 Advanced Semiconductor Eng Multi-chip semiconductor package and manufacturing method thereof
US20050248028A1 (en) * 2004-05-05 2005-11-10 Cheng-Yen Huang Chip-packaging with bonding options connected to a package substrate
JP4786976B2 (ja) * 2005-09-13 2011-10-05 パナソニック株式会社 配線基板及びその製造方法、並びに半導体装置
US8922028B2 (en) * 2007-02-13 2014-12-30 Advanced Semiconductor Engineering, Inc. Semiconductor package
KR100798896B1 (ko) * 2007-06-07 2008-01-29 주식회사 실리콘웍스 반도체 칩의 패드 배치 구조
US20100320591A1 (en) * 2009-06-19 2010-12-23 Zigmund Ramirez Camacho Integrated circuit packaging system with contact pads and method of manufacture thereof

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JP2800761B2 (ja) 1996-02-23 1998-09-21 日本電気株式会社 マルチチップ半導体装置
JPH11220091A (ja) 1998-02-02 1999-08-10 Toshiba Microelectronics Corp 半導体装置
US6159765A (en) * 1998-03-06 2000-12-12 Microchip Technology, Incorporated Integrated circuit package having interchip bonding and method therefor

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US9293399B2 (en) 2013-09-27 2016-03-22 Rohm Co., Ltd. Semiconductor device and electronic unit provided with the same
JP2015153985A (ja) * 2014-02-18 2015-08-24 株式会社デンソー 半導体パッケージ

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