JP2004007005A - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
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- JP2004007005A JP2004007005A JP2003322604A JP2003322604A JP2004007005A JP 2004007005 A JP2004007005 A JP 2004007005A JP 2003322604 A JP2003322604 A JP 2003322604A JP 2003322604 A JP2003322604 A JP 2003322604A JP 2004007005 A JP2004007005 A JP 2004007005A
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- base substrate
- electrode pad
- pellet
- semiconductor device
- semiconductor
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Abstract
【解決手段】 ベース基板1の主面のペレット搭載領域上に半導体ペレット2が搭載され、前記半導体ペレット2の主面に配置された外部端子2Aに前記ベース基板1の裏面に配置された第1電極パッド1Bが電気的に接続される半導体装置において、前記ベース基板1をリジット基板で構成し、前記ベース基板1の第1電極パッド1Bをその裏面に配置された第2電極パッド1Aに電気的に接続し、前記半導体ペレット2をその主面を下にして前記ベース基板1の主面のペレット搭載領域上に搭載し、前記半導体ペレット2の外部端子2Aと前記ベース基板1の第2電極パッド1Aとを前記ベース基板1に形成されたスリット5を通してボンディングワイヤ6で電気的に接続する。
【選択図】 図3
Description
前記ベース基板1の第1電極パッド1Bの表面上にはバンプ電極4が電気的及び機械的に接続される。バンプ電極4は例えばPb−Sn系の合金材で形成される。
このように構成されるBGA構造の半導体装置は実装基板の実装面上に実装され、そのバンプ電極4は実装基板の実装面に配置された電極パッドに電気的及び機械的に接続される。
このように構成される半導体装置は実装基板の実装面上に実装され、そのバンプ電極は実装基板の実装面に配置された電極パッドに電気的及び機械的に接続される。
一方、半導体ペレット2に搭載される回路システムは高集積化の傾向にあり、この回路システムの高集積化に伴って半導体ペレット2の外部端子2Aの数及びベース基板1の第2電極パッド1Aの数は増加する。つまり、回路システムの高集積化に伴い、第2電極パッド1Aと第1電極パッド1Bとを電気的に接続するスルーホール配線1Cの数は増加する。このため、スルーホール配線1Cの数に相当する分、ベース基板1の外形サイズが増加し、半導体装置が大型化する問題があった。
本発明の他の目的は、前記半導体装置の動作速度の高速化を図ることが可能な技術を提供することにある。
本発明の他の目的は、半導体装置の電気的信頼性を高めることが可能な技術を提供することにある。
本発明の他の目的は、半導体装置の実装精度を高めることが可能な技術を提供することにある。
本発明の他の目的は、前記目的を達成する半導体装置の製造技術を提供することにある。
本発明の前記ならびにその他の目的と新規な特徴は、本明細書の記述及び添付図面によって明らかになるであろう。
(1)ベース基板の主面のペレット搭載領域上に半導体ペレットが搭載され、前記半導体ペレットの主面に配置された外部端子に前記ベース基板の裏面に配置された第1電極パッドが電気的に接続される半導体装置において、前記ベース基板をリジット基板で構成し、前記ベース基板の第1電極パッドをその裏面に配置された第2電極パッドに電気的に接続し、前記半導体ペレットをその主面を下にして前記ベース基板の主面のペレット搭載領域上に搭載し、前記半導体ペレットの外部端子と前記ベース基板の第2電極パッドとを前記ベース基板に形成されたスリットを通してボンディングワイヤで電気的に接続する。
(2)ベース基板の主面のペレット搭載領域上に半導体ペレットが搭載され、前記半導体ペレットの主面に配置された外部端子に前記ベース基板の裏面に配置された第1電極パッドが電気的に接続される半導体装置の製造方法において、リジット基板で構成されたベース基板の主面のペレット搭載領域上に半導体ペレットをその主面を下にして搭載する工程と、前記半導体ペレットの外部端子と前記ベース基板の第1電極パッドに電気的に接続され、かつ前記ベース基板の裏面に配置された第2電極パッドとを前記ベース基板に形成されたスリットを通してボンディングワイヤで電気的に接続する工程とを備える。
ベース基板の主面のペレット搭載面上に半導体ペレットが搭載され、前記半導体ペレットの主面に配置された外部端子に前記ベース基板の裏面に配置された第1電極パッドが電気的に接続される半導体装置の小型化を図ることができる。
また、前記半導体装置の動作速度の高速化を図ることができる。
また、前記半導体装置の電気的信頼性を高めることができる。
また、前記半導体装置の実装精度を高めることができる。
なお、実施例を説明するための全図において、同一機能を有するものは同一符号を付け、その繰り返しの説明は省略する。
本発明の実施例1であるBGA構造を採用する半導体装置の概略構成を図1(主面側の平面図)、図2(図1に示すA−A線の位置で切った断面図)、図3(図2の要部拡大断面図)及び図4(裏面側の樹脂封止体を除去した状態を示す裏面側の要部拡大平面図)に示す。
前記第1電極パッド1Bの表面には、バンプ電極4が電気的及び機械的に接続される。このバンプ電極4は例えばPb−Sn系の合金材で形成される。
前記半導体ペレット2の主面と対向するその裏面はベース基板1の周辺領域上を覆う樹脂封止体7から露出される。
前記凹部12には、図示していないが、気泡の巻き込みによるボイドの発生を防止する目的として、ガス抜き孔が設けられる。
まず、リジット基板で構成されたベース基板1を用意する。ベース基板1にはスリット5が形成され、その裏面には第2電極パッド(1A)、第1電極パッド(1B)、配線(1B1)の夫々が配置される。
次に、ボンディングステージ(ヒートブロック)14上に前記半導体ペレット2を下にして前記ベース基板1を装着する。ボンディングステージ14には、半導体ペレット2を収納する凹部14Aが形成される。ベース基板1、半導体ペレット2の夫々はボンディングステージ14で200[℃]前後に加熱される。
(1)ベース基板1の主面のペレット搭載領域上に半導体ペレット2が搭載され、前記半導体ペレット2の主面に配置された外部端子2Aに前記ベース基板1の裏面に配置された第1電極パッド1Bが電気的に接続される半導体装置において、前記ベース基板1をリジット基板で構成し、前記ベース基板1の第1電極パッド1Bをその裏面に配置された第2電極パッド1Aに電気的に接続し、前記半導体ペレット2をその主面を下にして前記ベース基板1の主面のペレット搭載領域上に搭載し、前記半導体ペレット2の外部端子2Aと前記ベース基板1の第2電極パッド1Aとを前記ベース基板1に形成されたスリット5を通してボンディングワイヤ6で電気的に接続する。この構成により、半導体ペレット2の外部端子2Aとベース基板1の電極パッド1Bとをボンディングワイヤ6、電極パッド1Aの夫々を介して電気的に接続することができるので、第2電極パッド1Aと第1電極パッド1Bとを電気的に接続するスルーホール配線を廃止することができる。この結果、スルーホール配線の占有面積(ランド領域の面積)に相当する分、ベース基板1の外形サイズを縮小することができるので、半導体装置の小型化を図ることができる。
また、ベース基板1の機械的強度を樹脂封止体7の機械的強度で補うことができるので、実装時のリフロー熱によるベース基板1の変形(反り、ねじれ等)を防止することができる。
本発明の実施例2であるBGA構造を採用する半導体装置の概略構成を図12(断面図)及び図13(裏面側の樹脂封止体を除去した状態を示す裏面側の要部拡大平面図)に示す。
本発明の実施例3であるBGA構造を採用する半導体装置の概略構成を図14(裏面側の樹脂封止体を除去した状態を示す裏面側の要部平面図)に示す。
本発明の実施例4であるBGA構造を採用する半導体装置の概略構成を図15(裏面側の樹脂封止体を除去した状態を示す裏面側の要部平面図)に示す。
1A:電極パッド
1B:電極パッド
2:半導体ペレット
2A:外部端子
3:絶縁層
4:バンプ電極
5:スリット
6:ボンディングワイヤ
7:樹脂封止体
7A:樹脂
8A,8B:電極プレート
10:成形金型
10A:上型
10B:下型
11:キャビティ
11A,11B,12:凹部
13:流入ゲート
14:ヒートステージ
14A:凹部
15:実装基板
15A:電極パッド
Claims (9)
- ベース基板の主面のペレット搭載領域上に半導体ペレットが搭載され、前記半導体ペレットの主面に配置された外部端子に前記ベース基板の裏面に配置された第1電極パッドが電気的に接続される半導体装置において、前記ベース基板がリジット基板で構成され、前記ベース基板の第1電極パッドがその裏面に配置された第2電極パッドに電気的に接続され、前記半導体ペレットがその主面を下にして前記ベース基板の主面のペレット搭載領域上に搭載され、前記半導体ペレットの外部端子と前記ベース基板の第2電極パッドとが前記ベース基板に形成されたスリットを通してボンディングワイヤで電気的に接続されることを特徴とする半導体装置。
- 前記スリットは、前記半導体ペレットの主面に複数配列された外部端子の配列方向に沿って形成され、かつ前記半導体ペレットの外部端子上に配置されることを特徴とする請求項1に記載の半導体装置。
- 前記ベース基板の第2電極パッドは、前記スリットで仕切られたベース基板の裏面の両脇の夫々の領域に配置されることを特徴とする請求項1又は請求項2に記載の半導体装置。
- 前記スリットで仕切られたベース基板の裏面の一方の領域に配置される第2電極パッドには電源が印加され、前記スリットで仕切られたベース基板の裏面の他方の領域に配置される第2電極パッドには信号が印加されることを特徴とする請求項3に記載の半導体装置。
- 前記半導体ペレットの裏面は、前記ベース基板の主面の周辺領域上を覆う樹脂封止体から露出されることを特徴とする請求項1乃至請求項4のうちいずれか1項に記載の半導体装置。
- 前記ボンディングワイヤは樹脂封止体で封止されることを特徴とする請求項1乃至請求項5のうちいずれか1項に記載の半導体装置。
- 前記ベース基板の第1電極パッドの表面上には、バンプ電極が電気的及び機械的に接続されることを特徴とする請求項1乃至請求項6のうちいずれか1項に記載の半導体装置。
- ベース基板の主面のペレット搭載領域上に半導体ペレットが搭載され、前記半導体ペレットの主面に配置された外部端子に前記ベース基板の裏面に配置された第1電極パッドが電気的に接続される半導体装置の製造方法において、リジット基板で構成されたベース基板の主面のペレット搭載領域上に半導体ペレットをその主面を下にして搭載する工程と、前記半導体ペレットの外部端子と前記ベース基板の第1電極パッドに電気的に接続され、かつ前記ベース基板の裏面に配置された第2電極パッドとを前記ベース基板に形成されたスリットを通してボンディングワイヤで電気的に接続する工程とを備えたことを特徴とする半導体装置の製造方法。
- 前記ボンディングワイヤで電気的に接続する工程の後に、前記ベース基板の主面の周辺領域上を覆い、かつ前記ボンディングワイヤを封止する樹脂封止体をトランスファモールド法で形成する工程を備えたことを特徴とする請求項8に記載の半導体装置の製造方法。
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Publication number | Priority date | Publication date | Assignee | Title |
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WO2006030517A1 (ja) * | 2004-09-17 | 2006-03-23 | Fujitsu Limited | 半導体装置及びその製造方法 |
KR100743319B1 (ko) | 2005-05-31 | 2007-07-26 | 가부시끼가이샤 도시바 | 표면 실장형 반도체 장치 및 그 제조 방법 |
KR100886441B1 (ko) * | 2007-03-13 | 2009-03-04 | 후지쯔 마이크로일렉트로닉스 가부시키가이샤 | 반도체 장치 및 그 제조 방법 |
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Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
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WO2006030517A1 (ja) * | 2004-09-17 | 2006-03-23 | Fujitsu Limited | 半導体装置及びその製造方法 |
JPWO2006030517A1 (ja) * | 2004-09-17 | 2008-05-08 | 富士通株式会社 | 半導体装置及びその製造方法 |
JP4503611B2 (ja) * | 2004-09-17 | 2010-07-14 | 富士通セミコンダクター株式会社 | 半導体装置及びその製造方法 |
KR100743319B1 (ko) | 2005-05-31 | 2007-07-26 | 가부시끼가이샤 도시바 | 표면 실장형 반도체 장치 및 그 제조 방법 |
KR100886441B1 (ko) * | 2007-03-13 | 2009-03-04 | 후지쯔 마이크로일렉트로닉스 가부시키가이샤 | 반도체 장치 및 그 제조 방법 |
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