JP2003282755A - Package for housing semiconductor element and semiconductor device - Google Patents

Package for housing semiconductor element and semiconductor device

Info

Publication number
JP2003282755A
JP2003282755A JP2002086697A JP2002086697A JP2003282755A JP 2003282755 A JP2003282755 A JP 2003282755A JP 2002086697 A JP2002086697 A JP 2002086697A JP 2002086697 A JP2002086697 A JP 2002086697A JP 2003282755 A JP2003282755 A JP 2003282755A
Authority
JP
Japan
Prior art keywords
semiconductor element
line conductor
conductor
circuit board
high resistance
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2002086697A
Other languages
Japanese (ja)
Other versions
JP3702241B2 (en
Inventor
Koki Kawabata
幸喜 川畑
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP2002086697A priority Critical patent/JP3702241B2/en
Publication of JP2003282755A publication Critical patent/JP2003282755A/en
Application granted granted Critical
Publication of JP3702241B2 publication Critical patent/JP3702241B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Landscapes

  • Semiconductor Lasers (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a package for housing semiconductor element that can prevent a housed semiconductor element from malfunctioning due to the high-frequency signal component of a terminating signal entering into a terminating electrode of the element by reflection. <P>SOLUTION: This package is provided with a substrate 1 having a placing section 1a for placing the semiconductor element 5 and a circuit board 6 on its upper main surface, the circuit board 6 placed on the section 1a, and a frame body 2 bonded to the outer peripheral section of the upper main surface of the substrate 1 so as to surround the section 1a. On the upper surface of the circuit board 6, a line conductor 6b and a grounding conductor 6c surrounding the conductor 6a are formed. The line conductor 6b is connected to the semiconductor element 5 on one end side and to the grounding conductor 6c through high-resistance sections 8 on the other end side. The sections 8 are roughly axially symmetrically disposed on both sides of the line conductor 6b from one end at distances of <1/2 wavelength of high-frequency signals of used frequencies. In addition, a resistor section 9 for attenuation matched to the characteristic impedance of the line conductor 6b is provided on the end face of the other end of the conductor 6b. <P>COPYRIGHT: (C)2004,JPO

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【発明の属する技術分野】本発明は、高周波信号で作動
する半導体素子を収納するための半導体素子収納用パッ
ケージに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor element housing package for housing a semiconductor element that operates with a high frequency signal.

【０００２】[0002]

【従来の技術】従来、マイクロ波帯やミリ波帯等の高周
波信号を用いる各種半導体素子を収納する半導体素子収
納用パッケージ（以下、半導体パッケージともいう）に
は、半導体素子を電気的に接続するための導体パターン
としての線路導体が設けられている。このような半導体
パッケージの断面図および上面図を図３に示す。同図に
おいて、31は基体、32は金属製の枠体、34は蓋体、36は
回路基板である。2. Description of the Related Art Conventionally, a semiconductor element is electrically connected to a semiconductor element housing package (hereinafter also referred to as a semiconductor package) for housing various semiconductor elements using high frequency signals such as microwaves and millimeter waves. A line conductor is provided as a conductor pattern for. A sectional view and a top view of such a semiconductor package are shown in FIG. In the figure, 31 is a base, 32 is a metal frame, 34 is a lid, and 36 is a circuit board.

【０００３】基体31は鉄（Ｆｅ）−ニッケル（Ｎｉ）−
コバルト（Ｃｏ）合金や銅（Ｃｕ）−タングステン
（Ｗ）等の金属から成る略四角形状の板状体であり、そ
の上側主面の略中央部には、ＩＣ，ＬＳＩ，半導体レー
ザ（ＬＤ），フォトダイオード（ＰＤ）等の半導体素子
35を搭載して成る回路基板36を載置する載置部31ａが形
成されている。載置部31ａには、半導体素子35が、例え
ばアルミナ（Ａｌ2Ｏ3），窒化アルミニウム（Ａｌ
Ｎ），ムライト（３Ａｌ2Ｏ3−２ＳｉＯ2）等のセラミ
ックスから成る回路基板36に搭載された状態で載置固定
される。The base 31 is iron (Fe) -nickel (Ni)-
It is a substantially rectangular plate-shaped body made of a metal such as a cobalt (Co) alloy or copper (Cu) -tungsten (W), and an IC, LSI, semiconductor laser (LD) is provided at a substantially central portion of its upper main surface. , Semiconductor elements such as photodiodes (PD)
A mounting portion 31a for mounting the circuit board 36 on which the 35 is mounted is formed. A semiconductor element 35, such as alumina (Al 2 O 3 ), aluminum nitride (Al
N), mullite (3Al 2 O 3 -2SiO 2 ), etc. are mounted and fixed on the circuit board 36 made of ceramics.

【０００４】回路基板36の下面には、接地導体層36ｄが
被着されており、銀（Ａｇ）ろう，Ａｇ−銅（Ｃｕ）ろ
う等のろう材や半田によって接地導体層36ｄと載置部31
ａが強固に接着固定される。A ground conductor layer 36d is deposited on the lower surface of the circuit board 36. The ground conductor layer 36d and the mounting portion are made of a brazing material such as silver (Ag) braze or Ag-copper (Cu) braze or solder. 31
a is firmly bonded and fixed.

【０００５】回路基板36に搭載された半導体素子35は、
その電極が回路基板36に被着されている第１の線路導体
36ａおよび第２の線路導体36ｂにそれぞれボンディング
ワイヤ37ａ，37ｂを介して電気的に接続されている。The semiconductor element 35 mounted on the circuit board 36 is
A first line conductor whose electrodes are attached to the circuit board 36.
36a and the second line conductor 36b are electrically connected via bonding wires 37a and 37b, respectively.

【０００６】さらに、第２の線路導体36ｂと接地導体36
ｃとは、高抵抗体部38を介して終端接続されており、接
地導体36ｃは接地導体36ｅを介して接地導体層36ｄに接
続されている。このように第２の線路導体36ｂの終端を
高抵抗体部38を介して接地導体36ｃに接続することによ
り、第２の線路導体36ｂに流れる高周波信号の反射を防
ぎ、半導体素子35が誤動作するのを防いでいる。Further, the second line conductor 36b and the ground conductor 36
c is connected to the ground conductor 36c via a high resistance portion 38, and the ground conductor 36c is connected to a ground conductor layer 36d via a ground conductor 36e. By thus connecting the end of the second line conductor 36b to the ground conductor 36c through the high resistance part 38, the reflection of the high frequency signal flowing through the second line conductor 36b is prevented and the semiconductor element 35 malfunctions. To prevent it.

【０００７】基体31の上側主面の外周部には載置部31ａ
を囲繞するようにして枠体32が立設されており、枠体32
は基体31とともにその内側に半導体素子35を収容する空
所を形成する。枠体32は基体31と同様にＦｅ−Ｎｉ−Ｃ
ｏ合金やＣｕ−Ｗの焼結材等から成り、基体31と一体成
形されるか、または基体31にＡｇろう、Ａｇ−Ｃｕろう
等のろう材を介してろう付けされるか、またはシーム溶
接法等の溶接法により接合されることによって基体31の
上側主面の外周部に立設される。A mounting portion 31a is provided on the outer peripheral portion of the upper main surface of the base 31.
The frame 32 is erected so as to surround the
Together with the base body 31 form a cavity for accommodating the semiconductor element 35 therein. The frame 32 is made of Fe-Ni-C like the substrate 31.
It is made of a sintered alloy of o alloy or Cu-W and is integrally molded with the base 31, or is brazed to the base 31 via a brazing material such as Ag brazing or Ag-Cu brazing, or is seam welded. It is erected on the outer peripheral portion of the upper main surface of the base 31 by being joined by a welding method such as a welding method.

【０００８】枠体32の側面にはグラスビーズ33が嵌着さ
れる貫通孔32ａが形成されており、貫通孔32ａ内にグラ
スビーズ33を嵌め込むとともに半田等の封着材を貫通孔
32ａ内の隙間に挿入し、しかる後、加熱して封着材を溶
融させ、溶融した封着材を毛細管現象によりグラスビー
ズ33と貫通孔32ａの内壁との隙間に充填させることによ
って、グラスビーズ33が貫通孔32ａ内に封着材を介して
嵌着接合される。A through hole 32a into which the glass bead 33 is fitted is formed on the side surface of the frame 32. The glass bead 33 is fitted into the through hole 32a and a sealing material such as solder is passed through the through hole 32a.
The glass beads are inserted into the gap in 32a and then heated to melt the sealing material, and the molten sealing material is filled into the gap between the glass beads 33 and the inner wall of the through hole 32a by a capillary phenomenon. 33 is fitted and joined in the through hole 32a via a sealing material.

【０００９】グラスビーズ33には、中心軸部分に信号線
路としてＦｅ−Ｎｉ−Ｃｏ合金等の金属から成る棒状の
中心導体33ａが固定されている。中心導体33ａは半田等
から成る導電性接着材を介して回路基板36の第１の線路
導体36ａに電気的に接続される。このグラスビーズ33に
は、外部電気回路（図示せず）に接続された同軸ケーブ
ル（図示せず）が装着されることによって、内部に収納
された半導体素子35がグラスビーズ33の中心導体33ａを
介して外部電気回路に電気的に接続されることとなる。A rod-shaped central conductor 33a made of a metal such as Fe-Ni-Co alloy is fixed to the glass bead 33 as a signal line on the central axis portion. The center conductor 33a is electrically connected to the first line conductor 36a of the circuit board 36 via a conductive adhesive material such as solder. A coaxial cable (not shown) connected to an external electric circuit (not shown) is attached to the glass beads 33, so that the semiconductor element 35 housed in the glass beads 33 has the central conductor 33a of the glass beads 33. It will be electrically connected to an external electric circuit via.

【００１０】最後に、基体31および枠体32から成る容器
内部に半導体素子35を収容し、枠体32の上面に蓋体34を
ろう付け法やシームウエルド法等の溶接法により接合
し、容器内部を気密に封止することによって製品として
の半導体装置となる。Finally, the semiconductor element 35 is housed in a container consisting of the base 31 and the frame 32, and the lid 34 is joined to the upper surface of the frame 32 by a welding method such as a brazing method or a seam weld method. A semiconductor device as a product is obtained by hermetically sealing the inside.

【００１１】[0011]

【発明が解決しようとする課題】しかしながら、従来の
半導体パッケージにおいては、半導体素子35の高周波化
が進むにつれ、第２の線路導体36ｂおよび接地導体36ｃ
間に形成される高抵抗体部38の抵抗値のバラツキが原因
となって、高抵抗体部38での高周波信号の反射によるノ
イズが発生し、そのノイズが半導体素子35内に入り込ん
で、半導体素子35の誤動作を発生させるといった問題点
が発生していた。However, in the conventional semiconductor package, the second line conductor 36b and the ground conductor 36c are increased as the frequency of the semiconductor element 35 is increased.
Due to the variation in the resistance value of the high resistance portion 38 formed between them, noise is generated due to the reflection of the high frequency signal in the high resistance portion 38, and the noise enters the semiconductor element 35, There has been a problem in that the element 35 malfunctions.

【００１２】また、マイクロ波帯やミリ波帯等の高周波
信号においては、高抵抗体部38から接地導体層36ｄまで
に形成される接地導体36ｃおよび36ｅのインダクタンス
成分によって、高抵抗体部38から見たインピーダンス値
が変動し、高抵抗体部38が所望の終端特性を得られない
という新たな問題が発生してきた。Further, in the case of a high frequency signal such as a microwave band or a millimeter wave band, the inductance components of the ground conductors 36c and 36e formed from the high resistance body portion 38 to the ground conductor layer 36d cause the high resistance body portion 38 to pass through. The observed impedance value fluctuates, and a new problem has arisen in that the high resistance portion 38 cannot obtain the desired termination characteristics.

【００１３】さらに、第２の線路導体36ｂの端部と高抵
抗体部38との間の長さが使用する高周波信号の波長の１
／２に等しくなる領域において、第２の線路導体36ｂ上
に共振による定在波が発生し、所望の終端特性が得られ
ないといった問題点も発生してきた。Furthermore, the length between the end of the second line conductor 36b and the high resistance portion 38 is one of the wavelengths of the high frequency signal used.
In a region equal to / 2, a standing wave due to resonance is generated on the second line conductor 36b, and there is a problem that desired termination characteristics cannot be obtained.

【００１４】本発明は上記問題点に鑑み完成されたもの
であり、その目的は、半導体素子の終端用電極に終端用
信号の高周波信号成分が反射して入り込んで半導体素子
が誤作動を起こすのを防ぐことができる、信頼性の高い
半導体素子収納用パッケージおよびこれを用いた半導体
装置を提供することにある。The present invention has been completed in view of the above problems, and an object thereof is that a high frequency signal component of a termination signal is reflected and enters the termination electrode of the semiconductor element to cause a malfunction of the semiconductor element. It is an object of the present invention to provide a highly reliable package for storing a semiconductor element and a semiconductor device using the same, which can prevent the above.

【００１５】[0015]

【課題を解決するための手段】本発明の半導体素子収納
用パッケージは、上側主面に半導体素子および回路基板
を載置するための載置部を有する基体と、前記載置部に
載置された前記回路基板と、前記上側主面の外周部に前
記載置部を囲繞するように接合された枠体とを具備して
成り、前記回路基板の上面に線路導体および該線路導体
を取り囲む接地導体が形成されており、前記線路導体は
一端が半導体素子に、他端が高抵抗体部を介して前記接
地導体に電気的に接続されており、前記高抵抗体部は前
記一端より前記半導体素子の使用周波数の高周波信号の
波長の１／２未満の距離の前記線路導体の両側に略線対
称に配設されているとともに、前記線路導体の前記他端
の端面に前記線路導体の特性インピーダンスと整合のと
れた減衰用抵抗体部を設けたことを特徴とするものであ
る。A package for accommodating a semiconductor element according to the present invention includes a base body having a mounting portion for mounting a semiconductor element and a circuit board on an upper main surface thereof, and the mounting portion for mounting the semiconductor element. And a frame body joined to the outer peripheral portion of the upper main surface so as to surround the mounting portion, and a line conductor and a ground surrounding the line conductor on the upper surface of the circuit substrate. A conductor is formed, one end of the line conductor is electrically connected to the semiconductor element, and the other end is electrically connected to the ground conductor via a high resistance body portion, and the high resistance body portion is the semiconductor from the one end. The line conductors are arranged substantially symmetrically on both sides of the line conductor at a distance less than 1/2 of the wavelength of the high frequency signal of the operating frequency of the element, and the characteristic impedance of the line conductor is provided on the end face of the other end of the line conductor. Damping resistor matched with The is characterized in that provided.

【００１６】本発明の半導体素子収納用パッケージによ
れば、回路基板の上面に線路導体およびこの線路導体を
取り囲む接地導体が形成されていることから、高抵抗体
部をこの接地導体に直接接続することによって、高抵抗
体部から接地導体までの寄生インダクタンス成分や寄生
キャパシタンス成分を低減することができる。このよう
な寄生インダクタンス成分や寄生キャパシタンス成分は
周波数に依存してインピーダンス値を変動させるため、
高抵抗体部から接地導体までの寄生インダクタンス成分
や寄生キャパシタンス成分を低減できることにより線路
導体の他端側に接続された高抵抗体部から見た線路導体
のインピーダンス値の変動を小さくすることができ、そ
の結果、半導体素子の終端用電極に接続される線路導体
について高周波帯域までも安定した終端特性を得ること
が可能となる。According to the semiconductor element housing package of the present invention, since the line conductor and the ground conductor surrounding the line conductor are formed on the upper surface of the circuit board, the high resistance portion is directly connected to the ground conductor. As a result, the parasitic inductance component and the parasitic capacitance component from the high resistance portion to the ground conductor can be reduced. Since such parasitic inductance component and parasitic capacitance component change the impedance value depending on the frequency,
By reducing the parasitic inductance component and parasitic capacitance component from the high resistance part to the ground conductor, it is possible to reduce the fluctuation of the impedance value of the line conductor seen from the high resistance part connected to the other end of the line conductor. As a result, it is possible to obtain stable termination characteristics even in the high frequency band of the line conductor connected to the termination electrode of the semiconductor element.

【００１７】さらに、線路導体の他端を接地導体に電気
的に接続する高抵抗体部を、線路導体を挟んでその両側
に略線対称に２個以上配設したことにより、高抵抗体部
の１つ当りに要求される抵抗値のバラツキの範囲を緩和
することができると同時に、高抵抗体部に発生する寄生
インダクタンス成分を低減することができるため、線路
導体について高周波帯域まで使用可能な終端抵抗を得る
ことが可能となる。Further, by arranging two or more high-resistor portions electrically connecting the other end of the line conductor to the ground conductor on both sides of the line conductor in a line-symmetric manner, the high-resistor portion is formed. It is possible to reduce the range of variation in the resistance value required for each one, and at the same time, it is possible to reduce the parasitic inductance component generated in the high resistance part, so that the line conductor can be used up to a high frequency band. It is possible to obtain a terminating resistance.

【００１８】さらにまた、高抵抗体部を半導体素子に接
続される側の線路導体の一端より半導体素子の使用周波
数の高周波信号の波長の１／２未満の距離に配設するこ
とにより、線路導体の一端と高抵抗体部との接続部との
間に発生する高周波信号に対する共振現象を使用周波数
よりも高周波側へとシフトさせることができるため、使
用周波数において共振現象が発生することがなく、使用
周波数の高周波信号に対して良好な伝送特性を得ること
が可能となる。Furthermore, by arranging the high resistance portion at a distance less than 1/2 of the wavelength of the high frequency signal of the operating frequency of the semiconductor element from one end of the line conductor connected to the semiconductor element, Since it is possible to shift the resonance phenomenon for the high frequency signal generated between one end of the and the connection portion of the high resistance portion to a higher frequency side than the use frequency, the resonance phenomenon does not occur at the use frequency, It becomes possible to obtain good transmission characteristics for a high frequency signal of the used frequency.

【００１９】そして、線路導体の高抵抗体部が接続され
た他端の端面に線路導体の特性インピーダンスと整合の
とれた減衰用抵抗体部を設けたことにより、高抵抗体部
で終端しきれない場合の高周波信号をこの減衰用抵抗体
部でもって効果的に減衰させることができ、より効果的
にノイズを抑制することが可能となる。By providing the damping resistor portion matching the characteristic impedance of the line conductor on the end face of the other end to which the high resistance portion of the line conductor is connected, the end of the high resistance portion can be terminated. The high-frequency signal when there is no signal can be effectively attenuated by the attenuating resistor portion, and noise can be suppressed more effectively.

【００２０】従って、本発明の半導体素子収納用パッケ
ージは、以上のような構成により、線路導体を伝わる高
周波信号の反射によるノイズや共振が発生することを防
止し、半導体素子を正常に作動させることができる。Therefore, the package for storing a semiconductor element of the present invention is configured as described above to prevent noise and resonance due to the reflection of the high frequency signal transmitted through the line conductor and to operate the semiconductor element normally. You can

【００２１】また、本発明の半導体装置は、上記構成の
本発明の半導体素子収納用パッケージと、前記回路基板
上に載置された前記半導体素子と、前記枠体の上面に接
合された蓋体とを具備したことを特徴とするものであ
る。Further, the semiconductor device of the present invention is a semiconductor element housing package of the present invention having the above-mentioned configuration, the semiconductor element mounted on the circuit board, and a lid body joined to the upper surface of the frame body. And is provided.

【００２２】本発明の半導体装置によれば、このような
構成により、半導体素子の終端用電極に終端用信号の高
周波信号成分が反射して入り込んで半導体素子が誤作動
を起こすのを防ぐことができる、信頼性の高い半導体装
置を提供することができる。According to the semiconductor device of the present invention, with such a structure, it is possible to prevent the high frequency signal component of the termination signal from being reflected and entering the termination electrode of the semiconductor element to cause the semiconductor element to malfunction. It is possible to provide a highly reliable semiconductor device.

【００２３】[0023]

【発明の実施の形態】本発明の半導体素子収納用パッケ
ージについて以下に詳細に説明する。図１は本発明の半
導体素子収納用パッケージの実施の形態の一例を示す断
面図および上面図であり、１は基体、２は枠体、４は蓋
体、６は回路基板である。BEST MODE FOR CARRYING OUT THE INVENTION The semiconductor element housing package of the present invention will be described in detail below. FIG. 1 is a cross-sectional view and a top view showing an example of an embodiment of a package for housing a semiconductor element of the present invention, in which 1 is a base, 2 is a frame, 4 is a lid, and 6 is a circuit board.

【００２４】基体１は、Ｆｅ−Ｎｉ−Ｃｏ合金等の金属
やＣｕ−Ｗの焼結材等から成る略四角形の板状体であ
り、そのインゴットに圧延加工や打ち抜き加工等の従来
周知の金属加工法、または射出成形と切削加工等を施す
ことによって、所定の形状に製作される。基体１の上側
主面の略中央部には、ＩＣ，ＬＳＩ，ＬＤ，ＰＤ等の半
導体素子５を載置するための載置部１ａが形成されてお
り、載置部１ａには半導体素子５が、例えばＡｌ2Ｏ3，
ＡｌＮ，３Ａｌ2Ｏ3−２ＳｉＯ2等のセラミックスから
成る回路基板６に搭載された状態で載置固定される。回
路基板６の下面には接地導体層６ｄが被着形成されてお
り、Ａｇろう，Ａｇ−Ｃｕろう等のろう材やＡｕ−Ｓｎ
半田，Ｐｂ−Ｓｎ半田等の半田によって接地導体層６ｄ
と載置部１ａとが強固に接着固定される。The substrate 1 is a substantially rectangular plate-like body made of a metal such as Fe-Ni-Co alloy or a sintered material of Cu-W. The ingot is a conventionally known metal such as rolled or punched. It is manufactured into a predetermined shape by a processing method, or injection molding and cutting. A mounting portion 1a for mounting a semiconductor element 5 such as an IC, LSI, LD, PD or the like is formed in a substantially central portion of the upper main surface of the base body 1, and the semiconductor element 5 is mounted on the mounting portion 1a. Is, for example, Al 2 O 3 ,
The circuit board 6 made of ceramics such as AlN and 3Al 2 O 3 -2SiO 2 is mounted and fixed in a mounted state. A ground conductor layer 6d is formed on the lower surface of the circuit board 6 by using a brazing material such as Ag brazing or Ag-Cu brazing or Au-Sn.
Ground conductor layer 6d by solder such as solder or Pb-Sn solder
And the mounting portion 1a are firmly bonded and fixed.

【００２５】半導体素子５は、その電極が回路基板６の
上面に被着形成されている第１の線路導体６ａおよび第
２の線路導体６ｂにそれぞれボンディングワイヤ７ａ，
７ｂを介して電気的に接続される。The semiconductor element 5 has bonding electrodes 7a, 6b on the first and second line conductors 6a and 6b, respectively, the electrodes of which are adhered to the upper surface of the circuit board 6.
It is electrically connected via 7b.

【００２６】回路基板６は、例えばＡｌ2Ｏ3セラミック
スから成る場合、以下のようにして作製される。まず、
Ａｌ2Ｏ3，酸化珪素（ＳｉＯ2），酸化カルシウム（Ｃ
ａＯ），酸化マグネシウム（ＭｇＯ）等の原料粉末に適
当な有機バインダや可塑剤，分散剤，溶剤等を添加混合
して泥漿状となす。これを従来周知のドクターブレード
法でシート状となすことによってセラミックグリーンシ
ートを得る。しかる後、このセラミックグリーンシート
に適当な打ち抜き加工を施す、または、Ａｌ2Ｏ3，Ｓｉ
Ｏ2，ＣａＯ，ＭｇＯ等の原料粉末を金型に充填しプレ
ス成型することによって、所定の形状に成形する。その
セラミックグリーンシートに上面の第１の線路導体６
ａ，第２の線路導体６ｂおよび上面の接地導体６ｃ，端
面の接地導体６ｅ，下面の接地導体層６ｄとなる金属ペ
ーストを印刷塗布し、還元雰囲気中で約1600℃の温度で
焼成することによって製作される。When the circuit board 6 is made of Al 2 O 3 ceramics, for example, it is manufactured as follows. First,
Al 2 O 3 , silicon oxide (SiO 2 ), calcium oxide (C
aO), magnesium oxide (MgO), and other raw material powders are mixed with an appropriate organic binder, plasticizer, dispersant, solvent, etc. to form a slurry. A ceramic green sheet is obtained by forming this into a sheet by a conventionally known doctor blade method. Then, the ceramic green sheet is punched appropriately, or Al 2 O 3 , Si is used.
A raw material powder such as O 2 , CaO, and MgO is filled in a mold and press-molded to form a predetermined shape. The first line conductor 6 on the upper surface of the ceramic green sheet
a, the second line conductor 6b and the ground conductor 6c on the upper surface, the ground conductor 6e on the end surface, and the metal conductor to be the ground conductor layer 6d on the lower surface are printed and applied, and fired at a temperature of about 1600 ° C. in a reducing atmosphere. Produced.

【００２７】第１の線路導体６ａ，第２の線路導体６ｂ
および接地導体６ｃ，６ｅ，接地導体層６ｄとなる金属
ペーストは、Ｗ，モリブデン（Ｍｏ），マンガン（Ｍ
ｎ）等の高融点金属粉末に適当な有機バインダや溶剤を
添加混合してペースト状となしたものを従来周知のスク
リーン印刷法を採用して印刷することにより、セラミッ
クグリーンシートまたはセラミックスの成形体に印刷塗
布される。The first line conductor 6a and the second line conductor 6b
The metal paste to be the ground conductors 6c and 6e and the ground conductor layer 6d is W, molybdenum (Mo), manganese (M).
n) or the like, a high melting point metal powder to which a suitable organic binder or solvent is added and mixed to form a paste, which is printed by using a conventionally known screen printing method to form a ceramic green sheet or a ceramic molded body. Printed on.

【００２８】なお、第１の線路導体６ａ，第２の線路導
体６ｂおよび接地導体６ｃ，６ｅ，接地導体層６ｄは薄
膜形成法によって形成されていても良く、第１の線路導
体６ａ，第２の線路導体６ｂおよび接地導体６ｃ，６
ｅ，接地導体層６ｄは、窒化タンタル（Ｔａ2Ｎ），ニ
クロム（Ｎｉ−Ｃｒ合金），チタン（Ｔｉ），パラジウ
ム（Ｐｄ），白金（Ｐｔ），Ａｕ等から形成され、セラ
ミックグリーンシートを焼成した後に形成される。The first line conductor 6a, the second line conductor 6b, the ground conductors 6c and 6e, and the ground conductor layer 6d may be formed by a thin film forming method. Line conductor 6b and ground conductors 6c, 6
e, the ground conductor layer 6d is formed of tantalum nitride (Ta 2 N), nichrome (Ni—Cr alloy), titanium (Ti), palladium (Pd), platinum (Pt), Au, etc., and fires the ceramic green sheet. Formed after.

【００２９】また、基体１の上側主面の外周部には載置
部１ａを囲繞するようにして枠体２が立設するように接
合されており、枠体２は基体１とともにその内側に半導
体素子５を収容する空所を形成する。この枠体２は、基
体１と同様にＦｅ−Ｎｉ−Ｃｏ合金やＣｕ−Ｗの焼結材
等から成り、基体１と一体成形される、または基体１に
Ａｇろう等のろう材を介してろう付けされる、またはシ
ーム溶接法等の溶接法により接合されることによって、
基体１の上側主面の外周部に立設される。Further, a frame body 2 is joined to the outer peripheral portion of the upper main surface of the base body 1 so as to stand upright so as to surround the mounting portion 1a. A void for accommodating the semiconductor element 5 is formed. The frame body 2 is made of a sintered material such as a Fe—Ni—Co alloy or Cu—W similar to the base body 1, and is integrally molded with the base body 1 or via a brazing material such as Ag brazing on the base body 1. By brazing or joining by welding methods such as seam welding,
It is erected on the outer peripheral portion of the upper main surface of the base 1.

【００３０】なお、枠体２は上記のような金属から成る
か、またはセラミックス等の誘電体材料から成りかつそ
の表面にメタライズ層等の導体層が形成されているのが
好ましい。このように枠体２を形成した場合には、内部
の半導体素子５によって発生する放射ノイズまでも効果
的に接地することができ、さらに半導体素子５の動作を
安定化させることが可能となる。It is preferable that the frame 2 is made of the above metal or a dielectric material such as ceramics and has a conductor layer such as a metallized layer formed on the surface thereof. When the frame body 2 is formed in this way, even radiation noise generated by the internal semiconductor element 5 can be effectively grounded, and the operation of the semiconductor element 5 can be stabilized.

【００３１】また、外部より半導体素子５に駆動信号等
を入力させる入出力端子として、例えばグラスビーズ３
が用いられ、以下のようにして枠体２に設置される。ま
ず、枠体２の側面にグラスビーズ３が嵌着される貫通孔
２ａを形成し、貫通孔２ａ内にグラスビーズ３を嵌め込
むとともにＡｕ−Ｓｎ半田やＰｂ−Ｓｎ半田等の封着材
を貫通孔２ａとの隙間に挿入する。しかる後、加熱して
封着材を溶融させ、溶融した封着材を毛細管現象により
グラスビーズ３と貫通孔２ａの内壁との隙間に充填する
ことによって、グラスビーズ３が貫通孔２ａ内に半田等
の封着材を介して嵌着接合される。Further, as an input / output terminal for inputting a driving signal or the like to the semiconductor element 5 from the outside, for example, the glass beads 3
Is used and is installed in the frame body 2 as follows. First, a through hole 2a into which the glass beads 3 are fitted is formed on the side surface of the frame body 2, the glass beads 3 are fitted into the through holes 2a, and a sealing material such as Au-Sn solder or Pb-Sn solder is attached. It is inserted in the gap with the through hole 2a. Thereafter, the sealing material is melted by heating, and the molten sealing material is filled in the gap between the glass beads 3 and the inner wall of the through hole 2a by a capillary phenomenon, so that the glass beads 3 are soldered into the through hole 2a. It is fitted and joined via a sealing material such as.

【００３２】グラスビーズ３は、内部に収容する半導体
素子５を外部電気回路に接続された同軸ケーブルに電気
的に接続するものであり、Ｆｅ−Ｎｉ−Ｃｏ合金等の金
属から成る円筒形等の筒状の外周導体にガラス等の絶縁
体が充填され、中心軸にＦｅ−Ｎｉ−Ｃｏ合金等の金属
から成る中心導体３ａが固定されて成る。この中心導体
３ａは半田等から成る導電性接着材を介して回路基板６
の第１の線路導体６ａに電気的に接続される。このグラ
スビーズ３に同軸ケーブルが装着されることによって、
半導体パッケージの内部に収納された半導体素子５がグ
ラスビーズ３の中心導体３ａを介して外部電気回路に電
気的に接続されることとなる。The glass beads 3 are for electrically connecting the semiconductor element 5 housed inside to a coaxial cable connected to an external electric circuit, and have a cylindrical shape or the like made of a metal such as Fe--Ni--Co alloy. An insulating material such as glass is filled in a cylindrical outer peripheral conductor, and a central conductor 3a made of a metal such as Fe—Ni—Co alloy is fixed to the central axis. The center conductor 3a is connected to the circuit board 6 via a conductive adhesive material such as solder.
Is electrically connected to the first line conductor 6a. By attaching a coaxial cable to this glass bead 3,
The semiconductor element 5 housed inside the semiconductor package is electrically connected to the external electric circuit via the central conductor 3a of the glass beads 3.

【００３３】そして、半導体素子５の電極と回路基板６
の上面に形成された第１の線路導体６ａとがボンディン
グワイヤ７ａにより電気的に接続され、第１の線路導体
６ａと中心導体３ａとが半田等の導電性接着材を介して
電気的に接続される。The electrodes of the semiconductor element 5 and the circuit board 6
Is electrically connected to the first line conductor 6a formed on the upper surface of the substrate by a bonding wire 7a, and the first line conductor 6a and the center conductor 3a are electrically connected to each other via a conductive adhesive material such as solder. To be done.

【００３４】また、図２は回路基板６上に形成された高
抵抗体部８の例を示す要部拡大上面図である。図２に示
す例によれば、回路基板６の上側主面に形成された第２
の線路導体６ｂは、一端が半導体素子５に電気的に接続
され、他端には高抵抗体部８が、半導体素子５に接続さ
れる側の第２の線路導体６ｂの端部より使用周波数の高
周波信号の波長λの１／２（λ／２）未満の距離の線路
導体６ｂを挟んでその両側に略線対称になるように２個
以上が配設されており、この他端が高抵抗体部８を介し
て、回路基板６の上面の略全周に第２の線路導体６ｂに
略平行に、かつこの線路導体６ｂを取り囲むように形成
された接地導体６ｃに接続されている。この場合、接地
導体６ｃは回路基板６の上面の略全面に設けられるのが
好ましく、このように接地導体６ｃを形成することによ
り、高抵抗体部８をこの接地導体６ｃに直接接続するこ
とによって、高抵抗体部８から接地導体６ｃまでの寄生
インダクタンス成分や寄生キャパシタンス成分を低減す
ることができ、その結果、線路導体６ｂの他端側に接続
された高抵抗体部８から見た線路導体６ｂのインピーダ
ンス値の変動を小さくすることができるため、第２の線
路導体６ｂについて高周波帯域まで良好な終端特性を得
ることが可能となる。Further, FIG. 2 is an enlarged top view of an essential part showing an example of the high resistance body portion 8 formed on the circuit board 6. According to the example shown in FIG. 2, the second main surface of the circuit board 6
Of the second line conductor 6b is electrically connected to the semiconductor element 5 at one end and the high resistance portion 8 is provided at the other end from the end of the second line conductor 6b on the side connected to the semiconductor element 5. The two or more pieces are arranged on both sides of the line conductor 6b having a distance less than 1/2 (λ / 2) of the wavelength λ of the high frequency signal so as to be substantially line-symmetrical, and the other end is high. The resistor 8 is connected to a ground conductor 6c which is formed substantially all around the upper surface of the circuit board 6 substantially in parallel with the second line conductor 6b and surrounding the line conductor 6b. In this case, the ground conductor 6c is preferably provided on substantially the entire upper surface of the circuit board 6. By forming the ground conductor 6c in this way, the high resistance part 8 is directly connected to the ground conductor 6c. The parasitic inductance component and the parasitic capacitance component from the high resistance body portion 8 to the ground conductor 6c can be reduced, and as a result, the line conductor viewed from the high resistance body portion 8 connected to the other end side of the line conductor 6b. Since the fluctuation of the impedance value of 6b can be reduced, it is possible to obtain good termination characteristics for the second line conductor 6b up to a high frequency band.

【００３５】さらに線路導体26bの高抵抗体部28が接続
される側の線路導体端に線路導体26bの特性インピーダ
ンスと整合のとれた減衰用抵抗体部29を設けている。Further, a damping resistor portion 29 matched with the characteristic impedance of the line conductor 26b is provided at the end of the line conductor on the side of the line conductor 26b to which the high resistance portion 28 is connected.

【００３６】また、高抵抗体部８を半導体素子５に接続
される側の第２の線路導体６ｂの端部より使用周波数の
高周波信号の波長の１／２未満の距離に配置しているこ
とにより、第２の線路導体６ｂの一端と高抵抗体部８と
の接続部との間に発生する高周波信号に対する共振現象
を使用周波数よりも高周波側へとシフトさせることがで
きるため、使用周波数において共振現象が発生すること
がなく、使用周波数の高周波信号に対して良好な伝送特
性を得ることが可能となる。Further, the high resistance portion 8 is arranged at a distance less than 1/2 of the wavelength of the high frequency signal of the used frequency from the end portion of the second line conductor 6b on the side connected to the semiconductor element 5. As a result, the resonance phenomenon with respect to the high frequency signal generated between the one end of the second line conductor 6b and the connection portion of the high resistance body portion 8 can be shifted to a higher frequency side than the used frequency, and therefore at the used frequency. A resonance phenomenon does not occur, and it becomes possible to obtain a good transmission characteristic for a high frequency signal of a used frequency.

【００３７】さらに、高抵抗体部８を第２の線路導体６
ｂを挟んでその両側に略線対称に２個以上形成して配置
することにより、高抵抗体部８は第２の線路導体６ｂに
対して並列に接続されることとなるため、高抵抗体部８
の１つ当たりに要求される抵抗値を所望の抵抗値よりも
大きく設定することができる。このため高抵抗体部８の
１つ当たりに要求される抵抗値のバラツキの許容範囲も
緩和でき、製造歩留まりを向上することができる。ま
た、高抵抗体部８の寄生インダクタンス成分も第２の線
路導体６ｂに対して並列に接続されることになるため、
寄生インダクタンス成分も低減することが可能となり、
第２の線路導体６ｂについてさらに高周波帯域まで使用
可能な終端特性を得ることが可能となる。Further, the high resistance portion 8 is connected to the second line conductor 6
By forming and arranging two or more parts on both sides of b in a substantially line-symmetrical manner, the high resistance part 8 is connected in parallel to the second line conductor 6b, so that the high resistance part Part 8
It is possible to set the resistance value required for each of the above to be larger than the desired resistance value. Therefore, the allowable range of variation in the resistance value required for each of the high-resistance body portions 8 can be relaxed, and the manufacturing yield can be improved. Further, since the parasitic inductance component of the high resistance part 8 is also connected in parallel to the second line conductor 6b,
It is also possible to reduce the parasitic inductance component,
With respect to the second line conductor 6b, it is possible to obtain a termination characteristic that can be used up to a higher frequency band.

【００３８】このような高抵抗体部８は、Ｔａ2Ｎ，Ｎ
ｉ−Ｃｒ合金等の材料から成り、回路基板６に印刷塗布
された後に焼成されて形成されるか、薄膜形成法により
形成される。また、高抵抗体部８による終端抵抗値は、
伝送される高周波信号の周波数や第２の線路導体６ｂの
特性インピーダンスに応じて、高抵抗体部８の厚みや
幅，形状を適宜設定することによって、所望の値に設定
される。また、抵抗値を微小調整するために、高抵抗体
部８の一部をレーザ加工によって除去し、精度よく抵抗
値を調整することもできる。The high resistance portion 8 is formed of Ta 2 N, N
It is made of a material such as an i-Cr alloy and is formed by being printed and applied on the circuit board 6 and then baked, or by a thin film forming method. The terminating resistance value of the high resistance part 8 is
It is set to a desired value by appropriately setting the thickness, width and shape of the high resistance portion 8 according to the frequency of the transmitted high frequency signal and the characteristic impedance of the second line conductor 6b. Further, in order to finely adjust the resistance value, a part of the high resistance part 8 can be removed by laser processing, and the resistance value can be adjusted accurately.

【００３９】さらにまた、線路導体６ｂの高抵抗体部８
が接続される他端の端面に線路導体６ｂの特性インピー
ダンスと整合のとれた減衰用抵抗体部29を設けることに
よって、高抵抗体部８と線路導体６ｂの間のインピーダ
ンスのミスマッチに起因して発生する反射ノイズをこの
減衰用抵抗体部29によって効果的に減衰させることでき
るため、より効果的にノイズを抑制することが可能とな
る。Furthermore, the high resistance portion 8 of the line conductor 6b
By providing the damping resistor portion 29 that is matched with the characteristic impedance of the line conductor 6b on the end face of the other end to which is connected, due to the impedance mismatch between the high resistance portion 8 and the line conductor 6b. Since the generated reflection noise can be effectively attenuated by the attenuation resistor portion 29, the noise can be more effectively suppressed.

【００４０】この減衰用抵抗体部９は、Ｔａ2Ｎ，Ｎｉ
−Ｃｒ合金等の抵抗材料から成り、回路基板６に印刷塗
布された後に焼成されるか、薄膜形成法により形成され
る。また、減衰用抵抗体部９の抵抗値は、第２の線路導
体６ｂにより伝送される高周波信号の周波数や第２の線
路導体６ｂの特性インピーダンスに応じて、減衰用抵抗
体部９の厚みや幅，形状を適宜設定することにより所望
の値に設定される。The damping resistor portion 9 is made of Ta 2 N, Ni.
It is made of a resistance material such as -Cr alloy and is formed by a thin film forming method by baking after being applied by printing on the circuit board 6. The resistance value of the damping resistor portion 9 depends on the frequency of the high frequency signal transmitted by the second line conductor 6b and the characteristic impedance of the second line conductor 6b. It is set to a desired value by appropriately setting the width and shape.

【００４１】そして、本発明の半導体素子収納用パッケ
ージの回路基板６上に半導体素子５を載置固定するとと
もにボンディングワイヤ７ａ，７ｂを介して第１の線路
導体６ａおよび第２の線路導体６ｂに電気的に接続し、
枠体２の上面にＦｅ−Ｎｉ−Ｃｏ合金等の金属から成る
蓋体４を半田付けやシームウエルド法等により接合する
ことによって、本発明の半導体装置となる。この本発明
の半導体装置によれば、容器内部に半導体素子５を気密
に収納して半導体素子５を長期にわたり正常かつ安定に
作動させることができ、基体１が外部電気回路基板に固
定実装され、グラスビーズ３と外部電気回路に接続され
た同軸ケーブルとを接続することにより、内部に収納し
た半導体素子５が外部電気回路に電気的に接続され、半
導体素子５が高周波信号で作動することとなる。Then, the semiconductor element 5 is mounted and fixed on the circuit board 6 of the package for accommodating the semiconductor element of the present invention, and is bonded to the first line conductor 6a and the second line conductor 6b through the bonding wires 7a and 7b. Electrically connected,
The semiconductor device of the present invention is obtained by joining the lid body 4 made of a metal such as Fe-Ni-Co alloy to the upper surface of the frame body 2 by soldering or the seam weld method. According to the semiconductor device of the present invention, the semiconductor element 5 can be hermetically housed in the container to operate the semiconductor element 5 normally and stably for a long period of time, and the base 1 is fixedly mounted on the external electric circuit board. By connecting the glass beads 3 and the coaxial cable connected to the external electric circuit, the semiconductor element 5 housed inside is electrically connected to the external electric circuit, and the semiconductor element 5 operates with a high frequency signal. .

【００４２】本発明の半導体素子収納用パッケージおよ
び半導体装置における高周波信号の好ましい周波数帯
は、マイクロ波やミリ波帯領域である。これは、高抵抗
体部８の寄生インダクタンス成分や寄生キャパシタンス
成分が周波数に依存してインピーダンス値が変動するた
め、線路導体６ｂのインピーダンスとのミスマッチによ
って発生する反射ノイズを、減衰用抵抗体部29によって
効果的に減衰させることができるためである。The preferable frequency band of the high frequency signal in the package for housing a semiconductor element and the semiconductor device of the present invention is in the microwave or millimeter wave band region. This is because the impedance value of the parasitic inductance component or parasitic capacitance component of the high resistance part 8 varies depending on the frequency. This is because it can be effectively attenuated by.

【００４３】また、回路基板６は、例えばＩＣ，ＬＳ
Ｉ，半導体レーザ（ＬＤ），フォトダイオード（ＰＤ）
等の半導体素子35が２つ以上の回路ブロックに分割され
ていてもよく、その場合は、一端が半導体素子に接続さ
れ、他端が高抵抗体部を介して接地導体層に電気的に接
続されている線路導体に対して、この線路導体を取り囲
む接地導体を形成するとともに、高抵抗体部を一端より
半導体素子の使用周波数の高周波信号の波長の１／２未
満の距離の線路導体の両側に略線対称に配設すればよ
い。The circuit board 6 is, for example, IC, LS.
I, semiconductor laser (LD), photodiode (PD)
May be divided into two or more circuit blocks, in which case one end is connected to the semiconductor element and the other end is electrically connected to the ground conductor layer via the high resistance part. A ground conductor that surrounds the line conductor is formed on the line conductor, and both sides of the line conductor at a distance less than 1/2 of the wavelength of the high frequency signal of the operating frequency of the semiconductor element from one end of the high resistance portion are formed. It may be arranged substantially symmetrically.

【００４４】なお、本発明は以上の実施の形態の例に限
定されるものではなく、本発明の要旨を逸脱しない範囲
内で種々の変更を行なっても何ら差し支えない。The present invention is not limited to the examples of the above embodiment, and various modifications may be made without departing from the gist of the present invention.

【００４５】[0045]

【発明の効果】本発明の半導体素子収納用パッケージに
よれば、回路基板の上面に線路導体およびこの線路導体
を取り囲む接地導体が形成されていることから、高抵抗
体部をこの接地導体に直接接続することによって、高抵
抗体部から接地導体までの寄生インダクタンス成分や寄
生キャパシタンス成分を低減することができる。このよ
うな寄生インダクタンス成分や寄生キャパシタンス成分
は周波数に依存してインピーダンス値を変動させるた
め、高抵抗体部から接地導体までの寄生インダクタンス
成分や寄生キャパシタンス成分を低減できることにより
線路導体の他端側に接続された高抵抗体部から見た線路
導体のインピーダンス値の変動を小さくすることがで
き、その結果、半導体素子の終端用電極に接続される線
路導体について高周波帯域までも安定した終端特性を得
ることが可能となる。According to the semiconductor element accommodating package of the present invention, since the line conductor and the ground conductor surrounding the line conductor are formed on the upper surface of the circuit board, the high resistance portion is directly connected to the ground conductor. By connecting, the parasitic inductance component and the parasitic capacitance component from the high resistance part to the ground conductor can be reduced. Since such a parasitic inductance component or parasitic capacitance component changes the impedance value depending on the frequency, it is possible to reduce the parasitic inductance component or parasitic capacitance component from the high resistance part to the ground conductor, and The fluctuation of the impedance value of the line conductor viewed from the connected high resistance part can be reduced, and as a result, the line conductor connected to the termination electrode of the semiconductor element can obtain stable termination characteristics even in a high frequency band. It becomes possible.

【００４６】さらに、線路導体の他端を接地導体に電気
的に接続する高抵抗体部を、線路導体を挟んでその両側
に略線対称に２個以上配設したことにより、高抵抗体部
の１つ当りに要求される抵抗値のバラツキの範囲を緩和
することができると同時に、高抵抗体部に発生する寄生
インダクタンス成分を低減することができるため、線路
導体について高周波帯域まで使用可能な終端抵抗を得る
ことが可能となる。Further, by arranging two or more high-resistor parts electrically connecting the other end of the line conductor to the ground conductor on both sides of the line conductor, the high-resistor parts are arranged in line symmetry. It is possible to reduce the range of variation in the resistance value required for each one, and at the same time, it is possible to reduce the parasitic inductance component generated in the high resistance part, so that the line conductor can be used up to a high frequency band. It is possible to obtain a terminating resistance.

【００４７】さらにまた、高抵抗体部を半導体素子に接
続される側の線路導体の一端より半導体素子の使用周波
数の高周波信号の波長の１／２未満の距離に配設するこ
とにより、線路導体の一端と高抵抗体部との接続部との
間に発生する高周波信号に対する共振現象を使用周波数
よりも高周波側へとシフトさせることができるため、使
用周波数において共振現象が発生することがなく、使用
周波数の高周波信号に対して良好な伝送特性を得ること
が可能となる。Furthermore, by arranging the high resistance portion at a distance less than 1/2 of the wavelength of the high frequency signal of the operating frequency of the semiconductor element from one end of the line conductor connected to the semiconductor element, Since it is possible to shift the resonance phenomenon for the high frequency signal generated between one end of the and the connection portion of the high resistance portion to a higher frequency side than the use frequency, the resonance phenomenon does not occur at the use frequency, It becomes possible to obtain good transmission characteristics for a high frequency signal of the used frequency.

【００４８】そして、線路導体の高抵抗体部が接続され
た他端の端面に線路導体の特性インピーダンスと整合の
とれた減衰用抵抗体部を設けたことにより、高抵抗体部
で終端しきれない場合の高周波信号をこの減衰用抵抗体
部でもって効果的に減衰させることができ、より効果的
にノイズを抑制することが可能となる。Further, by providing the damping resistor portion matching the characteristic impedance of the line conductor on the end face of the other end to which the high resistance portion of the line conductor is connected, the high resistance portion can be completely terminated. The high-frequency signal when there is no signal can be effectively attenuated by the attenuating resistor portion, and noise can be suppressed more effectively.

【００４９】従って、本発明の半導体素子収納用パッケ
ージは、以上のような構成により、線路導体を伝わる高
周波信号の反射によるノイズや共振が発生することを防
止し、半導体素子を正常に作動させることができる。Therefore, the package for accommodating a semiconductor element of the present invention has the above-mentioned structure to prevent noise and resonance due to the reflection of the high frequency signal transmitted through the line conductor and to operate the semiconductor element normally. You can

【００５０】また、本発明の半導体装置によれば、本発
明の半導体素子収納用パッケージと、その回路基板上に
載置された半導体素子と、枠体の上面に接合された蓋体
とを具備したことから、半導体素子の終端用電極に終端
用信号の高周波信号成分が反射して入り込んで半導体素
子が誤作動を起こすのを防ぐことができる、信頼性の高
い半導体装置を提供することができる。Further, according to the semiconductor device of the present invention, it is provided with the semiconductor element housing package of the present invention, the semiconductor element mounted on the circuit board thereof, and the lid body joined to the upper surface of the frame body. Therefore, it is possible to provide a highly reliable semiconductor device which can prevent the semiconductor element from malfunctioning due to the high frequency signal component of the termination signal being reflected and entering the termination electrode of the semiconductor element. .

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明の半導体素子収納用パッケージの実施の
形態の一例を示す断面図および上面図である。FIG. 1 is a cross-sectional view and a top view showing an example of an embodiment of a package for housing a semiconductor element of the present invention.

【図２】本発明の半導体素子収納用パッケージの回路基
板上に形成された高抵抗体部の例を示す要部拡大上面図
である。FIG. 2 is an enlarged top view of essential parts showing an example of a high resistance body portion formed on a circuit board of a package for housing a semiconductor element of the present invention.

【図３】従来の半導体素子収納用パッケージの例を示す
断面図および上面図である。FIG. 3 is a cross-sectional view and a top view showing an example of a conventional semiconductor element housing package.

【符号の説明】[Explanation of symbols]

１：基体 １ａ：載置部 ２：枠体 ２ａ：貫通孔 ３：グラスビーズ ３ａ：中心導体 ４：蓋体 ５：半導体素子 ６：回路基板 ６ａ：第１の線路導体 ６ｂ：第２の線路導体 ６ｃ，６ｅ：接地導体 ６ｄ：接地導体層 ７ａ，７ｂ：ボンディングワイヤ ８：高抵抗体部 ９：減衰用抵抗体部 1: Base 1a: Placement part 2: Frame body 2a: through hole 3: Glass beads 3a: central conductor 4: Lid 5: Semiconductor element 6: Circuit board 6a: First line conductor 6b: Second line conductor 6c, 6e: Ground conductor 6d: Ground conductor layer 7a, 7b: Bonding wire 8: High resistance part 9: Damping resistor part

Claims (2)

【特許請求の範囲】[Claims] 【請求項１】 上側主面に半導体素子および回路基板を
載置するための載置部を有する基体と、前記載置部に載
置された前記回路基板と、前記上側主面の外周部に前記
載置部を囲繞するように接合された枠体とを具備して成
り、前記回路基板の上面に線路導体および該線路導体を
取り囲む接地導体が形成されており、前記線路導体は一
端が前記半導体素子に、他端が高抵抗体部を介して前記
接地導体に電気的に接続されており、前記高抵抗体部は
前記一端より前記半導体素子の使用周波数の高周波信号
の波長の１／２未満の距離の前記線路導体の両側に略線
対称に配設されているとともに、前記線路導体の前記他
端の端面に前記線路導体の特性インピーダンスと整合の
とれた減衰用抵抗体部を設けたことを特徴とする半導体
素子収納用パッケージ。1. A substrate having a mounting portion for mounting a semiconductor element and a circuit board on an upper main surface, the circuit board mounted on the mounting portion, and an outer peripheral portion of the upper main surface. A frame body joined so as to surround the mounting portion, wherein a line conductor and a ground conductor surrounding the line conductor are formed on the upper surface of the circuit board, and one end of the line conductor is The other end of the semiconductor element is electrically connected to the ground conductor through a high resistance part, and the high resistance part is ½ of the wavelength of the high frequency signal of the operating frequency of the semiconductor element from the one end. Attenuating resistor portions, which are arranged substantially symmetrically on both sides of the line conductor at a distance of less than, and which are matched with the characteristic impedance of the line conductor, are provided on the end face of the other end of the line conductor. A package for storing a semiconductor element, characterized by J. 【請求項２】 請求項１記載の半導体素子収納用パッケ
ージと、前記回路基板上に載置された前記半導体素子
と、前記枠体の上面に接合された蓋体とを具備したこと
を特徴とする半導体装置。2. The semiconductor element storage package according to claim 1, the semiconductor element mounted on the circuit board, and a lid body joined to the upper surface of the frame body. Semiconductor device.
JP2002086697A 2002-03-26 2002-03-26 Semiconductor element storage package and semiconductor device Expired - Fee Related JP3702241B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2002086697A JP3702241B2 (en) 2002-03-26 2002-03-26 Semiconductor element storage package and semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002086697A JP3702241B2 (en) 2002-03-26 2002-03-26 Semiconductor element storage package and semiconductor device

Publications (2)

Publication Number Publication Date
JP2003282755A true JP2003282755A (en) 2003-10-03
JP3702241B2 JP3702241B2 (en) 2005-10-05

Family

ID=29233207

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
JP (1) JP3702241B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009096568A1 (en) * 2008-01-30 2009-08-06 Kyocera Corporation Wiring board for high frequency, package for containing electronic component, electronic device and communication apparatus
JP2016062744A (en) * 2014-09-18 2016-04-25 株式会社アドバンテスト Electronic device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009096568A1 (en) * 2008-01-30 2009-08-06 Kyocera Corporation Wiring board for high frequency, package for containing electronic component, electronic device and communication apparatus
JP5309039B2 (en) * 2008-01-30 2013-10-09 京セラ株式会社 High-frequency wiring board, electronic component storage package, electronic device and communication device
JP2016062744A (en) * 2014-09-18 2016-04-25 株式会社アドバンテスト Electronic device

Also Published As

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