JP2010056203A - Wiring substrate and package for storing semiconductor element, and semiconductor device - Google Patents

Wiring substrate and package for storing semiconductor element, and semiconductor device Download PDF

Info

Publication number
JP2010056203A
JP2010056203A JP2008217912A JP2008217912A JP2010056203A JP 2010056203 A JP2010056203 A JP 2010056203A JP 2008217912 A JP2008217912 A JP 2008217912A JP 2008217912 A JP2008217912 A JP 2008217912A JP 2010056203 A JP2010056203 A JP 2010056203A
Authority
JP
Japan
Prior art keywords
conductor
signal line
bias
resistor
semiconductor element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2008217912A
Other languages
Japanese (ja)
Inventor
Michinobu Iino
道信 飯野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP2008217912A priority Critical patent/JP2010056203A/en
Publication of JP2010056203A publication Critical patent/JP2010056203A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item

Landscapes

  • Non-Reversible Transmitting Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a wiring substrate which has excellent termination characteristics even in a high frequency band of ≥20 GHz and on which a mounted semiconductor element operates normally. <P>SOLUTION: The wiring substrate 7 includes a signal line conductor 2 disposed on one principal surface of a dielectric substrate 1, first grounding conductors 3 disposed on both sides thereof with interval, a second grounding conductor 3a disposed on the other principal surface and connected to the first grounding conductor 3 through a connection conductor 3b, a first resistor 4 connecting one end of the signal line conductor 2 to the first grounding conductor 3, a bias terminal electrode 5 disposed on the one principal surface while insulated from the first grounding conductor 3, and a bias conductor 6 disposed in the dielectric substrate 1, having one end connected to the one end of the signal line conductor 2 and the other end connected to the bias terminal electrode 5 through a through conductor 6c, and also having at least a portion between both ends composed of a second resistor 6a. Even if the signal line conductor 2 and bias conductor 6 are electromagnetically coupled, reflection on the signal line conductor 2 is small because of attenuation, so that the excellent termination characteristics are obtained. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

本発明は、終端抵抗により高周波信号を終端する機能を有する配線基板を用いた半導体素子収納用パッケージに関し、特に20ＧＨｚ以上の高周波帯域で使用される半導体素子収納用パッケージおよび半導体装置に関するものである。   The present invention relates to a package for housing a semiconductor element using a wiring board having a function of terminating a high frequency signal by a terminating resistor, and more particularly to a package for housing a semiconductor element and a semiconductor device used in a high frequency band of 20 GHz or more.

従来、高周波信号を用いる半導体素子を収納する半導体素子収納用パッケージには、高周波信号成分を含む終端用信号を電気エネルギーから熱エネルギーに変換し、終端用信号の反射によるノイズを抑制するために、終端抵抗を有する配線基板が搭載されたものがある。このような半導体素子収納用パッケージは、例えば、図８（ａ）に上面図で、図８（ｂ）に断面図で示すように、半導体素子111を搭載する搭載部108ａを有する金属製の基体108上に搭載部108ａを取り囲むような金属製の枠体109が接合されており、信号端子113がガラス等の封止材114により枠体109に設けられた固定孔109ａに固定されている。信号端子113は搭載部108ａに搭載された中継基板115に電気的に接続され、半導体素子111の搭載部108ａを間に設けて終端抵抗を有する配線基板107が搭載される。   Conventionally, in a package for housing a semiconductor element that contains a semiconductor element that uses a high-frequency signal, in order to convert a termination signal including a high-frequency signal component from electrical energy to thermal energy, and to suppress noise due to reflection of the termination signal, There is one on which a wiring board having a termination resistor is mounted. Such a package for housing a semiconductor element is, for example, a metal substrate having a mounting portion 108a on which a semiconductor element 111 is mounted, as shown in a top view in FIG. 8A and a cross-sectional view in FIG. A metal frame 109 surrounding the mounting portion 108a is joined on 108, and a signal terminal 113 is fixed to a fixing hole 109a provided in the frame 109 by a sealing material 114 such as glass. The signal terminal 113 is electrically connected to the relay substrate 115 mounted on the mounting portion 108a, and the wiring substrate 107 having a terminating resistor is mounted with the mounting portion 108a of the semiconductor element 111 interposed therebetween.

そして、半導体素子111を搭載部108ａに搭載して、中継基板115と半導体素子111とをボンディングワイヤ116等により電気的に接続し、半導体素子111と配線基板107の信号線路導体102とを同様にボンディングワイヤ116により電気的に接続し、枠体109の上面に蓋体112を接合して封止することにより半導体装置となる。このときの配線基板107は、例えば、図９（ａ）に上面図で、図９（ｂ）に図９（ａ）のＡ−Ａ線における断面図で、また図９（ｃ）に下面図で示すように、誘電体基板101の上面に信号線路導体102とこれを取り囲むように同一面接地導体103が形成され、信号線路導体102の先端と同一面接地導体103との間に高抵抗部、すなわち終端抵抗104が設けられている。配線基板107の下面には接地導体103ａが形成されており、同一面接地導体103と接地導体103ａとは誘電体基板101の側面に形成された接続導体103ｂにより接続されている（例えば、特許文献１を参照。）。   Then, the semiconductor element 111 is mounted on the mounting portion 108a, the relay substrate 115 and the semiconductor element 111 are electrically connected by a bonding wire 116 or the like, and the semiconductor element 111 and the signal line conductor 102 of the wiring board 107 are similarly connected. A semiconductor device is obtained by electrically connecting with bonding wires 116 and bonding and sealing lid 112 to the upper surface of frame 109. The wiring board 107 at this time is, for example, a top view in FIG. 9A, a cross-sectional view taken along line AA in FIG. 9A, and a bottom view in FIG. 9C. As shown, the signal line conductor 102 is formed on the upper surface of the dielectric substrate 101 so as to surround the signal line conductor 102, and the high resistance portion is formed between the tip of the signal line conductor 102 and the same plane ground conductor 103. That is, a termination resistor 104 is provided. A ground conductor 103a is formed on the lower surface of the wiring board 107, and the same-surface ground conductor 103 and the ground conductor 103a are connected by a connection conductor 103b formed on the side surface of the dielectric substrate 101 (for example, Patent Literature 1). 1).

近年、このような半導体装置の配線基板にバイアス端子電極を設けて半導体素子に配線基板の信号線路導体を介してバイアス電圧を供給することにより、半導体素子にバイアス専用の端子や導体を設けないことで半導体素子を小型化したり、バイアス供給用の回路基板を搭載しないことで半導体装置を小型化したりすることが行なわれるようになっている。配線基板に形成されるバイアス端子電極は、バイアス端子に接続して外部からバイアス電圧の供給を受けるのが容易となるように、信号線路導体および同一面接地導体が形成された上面に形成される。
特開2002−319645号公報 In recent years, a bias terminal electrode is provided on a wiring board of such a semiconductor device, and a bias voltage is supplied to the semiconductor element via a signal line conductor of the wiring board, whereby a dedicated terminal or conductor for bias is not provided on the semiconductor element. Thus, it is possible to reduce the size of a semiconductor device or to reduce the size of a semiconductor device by not mounting a circuit board for supplying bias. The bias terminal electrode formed on the wiring board is formed on the upper surface on which the signal line conductor and the same-surface ground conductor are formed so that it is easy to connect to the bias terminal and receive a bias voltage from the outside. .
JP 2002-319645

しかしながら、信号線路導体102とバイアス端子電極とを接続するバイアス導体をそれらと同じ誘電体基板101の上面に形成すると、同一面接地導体103をバイアス導体が分断することとなり、信号線路導体102のインピーダンス整合が乱れて特性が劣化してしまうこととなる。そのため、誘電体基板101の下面に接地導体103ａがある従来の配線基板では、誘電体基板101を多層化して誘電体基板101の内部にバイアス導体を設けることとなる。   However, if the bias conductor connecting the signal line conductor 102 and the bias terminal electrode is formed on the upper surface of the same dielectric substrate 101, the bias conductor divides the coplanar ground conductor 103, and the impedance of the signal line conductor 102 is reduced. The alignment is disturbed and the characteristics are deteriorated. Therefore, in the conventional wiring board having the ground conductor 103a on the lower surface of the dielectric substrate 101, the dielectric substrate 101 is multilayered and the bias conductor is provided inside the dielectric substrate 101.

誘電体基板101の内部にバイアス導体を設けると、バイアス導体が信号線路導体102と上面視して重なる部分や、重ならなくても距離が近い部分においては、信号線路導体102とバイアス導体とが電磁結合してしまい、信号線路導体102に不要な反射等が発生して信号線路導体102のインピーダンスが変化することにより伝送特性が低下し、配線基板107の終端特性が不十分となり、半導体素子111を正常に動作させることができなくなるという問題点があった。   When the bias conductor is provided inside the dielectric substrate 101, the signal line conductor 102 and the bias conductor are not connected to each other in a portion where the bias conductor overlaps with the signal line conductor 102 in a top view or a portion where the distance does not overlap. Due to electromagnetic coupling, unnecessary reflection or the like is generated in the signal line conductor 102 and the impedance of the signal line conductor 102 is changed, so that the transmission characteristic is deteriorated, and the termination characteristic of the wiring board 107 becomes insufficient, and the semiconductor element 111 There was a problem that it became impossible to operate normally.

本発明は上記問題点に鑑み完成されたものであり、その目的は、20ＧＨｚ以上の高周波帯においても良好な終端特性を有し、半導体素子を正常に動作させることができる配線基板、およびそれを用いた高周波用半導体素子収納用パッケージならびに半導体装置を提供することにある。   The present invention has been completed in view of the above problems, and its object is to provide a wiring board that has good termination characteristics even in a high frequency band of 20 GHz or more and can operate a semiconductor element normally. It is an object of the present invention to provide a high-frequency semiconductor element storage package and a semiconductor device that are used.

本発明の配線基板は、誘電体基板と、該誘電体基板の一方主面上に配置された信号線路導体と、該信号線路導体の両側に間隔を設けて配置された第１の接地導体と、前記誘電体基板の他方主面に配置され、前記第１の接地導体と接続導体を介して接続されている第２の接地導体と、前記信号線路導体の一端と前記第１の接地導体とを接続する第１の抵抗体と、前記誘電体基板の一方主面上に前記第１の接地導体と絶縁されて配置されたバイアス端子電極と、前記誘電体基板の内部に配置された、一端が前記信号線路導体の前記一端に、および他端が前記バイアス端子電極にそれぞれ貫通導体を介して接続されており、両端間の少なくとも一部が第２の抵抗体からなるバイアス導体とを具備することを特徴とするものである。   The wiring board according to the present invention includes a dielectric substrate, a signal line conductor disposed on one main surface of the dielectric substrate, and a first ground conductor disposed on both sides of the signal line conductor with a space therebetween. A second ground conductor disposed on the other main surface of the dielectric substrate and connected to the first ground conductor via a connection conductor; one end of the signal line conductor; and the first ground conductor; A bias terminal electrode disposed on one main surface of the dielectric substrate so as to be insulated from the first ground conductor, and one end disposed inside the dielectric substrate. Are connected to the one end of the signal line conductor and the other end to the bias terminal electrode via a through conductor, respectively, and at least a part between both ends includes a bias conductor made of a second resistor. It is characterized by this.

また、本発明の配線基板は、上記構成において、前記バイアス導体の前記第２の抵抗体以外の導体部の長さが、前記信号線路導体により伝送する信号の波長の１／４未満であることを特徴とするものである。   In the wiring board according to the present invention, in the above configuration, the length of the conductor portion other than the second resistor of the bias conductor is less than ¼ of the wavelength of the signal transmitted by the signal line conductor. It is characterized by.

本発明の半導体素子収納用パッケージは、金属から成り上面に前記配線基板および半導体素子を搭載する搭載部を有する基体と、該基体の上面に接合された前記搭載部を取り囲む枠体と、前記搭載部に搭載された上記構成のいずれかの本発明の配線基板と、該配線基板の前記バイアス端子電極に電気的に接続されたバイアス端子とを具備することを特徴とするものである。   A package for housing a semiconductor element according to the present invention includes a base made of metal and having a mounting portion for mounting the wiring board and the semiconductor element on an upper surface, a frame surrounding the mounting portion bonded to the upper surface of the base, and the mounting And a bias terminal electrically connected to the bias terminal electrode of the wiring board.

本発明の半導体装置は、上記構成の本発明の半導体素子収納用パッケージと、前記搭載部に搭載されて前記信号線路導体および前記第１の接地導体に電気的に接続された半導体素子と、前記枠体の上面に接合された蓋体とを具備することを特徴とするものである。   The semiconductor device of the present invention includes a semiconductor element storage package of the present invention configured as described above, a semiconductor element mounted on the mounting portion and electrically connected to the signal line conductor and the first ground conductor, And a lid joined to the upper surface of the frame.

本発明の配線基板によれば、誘電体基板の内部に配置された、一端が信号線路導体の一端に、および他端がバイアス端子電極にそれぞれ貫通導体を介して接続されており、両端間の少なくとも一部が第２の抵抗体からなるバイアス導体とを具備することから、電磁結合によりバイアス導体に共振が発生したとしても、バイアス導体の一部が第２の抵抗体でできているため共振が熱エネルギーに変わって減衰するので、信号線路導体に反射して返ることを減少させることができる。それによって、20ＧＨｚ以上の高周波信号においても伝達特性が向上し良好な終端特性を得ることができる配線基板となる。   According to the wiring board of the present invention, one end disposed inside the dielectric substrate is connected to one end of the signal line conductor, and the other end is connected to the bias terminal electrode through the through conductor, respectively. Since at least a part of the bias conductor includes the second resistor, even if resonance occurs in the bias conductor due to electromagnetic coupling, resonance occurs because part of the bias conductor is made of the second resistor. Is attenuated by changing to thermal energy, so that it is possible to reduce the reflection back to the signal line conductor. As a result, the transmission characteristic is improved even for a high-frequency signal of 20 GHz or higher, and the wiring board can be obtained with good termination characteristics.

また、本発明の配線基板によれば、上記構成において、バイアス導体の第２の抵抗体以外の導体部の長さが、信号線路導体により伝送する信号の波長の１／４未満であるときには、バイアス導体の第２の抵抗体以外の導体部が信号線路導体と容量結合したとしてもバイアス導体が共振することなく減衰するため、信号線路導体に反射して返ってくることがない。それによって、より良好な終端特性を得ることができるようになる。   According to the wiring board of the present invention, in the above configuration, when the length of the conductor portion other than the second resistor of the bias conductor is less than ¼ of the wavelength of the signal transmitted by the signal line conductor, Even if a conductor portion other than the second resistor of the bias conductor is capacitively coupled to the signal line conductor, the bias conductor is attenuated without resonating, so that it is not reflected back to the signal line conductor. As a result, better termination characteristics can be obtained.

本発明の半導体素子収納用パッケージによれば、金属から成り上面に配線基板および半導体素子を搭載する搭載部を有する基体と、基体の上面に接合された搭載部を取り囲む枠体と、前記搭載部に搭載された配線基板と、配線基板のバイアス端子電極に電気的に接続されたバイアス端子とを具備することから、バイアス導体と信号線路導体とが電磁結合したとしても抵抗により熱エネルギーに変換されて電磁結合が小さくなるので、信号線路導体に不要な反射が発生してインピーダンスが変化することが抑えられ、20ＧＨｚ以上の高周波信号においても伝達特性が向上し良好な終端特性を得ることができ、搭載する半導体素子を高周波でも正常に動作させることができるようになる。   According to the package for housing a semiconductor element of the present invention, a base body made of metal and having a mounting portion for mounting the wiring substrate and the semiconductor element on the upper surface, a frame surrounding the mounting portion joined to the upper surface of the base body, and the mounting portion And the bias terminal electrically connected to the bias terminal electrode of the wiring board, even if the bias conductor and the signal line conductor are electromagnetically coupled, they are converted into thermal energy by resistance. Because electromagnetic coupling is reduced, unnecessary reflections are prevented from occurring in the signal line conductor and the impedance is suppressed, and transmission characteristics are improved even in high frequency signals of 20 GHz or higher, and good termination characteristics can be obtained. The mounted semiconductor element can be normally operated even at a high frequency.

本発明の半導体装置によれば、上記構成の本発明の半導体素子収納用パッケージと、搭載部に搭載されて信号線路導体および第１の接地導体に電気的に接続された半導体素子と、枠体の上面に接合された蓋体とを具備することから、本発明の配線基板により良好な終端特性が得られるので高周波においても半導体素子が安定に動作する半導体装置となる。   According to the semiconductor device of the present invention, the semiconductor element storage package of the present invention having the above configuration, the semiconductor element mounted on the mounting portion and electrically connected to the signal line conductor and the first ground conductor, and the frame Since the circuit board of the present invention provides good termination characteristics, the semiconductor device can operate stably even at high frequencies.

本発明の配線基板および半導体素子収納用パッケージならびに半導体装置について添付の図面を参照しつつ詳細に説明する。   A wiring board, a semiconductor element storage package, and a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

図１（ａ）は本発明の配線基板の実施の形態の一例を示す上面図であり、図１（ｂ）は図１（ａ）のＡ−Ａ線における断面図であり、図１（ｃ）は図１（ｂ）のＡ−Ａ線における断面図であり、図１（ｄ）は下面図である。図２（ａ）は本発明の配線基板の実施の形態の他の一例を示す上面図であり、図２（ｂ）は図２（ａ）のＡ−Ａ線における断面図であり、図２（ｃ）は図２（ｂ）のＡ−Ａ線における断面図であり、図２（ｄ）は下面図である。図３（ａ）は本発明の配線基板の実施の形態の他の例を示す上面図であり、図３（ｂ）は断面図である。図４および図５は、図３と同様に、それぞれ（ａ）は本発明の半導体装置の実施の形態の一例を示す上面図であり、（ｂ）は断面図である。図６は本発明の配線基板の等価回路図である。図１〜図５において、１は誘電体基板、１ａは第１の誘電体層、１ｂは第２の誘電体層、２は信号線路導体、３は第１の接地導体、３ａは第２の接地導体、３ｂは接続導体、４は第１の抵抗体、５はバイアス端子電極、６はバイアス導体、６ａは第２の抵抗体、６ｂは導体部、６ｃは貫通導体、７は配線基板である。   FIG. 1A is a top view showing an example of an embodiment of a wiring board according to the present invention, and FIG. 1B is a cross-sectional view taken along the line AA in FIG. ) Is a cross-sectional view taken along line AA in FIG. 1B, and FIG. 1D is a bottom view. 2A is a top view showing another example of the embodiment of the wiring board of the present invention, and FIG. 2B is a cross-sectional view taken along the line AA in FIG. 2A. (C) is sectional drawing in the AA of FIG.2 (b), FIG.2 (d) is a bottom view. FIG. 3A is a top view showing another example of the embodiment of the wiring board of the present invention, and FIG. 3B is a cross-sectional view. 4 and 5 are respectively a top view and a cross-sectional view, respectively, showing an example of the embodiment of the semiconductor device of the present invention, as in FIG. FIG. 6 is an equivalent circuit diagram of the wiring board of the present invention. 1 to 5, 1 is a dielectric substrate, 1a is a first dielectric layer, 1b is a second dielectric layer, 2 is a signal line conductor, 3 is a first ground conductor, and 3a is a second dielectric layer. Ground conductor, 3b is a connection conductor, 4 is a first resistor, 5 is a bias terminal electrode, 6 is a bias conductor, 6a is a second resistor, 6b is a conductor portion, 6c is a through conductor, and 7 is a wiring board. is there.

本発明の配線基板７は、図１〜図５に示す例のように、誘電体基板１と、誘電体基板１の一方主面上に配置された信号線路導体２と、信号線路導体２の両側に間隔を設けて配置された第１の接地導体３と、誘電体基板１の他方主面に配置され、第１の接地導体３と接続導体３ｂを介して接続されている第２の接地導体３ａと、信号線路導体２の一端と第１の接地導体３とを接続する第１の抵抗体４と、誘電体基板１の一方主面上に第１の接地導体３と絶縁されて配置されたバイアス端子電極５と、誘電体基板１の内部に配置された、一端が信号線路導体２の一端に、および他端がバイアス端子電極５にそれぞれ貫通導体６ｃを介して接続されており、両端間の少なくとも一部が第２の抵抗体６ａからなるバイアス導体６とを具備する。本発明の配線基板７によれば、このような構成としたことから、電磁結合によりバイアス導体６に共振が発生したとしても、バイアス導体６の一部が第２の抵抗体６ａでできているため共振が熱エネルギーに変わって減衰するので、信号線路導体２に反射して返ることを減少させることができる。それによって、20ＧＨｚ以上の高周波信号においても伝達特性が向上し良好な終端特性を得ることができる配線基板７となる。   The wiring board 7 of the present invention includes a dielectric substrate 1, a signal line conductor 2 disposed on one main surface of the dielectric substrate 1, and a signal line conductor 2, as in the examples shown in FIGS. A first grounding conductor 3 arranged on both sides with a gap between them and a second grounding arranged on the other main surface of the dielectric substrate 1 and connected via the first grounding conductor 3 and the connecting conductor 3b. A conductor 3a, a first resistor 4 that connects one end of the signal line conductor 2 and the first ground conductor 3, and a first ground conductor 3 disposed on one main surface of the dielectric substrate 1 are insulated. One end of the bias terminal electrode 5 disposed inside the dielectric substrate 1 is connected to one end of the signal line conductor 2 and the other end is connected to the bias terminal electrode 5 via the through conductor 6c. At least a part between both ends includes a bias conductor 6 made of a second resistor 6a. According to the wiring board 7 of the present invention, because of such a configuration, even if resonance occurs in the bias conductor 6 due to electromagnetic coupling, a part of the bias conductor 6 is made of the second resistor 6a. Therefore, the resonance is attenuated by changing to thermal energy, so that the reflection back to the signal line conductor 2 can be reduced. As a result, the transmission characteristics are improved even for high-frequency signals of 20 GHz or higher, and the wiring board 7 can obtain good termination characteristics.

本発明の配線基板７を回路図で示すと図５のようになり、信号線路導体２はその端部で終端抵抗である第１の抵抗体４を介して第１の接地導体３に接続されている。また、バイアス端子電極５とはバイアス導体６を介して接続されており、バイアス導体６は第２の抵抗体６ａとなっている。   The circuit board 7 of the present invention is shown in a circuit diagram as shown in FIG. 5, and the signal line conductor 2 is connected to the first ground conductor 3 via the first resistor 4 which is a terminating resistor at the end thereof. ing. The bias terminal electrode 5 is connected via a bias conductor 6, and the bias conductor 6 is a second resistor 6a.

また、本発明の配線基板７は、上記構成において、バイアス導体６の第２の抵抗体６ａ以外の導体部６ｂの長さ（図１にＬで示す。）が、信号線路導体２により伝送する信号の波長の１／４未満であるときには、バイアス導体６の第２の抵抗体６ａ以外の導体部６ｂが信号線路導体２と容量結合したとしても共振することなく減衰するため、信号線路導体２に反射して返ってくることがない。それによって、より良好な終端特性を得ることができるようになる。   Further, in the wiring board 7 of the present invention, the length of the conductor portion 6b (indicated by L in FIG. 1) other than the second resistor 6a of the bias conductor 6 is transmitted by the signal line conductor 2 in the above configuration. When the signal wavelength is less than ¼, even if the conductor portion 6b other than the second resistor 6a of the bias conductor 6 is capacitively coupled to the signal line conductor 2, the signal line conductor 2 is attenuated without resonating. It will not be reflected back. As a result, better termination characteristics can be obtained.

配線基板７は、誘電体基板１の一方主面上に信号線路導体２，第１の接地導体３，第１の抵抗体４，バイアス端子電極５が形成され、他方主面上に第２の接地導体３ａが形成され、内部にバイアス導体６が形成されたものである。   The wiring board 7 has a signal line conductor 2, a first ground conductor 3, a first resistor 4, and a bias terminal electrode 5 formed on one main surface of the dielectric substrate 1, and a second main surface on the other main surface. A ground conductor 3a is formed, and a bias conductor 6 is formed inside.

図１〜図５では配線基板７の信号線路導体２が平行に２本配置された例を示しているが、信号線路導体２の数は、使用される素子やモジュールに合わせることによって決まるものであるので、信号線路導体２の数が１本である場合や、２本より多い場合もある。   1 to 5 show an example in which two signal line conductors 2 of the wiring board 7 are arranged in parallel, but the number of signal line conductors 2 is determined according to the elements and modules used. Therefore, the number of signal line conductors 2 may be one or more than two.

第１の接地導体３と第２の接地導体３ａとを接続する接続導体３ｂは、図１に示す例のように、誘電体基板１の側面に形成された側面導体であってもよいし、図２〜図５に示す例のように誘電体基板１を貫通する貫通導体であってもよい。接続導体３ｂを貫通導体とし、図２〜図５に示す例のように、信号線路導体２を挟むように配置すると、擬似同軸構造となり高周波の信号をより良好に伝送することができるので好ましい。そして、このときの信号線路導体２を挟んだ接続導体３ｂの間隔（図２に示すＷ１）を信号線路導体２が伝送する信号の波長の１／２未満とし、また、信号線路導体２に沿って配置された接続導体３ｂの間隔（図２に示すＷ２）を伝送する信号の波長の１／４未満にすると、グラウンド付きコプレーナ線路のグラウンドがより強化されることで高次モードの共振を抑えることができ、特性をさらに優れたものとすることができるので好ましい。例えば、40ＧＨｚの信号を実効誘電率9.5の誘電体基板１上の信号線路導体２で伝送するのであれば、接続導体３ｂの間隔Ｗ１を約1.2ｍｍ以下、Ｗ２を約0.6ｍｍ以下とすればよい。   The connection conductor 3b connecting the first ground conductor 3 and the second ground conductor 3a may be a side conductor formed on the side surface of the dielectric substrate 1, as in the example shown in FIG. A through conductor penetrating through the dielectric substrate 1 may be used as in the examples shown in FIGS. It is preferable to use the connecting conductor 3b as a through conductor and arrange the signal line conductor 2 so as to sandwich the signal line conductor 2 as in the examples shown in FIGS. 2 to 5 because a high-frequency signal can be transmitted better. At this time, the distance (W1 shown in FIG. 2) between the connection conductors 3b sandwiching the signal line conductor 2 is set to be less than ½ of the wavelength of the signal transmitted by the signal line conductor 2, and along the signal line conductor 2 When the distance between the connection conductors 3b arranged in the same manner (W2 shown in FIG. 2) is less than ¼ of the wavelength of the signal to be transmitted, the ground of the grounded coplanar line is further strengthened to suppress higher-order mode resonance. This is preferable because the characteristics can be further improved. For example, if a 40 GHz signal is transmitted through the signal line conductor 2 on the dielectric substrate 1 having an effective dielectric constant of 9.5, the interval W1 between the connection conductors 3b may be about 1.2 mm or less and W2 may be about 0.6 mm or less. .

図１（ａ）および図２（ａ）に示す例では、配線基板７を上面から透視すると、バイアス導体６と信号線路導体２とが平行に重なっている。信号線路導体２とバイアス導体６との電磁結合をより小さくするためには、図３（ａ）に示す例のようにバイアス導体６の形状を変えて信号線路導体２からずらし、信号線路導体２との重なりを小さくするのが好ましい。また、図４（ａ）に示す例では、信号線路導体２を端部付近で屈曲させることで、信号線路導体２とバイアス導体６との重なりを小さくして電磁結合がより小さくなるようにしている。さらに、配線基板７の大きさ等による制限はあるが、図５（ａ）に示す例のように、信号線路導体２とバイアス導体６とが各々の接続部以外では重ならないようにすると電磁結合が最も小さくなるので最も好ましい。   In the example shown in FIGS. 1A and 2A, when the wiring board 7 is seen through from above, the bias conductor 6 and the signal line conductor 2 are overlapped in parallel. In order to make the electromagnetic coupling between the signal line conductor 2 and the bias conductor 6 smaller, the shape of the bias conductor 6 is changed and shifted from the signal line conductor 2 as in the example shown in FIG. Is preferably reduced. Further, in the example shown in FIG. 4A, the signal line conductor 2 is bent near the end so that the overlap between the signal line conductor 2 and the bias conductor 6 is reduced so that the electromagnetic coupling is further reduced. Yes. Further, although there is a limitation due to the size of the wiring board 7 and the like, if the signal line conductor 2 and the bias conductor 6 do not overlap except at their connecting portions as in the example shown in FIG. Is most preferable because it is the smallest.

なお、バイアス導体６は両端間の少なくとも一部が第２の抵抗体６ａからなるものであれば上記のような効果が得られるが、バイアス導体６の全てを第２の抵抗体６ａで形成しても構わない。また、貫通導体６ｃも第２の抵抗体６ａで形成してもよい。   The above effect can be obtained if the bias conductor 6 is formed of the second resistor 6a at least partly between both ends. However, the bias conductor 6 is entirely formed of the second resistor 6a. It doesn't matter. The through conductor 6c may also be formed of the second resistor 6a.

また、図１〜図５においては、バイアス導体６の導体部６ｂは、バイアス導体６の両端部であるバイアス導体６と貫通導体６ｃとの接続部に配置しているが、それ以外の部分に配置しても構わない。特に配線基板７を上面から透視して信号線路導体２と重なる位置または信号線路導体２と近い位置に導体部６ｂを配置する場合は、導体部６ｂの長さを信号線路導体２により伝送する信号の波長の１／４未満とするのが好ましい。   1 to 5, the conductor portion 6b of the bias conductor 6 is disposed at the connection portion between the bias conductor 6 and the through conductor 6c, which are both ends of the bias conductor 6, but in other portions. You may arrange. In particular, when the conductor portion 6b is disposed at a position overlapping the signal line conductor 2 or a position close to the signal line conductor 2 when the wiring board 7 is seen through from above, a signal transmitted by the signal line conductor 2 is the length of the conductor portion 6b. It is preferable to be less than ¼ of the wavelength.

誘電体基板１は、酸化アルミニウム（アルミナ：Ａｌ２Ｏ３）質焼結体，窒化アルミニウム（ＡｌＮ）質焼結体，ガラスセラミックス等のセラミックスから成る、第１の誘電体層１ａと第２の誘電体層１ｂとが積層されたもの、あるいはセラミックスから成る第１の誘電体層１ａと、ポリイミド樹脂，ポリフェニレンサルファイド樹脂，全芳香族ポリエステル樹脂，ＢＣＢ（ベンゾシクロブテン）樹脂，エポキシ樹脂，ビスマレイミドトリアジン樹脂，ポリフェニレンエーテル樹脂，ポリキノリン樹脂，フッ素樹脂等の絶縁性の樹脂から成る第２の誘電体層１ｂとが積層されたものである。第１の誘電体層１ａと第２の誘電体層１ｂとの間にバイアス導体６が形成される。第１の誘電体層１ａおよび第２の誘電体層１ｂは、１層の誘電体層から成るものであってもよいし複数の誘電体層から成るものであってもよい。誘電体基板１がセラミックスから成る第１の誘電体層１ａと第２の誘電体層１ｂとが積層されたものである場合は、第１の誘電体層１ａと第２の誘電体層１ｂとが同時焼成により一体的に作製されたものであってもよいし、別々に作製した第１の誘電体層１ａと第２の誘電体層１ｂとを接合したものであってもよい。 The dielectric substrate 1 includes a first dielectric layer 1a and a second dielectric layer made of ceramics such as an aluminum oxide (alumina: Al 2 O 3 ) sintered body, an aluminum nitride (AlN) sintered body, and glass ceramics. 1st dielectric layer 1a made of a laminate of dielectric layer 1b or ceramics, polyimide resin, polyphenylene sulfide resin, wholly aromatic polyester resin, BCB (benzocyclobutene) resin, epoxy resin, bismaleimide A second dielectric layer 1b made of an insulating resin such as triazine resin, polyphenylene ether resin, polyquinoline resin, or fluorine resin is laminated. A bias conductor 6 is formed between the first dielectric layer 1a and the second dielectric layer 1b. The first dielectric layer 1a and the second dielectric layer 1b may be composed of a single dielectric layer or a plurality of dielectric layers. When the dielectric substrate 1 is formed by laminating a first dielectric layer 1a and a second dielectric layer 1b made of ceramics, the first dielectric layer 1a and the second dielectric layer 1b May be produced integrally by co-firing, or may be obtained by joining separately produced first dielectric layer 1a and second dielectric layer 1b.

誘電体基板１の第１の誘電体層１ａおよび第２の誘電体層１ｂは、例えば、アルミナ（Ａｌ２Ｏ３）質セラミックスから成る場合、以下のようにして作製される。まず、Ａｌ２Ｏ３，酸化珪素（ＳｉＯ２），酸化カルシウム（ＣａＯ），酸化マグネシウム（ＭｇＯ）等の原料粉末に適当な有機バインダや可塑剤，分散剤，溶剤等を添加混合して泥漿状となす。これを従来周知のドクターブレード法等でシート状となすことによってセラミックグリーンシートを得る。しかる後、このセラミックグリーンシートに適当な打ち抜き加工を施すことによって所定の形状に成形するとともに必要に応じて複数枚積層して生成形体を作製し、これを還元雰囲気中で約1600℃の温度で焼成することにより製作される。なお、生成形体は、Ａｌ２Ｏ３，ＳｉＯ２，ＣａＯ，ＭｇＯ等の原料粉末（必要に応じて有機バインダを加えて顆粒状とする。）を金型に充填しプレス成型することによって所定の形状のものを作製してもよい。 When the first dielectric layer 1a and the second dielectric layer 1b of the dielectric substrate 1 are made of, for example, an alumina (Al 2 O 3 ) ceramic, they are produced as follows. First, a suitable organic binder, plasticizer, dispersant, solvent, etc. are added to and mixed with raw material powders such as Al 2 O 3 , silicon oxide (SiO 2 ), calcium oxide (CaO), magnesium oxide (MgO), etc. And A ceramic green sheet is obtained by making this into a sheet by a conventionally known doctor blade method or the like. Thereafter, the ceramic green sheet is formed into a predetermined shape by performing an appropriate punching process, and a plurality of pieces are laminated as necessary to produce a formed shape, and this is formed in a reducing atmosphere at a temperature of about 1600 ° C. Manufactured by firing. Note that green product is, Al 2 O 3, SiO 2 , CaO, such as MgO raw material powder (added an organic binder if necessary and granulated with.) The predetermined by press molding was filled in a mold You may produce the shape.

配線基板７の誘電体基板１がセラミックスから成り、第１の誘電体層１ａと第２の誘電体層１ｂとが同時焼成により一体的に作製される場合は、第１の誘電体層１ａとなるセラミックグリーンシートの上面に、信号線路導体２，接地導体３，第１の抵抗体４，バイアス端子電極５，また下面にバイアス導体６の導体部６ｂ用の金属ペーストを、また、第２の誘電体層１ｂとなるセラミックグリーンシートの下面に第２の接地導体３用の金属ペーストをスクリーン印刷法等の塗布手段により印刷塗布し、バイアス導体６の抵抗体部６ａ用の抵抗体ペーストを第１の誘電体層１ａとなるセラミックグリーンシートの下面に印刷塗布し、第１の誘電体層１ａとなるセラミックグリーンシートと第２の誘電体層１ｂとなるセラミックグリーンシートとを積層して生成形体を作製しておけばよい。バイアス導体６の導体部６ｂ用の金属ペーストおよびバイアス導体６の抵抗体部６ａ用の抵抗体ペーストは、第２の誘電体層１ｂとなるセラミックグリーンシートの上面に印刷塗布してもよい。貫通導体６ｃは、第１の誘電体層１ａとなるセラミックグリーンシートに貫通孔を形成して貫通孔に金属ペーストを充填しておくことにより形成することができる。接続導体３ｂが貫通導体である場合も同様に、第１の誘電体層１ａとなるセラミックグリーンシートおよび第２の誘電体層１ｂとなるセラミックグリーンシートに貫通孔を形成して金属ペーストを充填しておけばよい。接続導体３ｂが側面導体である場合は、生成形体作製した後にその側面に金属ペーストを印刷塗布すればよい。金属ペーストは、金属粉末に適当な有機バインダや溶剤を添加混合して作製する。金属粉末は、例えば、第１の誘電体層１ａおよび第２の誘電体層１ｂがアルミナ質セラミックスから成る場合であれば、タングステン（Ｗ），モリブデン（Ｍｏ），マンガン（Ｍｎ）等が用いられ、第１の誘電体層１ａおよび第２の誘電体層１ｂがガラスセラミックスから成る場合であれば、銅（Ｃｕ），銀（Ａｇ），パラジウム（Ｐｄ），Ａｇ−Ｐｄ合金等が用いられる。誘電体基板１の外表面の信号線路導体２，第１の接地導体３，第２の接地導体３ａ，第１の抵抗体４，バイアス端子電極５，側面導体（接続導体３ｂ）は、セラミックグリーンシートと同時焼成による形成ではなく、内部のバイアス導体６や貫通導体６ｃおよび接続導体３ｂである貫通導体が形成された誘電体基板１を作製した後に、蒸着法等の薄膜形成法にて形成してもよい。特に第１の抵抗体４は、終端抵抗値を精度よく形成することができるので、薄膜形成法にて形成するのが好ましい。   When the dielectric substrate 1 of the wiring substrate 7 is made of ceramics, and the first dielectric layer 1a and the second dielectric layer 1b are integrally manufactured by simultaneous firing, the first dielectric layer 1a On the upper surface of the ceramic green sheet, the signal line conductor 2, the ground conductor 3, the first resistor 4, the bias terminal electrode 5, the metal paste for the conductor portion 6b of the bias conductor 6 on the lower surface, and the second A metal paste for the second ground conductor 3 is printed and applied to the lower surface of the ceramic green sheet to be the dielectric layer 1b by a coating means such as a screen printing method, and the resistor paste for the resistor portion 6a of the bias conductor 6 is first applied. A ceramic green sheet to be a first dielectric layer 1a and a ceramic green sheet to be a second dielectric layer 1b; A green product by stacking it is sufficient to prepare. The metal paste for the conductor portion 6b of the bias conductor 6 and the resistor paste for the resistor portion 6a of the bias conductor 6 may be printed and applied on the upper surface of the ceramic green sheet that becomes the second dielectric layer 1b. The through conductor 6c can be formed by forming a through hole in the ceramic green sheet to be the first dielectric layer 1a and filling the through hole with a metal paste. Similarly, when the connecting conductor 3b is a through conductor, a through hole is formed in the ceramic green sheet to be the first dielectric layer 1a and the ceramic green sheet to be the second dielectric layer 1b and filled with a metal paste. Just keep it. When the connection conductor 3b is a side conductor, a metal paste may be printed and applied to the side surface after producing the generated shape. The metal paste is prepared by adding and mixing an appropriate organic binder or solvent to the metal powder. For example, if the first dielectric layer 1a and the second dielectric layer 1b are made of an alumina ceramic, tungsten (W), molybdenum (Mo), manganese (Mn), or the like is used as the metal powder. If the first dielectric layer 1a and the second dielectric layer 1b are made of glass ceramics, copper (Cu), silver (Ag), palladium (Pd), an Ag—Pd alloy, or the like is used. The signal line conductor 2, the first ground conductor 3, the second ground conductor 3a, the first resistor 4, the bias terminal electrode 5, and the side conductor (connection conductor 3b) on the outer surface of the dielectric substrate 1 are ceramic green. Instead of forming the sheet by simultaneous firing with the sheet, the dielectric substrate 1 on which the internal bias conductor 6, the through conductor 6c, and the through conductor as the connecting conductor 3b are formed is formed, and then formed by a thin film forming method such as a vapor deposition method. May be. In particular, the first resistor 4 is preferably formed by a thin film forming method because the terminal resistance value can be accurately formed.

配線基板７の誘電体基板１が別々に作製したセラミックスから成る第１の誘電体層１ａと第２の誘電体層１ｂとを接合したものである場合は、信号線路導体２，第１の接地導体３，バイアス端子電極５，バイアス導体６の導体部６ｂは、これらの導体用の金属ペーストを、バイアス導体６の抵抗体部６ａは、抵抗体ペーストを第１の誘電体層１ａとなるセラミックグリーンシートまたは焼成後の第１の誘電体層１ａにスクリーン印刷法等の塗布手段により印刷塗布し、焼成することによって第１の誘電体層１ａに形成することができる。この第１の誘電体層１ａと、同様にして第２の接地導体３ａを形成した第２の誘電体層１ｂとを積層して接合することによって形成することができる。バイアス導体６は第２の誘電体層１ｂとなるセラミックグリーンシートまたは焼成後の第２の誘電体層１ｂの上面に形成してもよい。貫通導体６ｃ、貫通導体である接続導体３ｂは、グリーンシートに貫通孔を形成して貫通孔に金属ペーストを充填しておくことにより、あるいは焼成後の誘電体層１ａ，１ｂに形成した貫通孔に金属ペーストを充填して焼成することにより形成することができる。また、この場合も信号線路導体２，第１の接地導体３，第２の接地導体３ａ，第１の抵抗体４，バイアス端子電極５，バイアス導体６（第２の抵抗体６ａおよび導体部６ｂ）は、内部に貫通導体６ｃおよび接続導体３である貫通導体が形成された第１の誘電体層１ａおよび第２の誘電体層１ｂを作製した後に、蒸着法等の薄膜形成法にて形成してもよい。接続導体３ｂが側面導体である場合は、第１の誘電体層１ａと第２の誘電体層１ｂとを積層して接合した後に薄膜形成法により形成すればよい。第１の誘電体層１ａと第２の誘電体層１ｂとを接合するには、それぞれに形成された貫通導体６ｃをはんだや導電性接着剤等の導電性接合材で接続した後に周囲をエポキシ樹脂等の絶縁性樹脂で接合したり、異方性導電樹脂により接着したりすればよい。   When the dielectric substrate 1 of the wiring substrate 7 is formed by joining the first dielectric layer 1a and the second dielectric layer 1b made of ceramics separately produced, the signal line conductor 2, the first grounding Conductor 3, bias terminal electrode 5, conductor portion 6b of bias conductor 6 is a metal paste for these conductors, and resistor portion 6a of bias conductor 6 is a ceramic that serves as the first dielectric layer 1a. The first dielectric layer 1a can be formed by printing on the green sheet or the first dielectric layer 1a after firing by coating means such as a screen printing method and firing. The first dielectric layer 1a can be formed by laminating and joining the second dielectric layer 1b on which the second ground conductor 3a is formed in the same manner. The bias conductor 6 may be formed on the upper surface of the ceramic green sheet to be the second dielectric layer 1b or the fired second dielectric layer 1b. The through conductor 6c and the connecting conductor 3b, which is a through conductor, are formed by forming a through hole in a green sheet and filling the through hole with a metal paste, or through holes formed in the dielectric layers 1a and 1b after firing. It can be formed by filling and baking a metal paste. Also in this case, the signal line conductor 2, the first ground conductor 3, the second ground conductor 3a, the first resistor 4, the bias terminal electrode 5, the bias conductor 6 (the second resistor 6a and the conductor portion 6b). ) Is formed by a thin film formation method such as a vapor deposition method after the first dielectric layer 1a and the second dielectric layer 1b in which the through conductor 6c and the through conductor as the connection conductor 3 are formed are formed. May be. In the case where the connection conductor 3b is a side conductor, the first dielectric layer 1a and the second dielectric layer 1b may be stacked and bonded together and then formed by a thin film forming method. In order to join the first dielectric layer 1a and the second dielectric layer 1b, the through conductors 6c formed on the first dielectric layer 1a and the second dielectric layer 1b are connected with a conductive bonding material such as solder or conductive adhesive, and then the periphery is epoxy-bonded. What is necessary is just to join by insulating resin, such as resin, and adhere | attach by anisotropic conductive resin.

配線基板７の誘電体基板１がセラミックスから成る第１の誘電体層１ａと絶縁性の樹脂から成る第２の誘電体層１ｂとが積層されたものである場合は、上記と同様にして作製された、信号線路導体２，第１の接地導体３，第１の抵抗体４，バイアス端子電極５，バイアス導体６（第２の抵抗体６ａおよび導体部６ｂ），貫通導体６ｃおよび接続導体３である貫通導体が形成された第１の誘電体層１ａの上に、上述したような絶縁性樹脂からなる誘電体層１ｂを形成し、第１の誘電体層１ａの接続導体３である貫通導体に接続するように、第２の誘電体層１ｂにも接続導体３である貫通導体を形成し、さらにその上に薄膜形成法により第２の接地導体３ａを形成する。接続導体３が側面導体である場合は、第２の誘電体層１ｂ上に第２の接地導体３ａを形成した後に、薄膜形成法により形成すればよい。   When the dielectric substrate 1 of the wiring substrate 7 is formed by laminating the first dielectric layer 1a made of ceramics and the second dielectric layer 1b made of insulating resin, it is manufactured in the same manner as described above. Signal line conductor 2, first ground conductor 3, first resistor 4, bias terminal electrode 5, bias conductor 6 (second resistor 6 a and conductor portion 6 b), through conductor 6 c and connection conductor 3 A dielectric layer 1b made of an insulating resin as described above is formed on the first dielectric layer 1a on which the through conductor is formed, and the through conductor serving as the connection conductor 3 of the first dielectric layer 1a is formed. A through conductor as the connection conductor 3 is formed on the second dielectric layer 1b so as to be connected to the conductor, and a second ground conductor 3a is formed thereon by a thin film formation method. When the connecting conductor 3 is a side conductor, the second grounding conductor 3a is formed on the second dielectric layer 1b and then formed by a thin film forming method.

セラミックスから成る第１の誘電体層１ａの上に絶縁樹脂から成る第２の誘電体層１ｂを形成するには、例えば、ポリイミド樹脂からなる場合には、ワニス状のポリイミド前駆体を第１の誘電体層１ａの上面にスピンコート法・ダイコート法・カーテンコート法・印刷法等の塗布法により塗布し、しかる後、400℃程度の熱で硬化させてポリイミド化させることによって10μｍ〜100μｍ程度の厚みに形成する。あるいは、上記樹脂から成る10μｍ〜100μｍ程度のシートの下面に、シロキサン変性ポリアミドイミド樹脂，シロキサン変性ポリイミド樹脂，ポリイミド樹脂,ビスマレイミドトリアジン樹脂，エポキシ樹脂等の樹脂接着剤を乾燥厚みで５μｍ〜20μｍ程度にドクターブレード法等の塗布法にて塗布して乾燥させることで接着剤層を形成し、これを第１の誘電体層１ａの上に重ねて加熱プレスすることで形成する。塗布・硬化や加熱プレスを繰り返すことにより10μｍ〜50μｍの絶縁樹脂層を複数層積層して上記の厚みの第２の誘電体層１ｂとしてもよい。フィルムの樹脂を用いる方法は、複数のフィルムを一括してプレスすることが可能であり、１層毎に塗布および硬化を行なう必要がないので、製造工程を短くすることができる。   In order to form the second dielectric layer 1b made of insulating resin on the first dielectric layer 1a made of ceramic, for example, when made of polyimide resin, a varnish-like polyimide precursor is used as the first dielectric layer 1b. It is applied to the upper surface of the dielectric layer 1a by a coating method such as a spin coating method, a die coating method, a curtain coating method, a printing method, etc., and then cured by heat at about 400 ° C. to be converted into a polyimide, and the thickness is about 10 μm to 100 μm. Form to thickness. Alternatively, a resin adhesive such as a siloxane-modified polyamideimide resin, a siloxane-modified polyimide resin, a polyimide resin, a bismaleimide triazine resin, or an epoxy resin is dried on the lower surface of a sheet of about 10 μm to 100 μm made of the above resin with a dry thickness of about 5 μm to 20 μm. An adhesive layer is formed by applying and drying by a doctor blade method or the like, and the adhesive layer is formed on the first dielectric layer 1a by heating and pressing. A plurality of insulating resin layers having a thickness of 10 μm to 50 μm may be laminated by repeating coating / curing and heating press to form the second dielectric layer 1b having the above thickness. In the method using a resin for a film, a plurality of films can be pressed at once, and it is not necessary to apply and cure for each layer, so that the manufacturing process can be shortened.

第２の誘電体層１ｂに接続導体３ｂである貫通導体を形成する場合は、例えば、直径20μｍ〜100μｍの貫通孔を形成して貫通孔内に導体を形成することで貫通導体を形成する。貫通孔の形成方法は、まず絶縁樹脂層上に開口を有するレジスト膜を形成するとともにこのレジスト膜の開口に位置する絶縁樹脂層をエッチングすることによって、あるいはレーザを使い直接絶縁樹脂層の一部を除去することによって形成される。このときのレーザはエキシマレーザ，ＣＯ２レーザ等を用いることができるが、貫通孔の内壁の形状を垂直に近く調整でき、さらに貫通孔の内壁面を滑らかに加工できる紫外線レーザで形成しておくのが望ましい。あるいは、ワニス状の樹脂を塗布する方法の場合であれば、感光性の樹脂を用いて、例えば露光により貫通孔が形成される部分以外を硬化させて、貫通孔が形成される部分の樹脂をエッチングにより除去することにより貫通孔を形成してもよい。貫通孔内に導体を形成するには、例えば、銅等の金属粉末と樹脂を主成分とする導体ペーストを絶縁樹脂層の貫通孔に充填しておくことにより貫通孔が導体により充填されたものが形成される。あるいは、貫通孔の底面に位置する第１の誘電体層に形成された貫通導体が露出した面および貫通孔の内面に薄膜形成法により導体層を形成し、その上にめっき法により銅（Ｃｕ），金（Ａｕ），ニッケル（Ｎｉ）等の電気抵抗の小さい金属から成るめっき皮膜を形成してもよい。このめっき皮膜の厚みを厚くすると貫通孔が導体により充填されたものとすることができる。 When forming the through conductor as the connection conductor 3b in the second dielectric layer 1b, for example, the through conductor is formed by forming a through hole having a diameter of 20 μm to 100 μm and forming a conductor in the through hole. The through hole is formed by first forming a resist film having an opening on the insulating resin layer and etching the insulating resin layer located in the opening of the resist film, or by using a laser and directly part of the insulating resin layer. It is formed by removing. As the laser at this time, an excimer laser, a CO 2 laser, or the like can be used. However, the shape of the inner wall of the through hole can be adjusted almost vertically, and the inner wall surface of the through hole can be formed with an ultraviolet laser that can be processed smoothly. Is desirable. Alternatively, in the case of a method of applying a varnish-like resin, a photosensitive resin is used, for example, a portion other than a portion where a through-hole is formed by exposure is cured, and a resin in a portion where the through-hole is formed is obtained. The through hole may be formed by removing by etching. In order to form a conductor in the through hole, for example, the through hole of the insulating resin layer is filled with a conductive paste mainly composed of a metal powder such as copper and a resin and the through hole is filled with the conductor. Is formed. Alternatively, a conductor layer is formed on the exposed surface of the first dielectric layer located on the bottom surface of the through hole and the inner surface of the through hole by a thin film formation method, and copper (Cu ), Gold (Au), nickel (Ni) or the like, a plating film made of a metal having a small electric resistance may be formed. When the thickness of the plating film is increased, the through hole can be filled with a conductor.

信号線路導体２，第１の接地導体３，第２の接地導体３ａ，バイアス端子電極５，バイアス導体６の導体部６ｂを薄膜形成法を用いて形成する場合は、窒化タンタル（Ｔａ２Ｎ），ニッケル−クロム（Ｎｉ−Ｃｒ）合金，チタン（Ｔｉ）等から成る密着金属層の上に、ニッケル（Ｎｉ），ニッケル−クロム（Ｎｉ−Ｃｒ）合金，パラジウム（Ｐｄ），白金（Ｐｔ）等から成る拡散防止層を介して、銅（Ｃｕ），金（Ａｕ），ニッケル（Ｎｉ）等の電気抵抗の小さい金属から成る主導体層を形成する。薄膜形成法で信号線路導体２等の配線を貫通導体６ｃおよび接続導体３ｂの貫通導体の上に形成する場合は、貫通導体６ｃおよび接続導体３ｂの貫通導体が誘電体基板１の表面から露出する部分には、ニッケル（Ｎｉ）や金（Ａｕ）等の表面保護層を形成しておくことが好ましい。 When the signal line conductor 2, the first ground conductor 3, the second ground conductor 3 a, the bias terminal electrode 5, and the conductor portion 6 b of the bias conductor 6 are formed using a thin film forming method, tantalum nitride (Ta 2 N) Nickel (Ni), nickel-chromium (Ni-Cr) alloy, palladium (Pd), platinum (Pt), etc. on the adhesion metal layer made of nickel-chromium (Ni-Cr) alloy, titanium (Ti), etc. A main conductor layer made of a metal having a low electric resistance, such as copper (Cu), gold (Au), nickel (Ni), is formed through a diffusion prevention layer made of When the wiring such as the signal line conductor 2 is formed on the through conductors 6c and the through conductors 3b by the thin film forming method, the through conductors 6c and the through conductors of the connecting conductor 3b are exposed from the surface of the dielectric substrate 1. It is preferable to form a surface protective layer such as nickel (Ni) or gold (Au) on the part.

第１の抵抗体４の終端抵抗値およびバイアス導体６の第２の抵抗体６ａの抵抗値は、伝送される高周波信号の周波数や信号線路導体２の特性インピーダンスに応じて、適当な材質を選択し、その厚みや幅および形状を適宜設定して所望の値に設定される。   For the termination resistance value of the first resistor 4 and the resistance value of the second resistor 6a of the bias conductor 6, an appropriate material is selected in accordance with the frequency of the transmitted high-frequency signal and the characteristic impedance of the signal line conductor 2. Then, the thickness, width and shape are appropriately set and set to desired values.

第１の抵抗体４およびバイアス導体６の第２の抵抗体６ａは、所定の抵抗値が得られるものであれば特に制限はなく、薄膜形成法により第１の抵抗体４および第２の抵抗体６ａを形成する場合は、例えば窒化タンタル（Ｔａ２Ｎ），ニクロム（Ｎｉ−Ｃｒ合金）等の薄膜を用いて形成する。また、抵抗体ペーストを印刷塗布して焼成することにより形成する場合は、ＲｕＯ２等を主成分とする厚膜を用いて形成する。抵抗体ペーストは、主にガラス組成物、導電性材料、抵抗値および温度特性の調整等を目的とした金属酸化物等の添加物からなり、これらが有機ビヒクルと混合されてなるものである。ガラス組成物は、例えばＣａＯ，Ｂ２Ｏ３，ＳｉＯ２およびＭｎＯを含むＣａ−Ｂ−Ｓｉ−Ｍｎ−Ｏ系の鉛を含まないガラス組成が挙げられる。導電性材料としては、ＲｕＯ２等のルテニウム酸化物や、Ａｇ−Ｐｄ合金，Ａｇ−Ｐｔ合金，ＴａＮ，ＷＣ，ＬａＢ６，ＭｏＳｉＯ２，ＴａＳｉＯ２および金属（Ａｇ，Ａｕ，Ｐｔ，Ｐｄ，Ｃｕ，Ｎｉ，Ｗ，Ｍｏ等）が挙げられる。金属酸化物等の添加物としては、例えばＶ２Ｏ５，ＣｕＯ，ＺｎＯ，ＣｏＯ，ＭｎＯ２，Ｍｎ３Ｏ４が挙げられる。 The first resistor 4 and the second resistor 6a of the bias conductor 6 are not particularly limited as long as a predetermined resistance value can be obtained, and the first resistor 4 and the second resistor are formed by a thin film forming method. In the case of forming the body 6a, for example, a thin film such as tantalum nitride (Ta 2 N) or nichrome (Ni—Cr alloy) is used. In addition, when the resistor paste is formed by printing and baking, a thick film mainly composed of RuO 2 or the like is used. The resistor paste is mainly composed of an additive such as a glass composition, a conductive material, a resistance value and a metal oxide for the purpose of adjusting temperature characteristics, etc., and these are mixed with an organic vehicle. Examples of the glass composition include a Ca—B—Si—Mn—O based glass composition containing CaO, B 2 O 3 , SiO 2 and MnO. As the conductive material, and ruthenium oxide RuO 2, etc., Ag-Pd alloy, Ag-Pt alloy, TaN, WC, LaB 6, MoSiO 2, TaSiO 2 and metal (Ag, Au, Pt, Pd , Cu, Ni, W, Mo, etc.). Examples of additives such as metal oxides include V 2 O 5 , CuO, ZnO, CoO, MnO 2 , and Mn 3 O 4 .

配線基板７は、例えば、比誘電率が9.5の酸化アルミニウム質焼結体から成り、厚みが0.2ｍｍである誘電体基板１を用いた場合であれば、信号線路導体２の幅を0.1ｍｍ、厚みを0.002ｍｍとし、その両側に0.053ｍｍの間隔を設けて同じ厚みで誘電体基板１の外周縁まで第１の接地導体３を形成し、他方主面の全体に第２の接地導体３ａを形成して接続導体３ｂにより接続することにより、信号線路導体２を50Ωにインピーダンス整合させたグラウンド付きコプレーナ線路とすることができる。信号線路導体２，第１の接地導体３，第２の接地導体３ａを同様の寸法で形成した場合、厚みが0.14ｍｍである比誘電率が9.5の酸化アルミニウム質焼結体から成る第１の誘電体層１ａの上に、厚みが0.015ｍｍである比誘電率が3.4のポリイミド樹脂から成る第２の誘電体層１ｂを形成した誘電体基板１としても、同じく信号線路導体２を50Ωにインピーダンス整合させたグラウンド付きコプレーナ線路とすることができる。終端抵抗である第１の抵抗体４は抵抗値が50Ωになるように形成する。例えば第１の抵抗体４を薄膜で形成する場合であれば、窒化タンタル（Ｔａ２Ｎ）薄膜の幅を0.1ｍｍ、長さを0.1ｍｍ、厚みを約0.1μｍとすることで第１の抵抗体４の抵抗値が約50Ωとなる。必要に応じて形成した第１の抵抗体４の一部をレーザ加工によって除去して抵抗値を精度良く調整すればよい。 For example, when the dielectric substrate 1 made of an aluminum oxide sintered body having a relative dielectric constant of 9.5 and having a thickness of 0.2 mm is used, the wiring substrate 7 has a width of the signal line conductor 2 of 0.1 mm, The thickness is set to 0.002 mm, the first ground conductor 3 is formed to the outer peripheral edge of the dielectric substrate 1 with the same thickness with an interval of 0.053 mm on both sides thereof, and the second ground conductor 3a is formed on the entire other main surface. By forming and connecting with the connection conductor 3b, a grounded coplanar line in which the signal line conductor 2 is impedance-matched to 50Ω can be obtained. When the signal line conductor 2, the first ground conductor 3, and the second ground conductor 3 a are formed with the same dimensions, the first composed of an aluminum oxide sintered body having a thickness of 0.14 mm and a relative dielectric constant of 9.5. Similarly, the dielectric substrate 1 in which the second dielectric layer 1b made of polyimide resin having a relative dielectric constant of 3.4 having a thickness of 0.015 mm is formed on the dielectric layer 1a. It can be a coplanar track with a matched ground. The first resistor 4 which is a termination resistor is formed so that the resistance value is 50Ω. For example, when the first resistor 4 is formed as a thin film, the first resistor 4 is formed by setting the width of the tantalum nitride (Ta 2 N) thin film to 0.1 mm, the length to 0.1 mm, and the thickness to about 0.1 μm. The resistance value of the body 4 is about 50Ω. A part of the first resistor 4 formed as necessary may be removed by laser processing to adjust the resistance value with high accuracy.

バイアス導体６の一部が第２の抵抗体６ａである場合に、第２の抵抗体６ａの単位長さ当たりの電気抵抗が導体部６ｂの100倍以上であると、電磁結合による共振を第２の抵抗体６ａでほとんど熱エネルギーに変換して減衰し、その共振によるノイズが信号線路導体２に反射して返ることを減少させることができるので好ましい。ここで第２の抵抗体６ａが窒化タンタル（Ｔａ２Ｎ）の場合は、窒化タンタルの比抵抗は125μΩｃｍであり、導体部６ｂが銅（Ｃｕ）の場合は、銅の比抵抗は1.55μΩｃｍであるので、バイアス導体６において第２の抵抗体６ａと導体部６ｂが同じ幅であれば、導体部６ｂの銅の厚みを第２の抵抗体６ａの窒化タンタルよりも約25％厚く形成することで、第２の抵抗体６ａの単位長さ当たりの電気抵抗を導体部６ｂの単位長さ当たりの電気抵抗の100倍以上にすることができる。 When a part of the bias conductor 6 is the second resistor 6a, if the electric resistance per unit length of the second resistor 6a is 100 times or more that of the conductor 6b, resonance due to electromagnetic coupling is caused. The second resistor 6a is preferably converted into thermal energy and attenuated, and noise caused by the resonance can be reduced from being reflected back to the signal line conductor 2, which is preferable. Here, when the second resistor 6a is tantalum nitride (Ta 2 N), the specific resistance of tantalum nitride is 125 μΩcm, and when the conductor 6b is copper (Cu), the specific resistance of copper is 1.55 μΩcm. Therefore, if the second resistor 6a and the conductor portion 6b have the same width in the bias conductor 6, the copper thickness of the conductor portion 6b should be about 25% thicker than the tantalum nitride of the second resistor 6a. Thus, the electrical resistance per unit length of the second resistor 6a can be made 100 times or more the electrical resistance per unit length of the conductor portion 6b.

また、バイアス導体６に信号線路導体２の高周波信号が漏れないように、コンデンサを第１の抵抗体４と信号線路導体２との間に配置してもよい。このコンデンサは、バイアス導体６に流れる電流は直流であるので、その電流をカットして終端抵抗（第１の抵抗体４）に流れ込むことを防ぐ働きをする。   Further, a capacitor may be disposed between the first resistor 4 and the signal line conductor 2 so that the high-frequency signal of the signal line conductor 2 does not leak into the bias conductor 6. Since the current flowing through the bias conductor 6 is a direct current, this capacitor functions to cut the current and prevent it from flowing into the terminating resistor (first resistor 4).

図７（ａ）は本発明の半導体装置の実施の形態の一例を示す平面図であり、図７（ｂ）は図７（ａ）のＡ−Ａ線における断面図である。図７において、８は基体、８ａは搭載部、８ｂは基体固定孔、９は枠体、９ａは固定孔、10はバイアス端子、11は半導体素子、12は蓋体、13は信号端子、14は封止材、15は中継基板、16はボンディングワイヤである。なお、図７（ａ）の平面図は、蓋体12を外した状態を示している。   FIG. 7A is a plan view showing an example of an embodiment of the semiconductor device of the present invention, and FIG. 7B is a cross-sectional view taken along the line AA in FIG. In FIG. 7, 8 is a base, 8a is a mounting portion, 8b is a base fixing hole, 9 is a frame, 9a is a fixing hole, 10 is a bias terminal, 11 is a semiconductor element, 12 is a lid, 13 is a signal terminal, 14 Is a sealing material, 15 is a relay substrate, and 16 is a bonding wire. In addition, the top view of Fig.7 (a) has shown the state which removed the cover body 12. FIG.

本発明の半導体素子収納用パッケージは主として基体８と、基体８の上面に接合された枠体９と、枠体９内の基体８の上面に搭載された配線基板７と、配線基板７のバイアス端子電極５に電気的に接続されたバイアス端子10とで構成され、この半導体素子収納用パッケージに半導体素子11を搭載して配線基板７の信号線路導体２および第１の接地導体３に電気的に接続し、蓋体12を枠体９の上面に接合することにより封止して、本発明の半導体装置が構成される。   The semiconductor element storage package of the present invention mainly includes a base body 8, a frame body 9 bonded to the upper surface of the base body 8, a wiring board 7 mounted on the upper surface of the base body 8 in the frame body 9, and a bias of the wiring board 7. A bias terminal 10 electrically connected to the terminal electrode 5 is mounted. The semiconductor element 11 is mounted on the semiconductor element housing package, and the signal line conductor 2 and the first ground conductor 3 of the wiring board 7 are electrically connected. And the lid 12 is sealed by bonding to the upper surface of the frame 9 to constitute the semiconductor device of the present invention.

本発明の半導体素子収納用パッケージは、図７に示す例のように、金属から成り上面に配線基板７および半導体素子11を搭載する搭載部８ａを有する基体８と、基体８の上面に接合された搭載部８ａを取り囲む枠体９と、搭載部８ａに搭載された配線基板７と、配線基板７のバイアス端子電極５に電気的に接続されたバイアス端子10とを具備するものである。本発明の半導体素子収納用パッケージによれば、このような構成としたことから、バイアス導体と信号線路導体とが電磁結合したとしても抵抗により熱エネルギーに変換されて電磁結合が小さくなるので、信号線路導体２に不要な反射等が発生してインピーダンスが変化することが抑えられ、20ＧＨｚ以上の高周波信号においても伝達特性が向上して良好な終端特性を得ることができ、搭載する半導体素子12を高周波でも正常に動作させることができるようになる。   As shown in the example shown in FIG. 7, the semiconductor element storage package of the present invention is made of metal and has a base 8 having a mounting portion 8 a on which the wiring substrate 7 and the semiconductor element 11 are mounted on the top surface, and a top surface of the base body 8. A frame body 9 surrounding the mounting portion 8a, a wiring board 7 mounted on the mounting portion 8a, and a bias terminal 10 electrically connected to the bias terminal electrode 5 of the wiring substrate 7 are provided. According to the package for housing a semiconductor element of the present invention, since it is configured as described above, even if the bias conductor and the signal line conductor are electromagnetically coupled, they are converted into thermal energy by resistance and the electromagnetic coupling becomes small. It is possible to suppress an impedance change due to an unnecessary reflection or the like in the line conductor 2, improve a transmission characteristic even in a high-frequency signal of 20 GHz or higher, and obtain a favorable termination characteristic. It will be possible to operate normally even at high frequencies.

本発明の半導体装置は、図７に示す例のように、上記構成の本発明の半導体素子収納用パッケージと、搭載部８ａに搭載されて信号線路導体２および第１の接地導体３に電気的に接続された半導体素子11と、枠体９の上面に接合された蓋体12とを具備するものである。このような構成としたことから、本発明の配線基板７により良好な終端特性が得られるので、高周波においても半導体素子11が安定に動作する半導体装置を提供することができる。   As shown in the example shown in FIG. 7, the semiconductor device of the present invention is electrically connected to the signal line conductor 2 and the first grounding conductor 3 mounted on the mounting portion 8a and the semiconductor element housing package of the present invention having the above-described configuration. And the lid 12 joined to the upper surface of the frame body 9. With such a configuration, good termination characteristics can be obtained by the wiring substrate 7 of the present invention, so that a semiconductor device in which the semiconductor element 11 operates stably even at high frequencies can be provided.

基体８は、Ｆｅ−Ｎｉ−Ｃｏ合金等の金属やＣｕ−Ｗ焼結材等の金属から成る板状体であり、例えば金属インゴットに圧延加工や打ち抜き加工等の従来周知の金属加工法により、または射出成形したものに切削加工等を施すことによって、所定の形状に製作される。なお、基体８は図７に示す例のような四角形の板状体に限定されるものではなく、円形または多角形状の板状体であってもよい。また、図７に示す例のように、例えば、基体８を外部基板にねじ止めして固定するために用いる基体固定孔８ｂを基体８のコーナー部に設けてもよい。   The substrate 8 is a plate-like body made of a metal such as an Fe—Ni—Co alloy or a metal such as a Cu—W sintered material. For example, a metal ingot is rolled by a conventionally known metal processing method such as punching or Alternatively, it is manufactured into a predetermined shape by performing cutting or the like on the injection-molded one. The substrate 8 is not limited to a rectangular plate-like body as in the example shown in FIG. 7, and may be a circular or polygonal plate-like body. Further, as in the example shown in FIG. 7, for example, base fixing holes 8 b used for fixing the base 8 to the external substrate by screwing may be provided in the corner portion of the base 8.

配線基板７の基体８への搭載は、基体８の搭載部８ａにエポキシ樹脂等の樹脂製接着剤に銀等の導電性粒子を分散させた導電性接着剤あるいははんだなどの導電性の接合材で固定して行なわれる。   The wiring board 7 is mounted on the base 8 by a conductive adhesive such as a conductive adhesive or solder in which conductive particles such as silver are dispersed in a resin adhesive such as epoxy resin on the mounting portion 8 a of the base 8. It is done with fixed.

基体８と、基体８の搭載部８ａを取り囲む枠体９とにより、内側に半導体素子11を収容する空所を有する容器体となる。   The base body 8 and the frame body 9 surrounding the mounting portion 8a of the base body 8 form a container body having a space for accommodating the semiconductor element 11 inside.

枠体９は、基体８と同様のＦｅ−Ｎｉ−Ｃｏ合金やＣｕ−Ｗの焼結材等の金属や酸化アルミニウム質焼結体，窒化アルミニウム質焼結体等のセラミックスから成るものである。枠体９が金属から成る場合であれば、基体８と同時に一体成形するか、打ち抜き加工等の金属加工法により作製した枠体９を、基体８にＡｇろう等のろう材によりろう付けする、またはシーム溶接法等の溶接法により接合することで作製することができる。枠体９がセラミックスから成る場合であれば、枠体９の基体８との接合面に金属層を形成しておいてろう材で接合するか、活性金属を含むろう材により直接接合することにより作製することができる。   The frame body 9 is made of a metal such as an Fe—Ni—Co alloy or Cu—W sintered material similar to that of the base body 8, or a ceramic such as an aluminum oxide sintered body or an aluminum nitride sintered body. If the frame body 9 is made of metal, the frame body 9 is integrally formed simultaneously with the base body 8 or is brazed to the base body 8 using a brazing material such as Ag brazing. Or it can produce by joining by welding methods, such as a seam welding method. If the frame 9 is made of ceramics, a metal layer is formed on the bonding surface of the frame 9 with the base body 8 and bonded with a brazing material, or directly bonded with a brazing material containing an active metal. Can be produced.

なお、枠体９がセラミックスから成る場合は、その表面にメタライズ層等の導体層が形成されているのが好ましい。枠体９は、金属から成るか、または表面に導体層が形成された誘電体材料から成ることにより、内部の半導体素子11によって発生する放射ノイズまたは枠体９の外側から侵入して来る放射ノイズを遮蔽することができる。   In addition, when the frame body 9 consists of ceramics, it is preferable that conductor layers, such as a metallization layer, are formed in the surface. The frame body 9 is made of a metal or a dielectric material having a conductor layer formed on the surface thereof, so that radiated noise generated by the internal semiconductor element 11 or radiated noise entering from the outside of the frame body 9 is formed. Can be shielded.

図６に示す例では、外部より半導体素子11に駆動信号等を入力させる入出力用の信号端子13が枠体９に設置されている。Ｆｅ−Ｎｉ−Ｃｏ合金等の金属から成る信号端子13は枠体９の側面に形成された固定孔９ａにガラスから成る封止材14の中心を貫通して固定されている。あるいは、信号端子13を金属環内に封止材14で固定した後に、固定孔９ａ内に金属環を嵌め込むとともにＡｕ−Ｓｎ半田やＰｂ−Ｓｎ半田等の封着材により固定孔９ａに接合してもよい。   In the example shown in FIG. 6, an input / output signal terminal 13 for inputting a drive signal or the like to the semiconductor element 11 from the outside is provided on the frame body 9. A signal terminal 13 made of a metal such as an Fe—Ni—Co alloy is fixed to a fixing hole 9 a formed on the side surface of the frame 9 through the center of a sealing material 14 made of glass. Alternatively, after fixing the signal terminal 13 in the metal ring with the sealing material 14, the metal ring is fitted into the fixing hole 9a and joined to the fixing hole 9a by a sealing material such as Au-Sn solder or Pb-Sn solder. May be.

基体８および枠体９の表面には、耐食性に優れ、ろう材との濡れ性に優れた厚さが0.5〜９μｍのＮｉ層と厚さが0.5〜５μｍのＡｕ層とをめっき法により順次被着させておくのがよい。これにより、基体１が酸化腐食するのを有効に防止することができるとともに、配線基板７や半導体素子11をはんだにより良好に接合することができる。   On the surface of the base body 8 and the frame body 9, a Ni layer having a thickness of 0.5 to 9 μm and an Au layer having a thickness of 0.5 to 5 μm, which are excellent in corrosion resistance and wettability with a brazing material, are successively covered by a plating method. It is good to wear it. Thereby, it is possible to effectively prevent the base body 1 from being oxidatively corroded, and to satisfactorily join the wiring board 7 and the semiconductor element 11 with solder.

バイアス端子10は、Ｆｅ−Ｎｉ−Ｃｏ合金等の金属を打ち抜き加工等の金属加工法により加工することで作製され、ガラス等により枠体９の側面に形成された貫通孔内に固定される。   The bias terminal 10 is manufactured by processing a metal such as an Fe—Ni—Co alloy by a metal processing method such as punching, and is fixed in a through hole formed on the side surface of the frame body 9 by glass or the like.

枠体９内の基体８の上面に搭載された配線基板７のバイアス端子電極５とバイアス端子電極とを電気的に接続することで、本発明の半導体素子収納用パッケージとなる。バイアス端子電極５とバイアス端子６との電気的接続は、ボンディングワイヤ16により行なう。   By electrically connecting the bias terminal electrode 5 and the bias terminal electrode of the wiring board 7 mounted on the upper surface of the base body 8 in the frame body 9, the package for housing a semiconductor element of the present invention is obtained. Electrical connection between the bias terminal electrode 5 and the bias terminal 6 is performed by a bonding wire 16.

半導体素子11は、ＩＣ（Integrated circuit），ＬＳＩ（Large Scale Integrated circuit），ＬＤ（Laser Diode），ＰＤ（Photo Diode）であり、基体８の搭載部８ａへの搭載は、ＡｇろうやＡｇ−Ｃｕろう等のろう材，Ａｕ−ＳｎはんだやＰｂ−Ｓｎはんだ等のはんだ，エポキシ樹脂等の接着剤により基体８の上面に強固に接着固定することによって行なう。   The semiconductor element 11 is an integrated circuit (IC), a large scale integrated circuit (LSI), a laser diode (LD), or a photo diode (PD). The base 8 is mounted on the mounting portion 8a by Ag brazing or Ag-Cu. This is performed by firmly bonding and fixing to the upper surface of the substrate 8 with a brazing material such as brazing, solder such as Au—Sn solder or Pb—Sn solder, or an adhesive such as epoxy resin.

半導体素子11は、その電極が配線基板７の信号線路導体２および第１の接地導体３にそれぞれボンディングワイヤ16を介して電気的に接続される。また、図６および図７に示す例では、半導体素子11と信号端子13とが、それらの間の基体８の上面に搭載された中継基板15を介して電気的に接続されている。具体的には、半導体素子11の電極と中継基板15の上面に形成された信号線路導体とがボンディングワイヤ16により電気的に接続され、中継基板15の信号線路導体と信号端子13とがろう材等から成る導電性接着材を介して電気的に接続される。   The electrodes of the semiconductor element 11 are electrically connected to the signal line conductor 2 and the first ground conductor 3 of the wiring board 7 via bonding wires 16, respectively. In the example shown in FIGS. 6 and 7, the semiconductor element 11 and the signal terminal 13 are electrically connected via a relay substrate 15 mounted on the upper surface of the base 8 between them. Specifically, the electrode of the semiconductor element 11 and the signal line conductor formed on the upper surface of the relay substrate 15 are electrically connected by the bonding wire 16, and the signal line conductor of the relay substrate 15 and the signal terminal 13 are connected to the brazing material. They are electrically connected via a conductive adhesive made of, for example.

中継基板15は、セラミックスから成る誘電体基板上に信号線路導体が形成されたものであり、配線基板７と同様にして作製することができ、配線基板７と同様の方法で基体８の上に搭載される。   The relay substrate 15 has a signal line conductor formed on a dielectric substrate made of ceramics, and can be manufactured in the same manner as the wiring substrate 7, and can be formed on the substrate 8 in the same manner as the wiring substrate 7. Installed.

そして、本発明の半導体素子収納用パッケージに半導体素子11を搭載して、半導体素子11と配線基板７の信号線路導体２および第１の接地導体３とを電気的に接続した後に、ろう付け法やシームウエルド法等の溶接法により枠体９の上面に蓋体12を接合し、パッケージ内部を気密に封止することによって、本発明の半導体装置となる。   Then, after mounting the semiconductor element 11 on the semiconductor element storage package of the present invention and electrically connecting the semiconductor element 11 to the signal line conductor 2 and the first ground conductor 3 of the wiring board 7, the brazing method is performed. The lid 12 is joined to the upper surface of the frame 9 by a welding method such as the seam weld method or the like, and the inside of the package is hermetically sealed, thereby obtaining the semiconductor device of the present invention.

蓋体12は、Ｆｅ−Ｎｉ−Ｃｏ合金やＣｕ−Ｗの焼結材等の金属や酸化アルミニウム質焼結体，窒化アルミニウム質焼結体等のセラミックスから成る、板状のものである。図６に示す例のように、蓋体12の下面に段差を設けると、枠体９との位置合わせが容易となるのでよい。また、蓋体12がセラミックスから成る場合は、下面の周縁部に厚膜法や薄膜法で金属接合層を形成しておくことにより、ろう材による接合が可能となる。   The lid 12 is a plate-shaped member made of a metal such as an Fe—Ni—Co alloy or Cu—W sintered material, or a ceramic such as an aluminum oxide sintered body or an aluminum nitride sintered body. As in the example illustrated in FIG. 6, if a step is provided on the lower surface of the lid body 12, alignment with the frame body 9 may be facilitated. Further, when the lid 12 is made of ceramics, bonding with a brazing material can be performed by forming a metal bonding layer on the peripheral portion of the lower surface by a thick film method or a thin film method.

なお、本発明は、上述の実施の形態の例に限定されるものではなく、本発明の要旨を逸脱しない範囲であれば種々の変更は可能である。例えば、半導体素子11は、これに代えてＬｉＮｂＯ３（ニオブ酸リチウム：ＬＮ）の単結晶基板を用いた光変調素子を搭載したＬＮ光変調器であっても構わない。 Note that the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the present invention. For example, the semiconductor element 11 may be an LN optical modulator equipped with an optical modulation element using a single crystal substrate of LiNbO 3 (lithium niobate: LN) instead.

（ａ）は本発明の配線基板の実施の形態の一例を示す上面図であり、（ｂ）は（ａ）のＡ−Ａ線における断面図であり、（ｃ）は（ｂ）のＡ−Ａ線における断面図であり、（ｄ）は下面図である。(A) is a top view which shows an example of embodiment of the wiring board of this invention, (b) is sectional drawing in the AA of (a), (c) is A- of (b). It is sectional drawing in A line, (d) is a bottom view. （ａ）は本発明の配線基板の実施の形態の他の一例を示す上面図であり、（ｂ）は（ａ）のＡ−Ａ線における断面図であり、（ｃ）は（ｂ）のＡ−Ａ線における断面図であり、（ｄ）は下面図である。(A) is a top view which shows another example of embodiment of the wiring board of this invention, (b) is sectional drawing in the AA of (a), (c) is (b) It is sectional drawing in the AA line, (d) is a bottom view. （ａ）は本発明の配線基板の実施の形態の他の例を示す上面図であり、（ｂ）は断面図である。(A) is a top view which shows the other example of embodiment of the wiring board of this invention, (b) is sectional drawing. （ａ）は本発明の配線基板の実施の形態の一例を示す上面図であり、（ｂ）は断面図である。(A) is a top view which shows an example of embodiment of the wiring board of this invention, (b) is sectional drawing. （ａ）は本発明の配線基板の実施の形態の一例を示す上面図であり、（ｂ）は断面図である。(A) is a top view which shows an example of embodiment of the wiring board of this invention, (b) is sectional drawing. 本発明の配線基板の等価回路図である。It is an equivalent circuit diagram of the wiring board of the present invention. （ａ）は本発明の半導体装置の実施の形態の一例を示す平面図であり、（ｂ）は（ａ）のＡ−Ａ線における断面図である。(A) is a top view which shows an example of embodiment of the semiconductor device of this invention, (b) is sectional drawing in the AA of (a). （ａ）は従来の半導体装置の実施の形態の一例を示す平面図であり、（ｂ）は（ａ）のＡ−Ａ線における断面図である。(A) is a top view which shows an example of embodiment of the conventional semiconductor device, (b) is sectional drawing in the AA of (a). （ａ）は従来の半導体装置に搭載されている配線基板の上面図であり、（ｂ）は（ａ）のＡ−Ａ線の断面図であり、（ｃ）は下面図である。(A) is a top view of the wiring board mounted in the conventional semiconductor device, (b) is a sectional view of the AA line of (a), (c) is a bottom view.

符号の説明Explanation of symbols

１：誘電体基板
１ａ：第１の誘電体層
１ｂ：第２の誘電体層
２：信号線路導体
３：第１の接地導体
３ａ：第２の接地導体
３ｂ：接続導体
４：第１の抵抗体
５：バイアス端子電極
６：バイアス導体
６ａ：第２の抵抗体
６ｂ：導体部
６ｃ：貫通導体
７：配線基板
８：基体
８ａ：搭載部
８ｂ：基体固定孔
９：枠体
９ａ：固定孔
１０：バイアス端子
１１：半導体素子
１２：蓋体
１３：信号端子
１４：封止材
１５：中継基板
１６：ボンディングワイヤ 1: Dielectric substrate 1a: First dielectric layer 1b: Second dielectric layer 2: Signal line conductor 3: First ground conductor 3a: Second ground conductor 3b: Connection conductor 4: First resistor Body 5: Bias terminal electrode 6: Bias conductor 6a: Second resistor 6b: Conductor portion 6c: Through conductor 7: Wiring substrate 8: Base body 8a: Mounting portion 8b: Base body fixing hole 9: Frame body 9a: Fixed hole 10 : Bias terminal 11: Semiconductor element 12: Lid 13: Signal terminal 14: Sealing material 15: Relay substrate 16: Bonding wire

Claims (4)

誘電体基板と、該誘電体基板の一方主面上に配置された信号線路導体と、該信号線路導体の両側に間隔を設けて配置された第１の接地導体と、前記誘電体基板の他方主面に配置され、前記第１の接地導体と接続導体を介して接続されている第２の接地導体と、前記信号線路導体の一端と前記第１の接地導体とを接続する第１の抵抗体と、前記誘電体基板の一方主面上に前記第１の接地導体と絶縁されて配置されたバイアス端子電極と、前記誘電体基板の内部に配置された、一端が前記信号線路導体の前記一端に、および他端が前記バイアス端子電極にそれぞれ貫通導体を介して接続されており、両端間の少なくとも一部が第２の抵抗体からなるバイアス導体とを具備することを特徴とする配線基板。 A dielectric substrate; a signal line conductor disposed on one principal surface of the dielectric substrate; a first ground conductor disposed on both sides of the signal line conductor; and the other of the dielectric substrate A first resistor disposed on the main surface and connected to the first ground conductor and the first ground conductor; and a first resistor connecting the one end of the signal line conductor and the first ground conductor. Body, a bias terminal electrode disposed on one main surface of the dielectric substrate and insulated from the first ground conductor, and one end disposed inside the dielectric substrate, the one end of the signal line conductor A wiring board comprising: one end and the other end connected to the bias terminal electrode via a through conductor, and at least a part between the both ends including a bias conductor made of a second resistor. . 前記バイアス導体の前記第２の抵抗体以外の導体部の長さが、前記信号線路導体により伝送する信号の波長の１／４未満であることを特徴とする請求項１に記載の配線基板。 The wiring board according to claim 1, wherein a length of a conductor portion other than the second resistor of the bias conductor is less than ¼ of a wavelength of a signal transmitted by the signal line conductor. 金属から成り上面に前記配線基板および半導体素子を搭載する搭載部を有する基体と、該基体の上面に接合された前記搭載部を取り囲む枠体と、前記搭載部に搭載された請求項１または請求項２に記載の配線基板と、該配線基板の前記バイアス端子電極に電気的に接続されたバイアス端子とを具備することを特徴とする半導体素子収納用パッケージ。 2. A base body made of metal and having a mounting portion on which the wiring board and the semiconductor element are mounted, a frame surrounding the mounting portion joined to the upper surface of the base body, and a mounting body mounted on the mounting portion. Item 3. A package for housing a semiconductor element, comprising: the wiring board according to Item 2; and a bias terminal electrically connected to the bias terminal electrode of the wiring board. 請求項３に記載の半導体素子収納用パッケージと、前記搭載部に搭載されて前記信号線路導体および前記第１の接地導体に電気的に接続された半導体素子と、前記枠体の上面に接合された蓋体とを具備することを特徴とする半導体装置。 The semiconductor element storage package according to claim 3, a semiconductor element mounted on the mounting portion and electrically connected to the signal line conductor and the first ground conductor, and joined to an upper surface of the frame body. A semiconductor device comprising a lid.
JP2008217912A 2008-08-27 2008-08-27 Wiring substrate and package for storing semiconductor element, and semiconductor device Pending JP2010056203A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2008217912A JP2010056203A (en) 2008-08-27 2008-08-27 Wiring substrate and package for storing semiconductor element, and semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2008217912A JP2010056203A (en) 2008-08-27 2008-08-27 Wiring substrate and package for storing semiconductor element, and semiconductor device

Publications (1)

Publication Number Publication Date
JP2010056203A true JP2010056203A (en) 2010-03-11

Family

ID=42071824

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008217912A Pending JP2010056203A (en) 2008-08-27 2008-08-27 Wiring substrate and package for storing semiconductor element, and semiconductor device

Country Status (1)

Country Link
JP (1) JP2010056203A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015045790A (en) * 2013-08-29 2015-03-12 富士通オプティカルコンポーネンツ株式会社 Optical module and optical transmission device
JP2015055840A (en) * 2013-09-13 2015-03-23 富士通オプティカルコンポーネンツ株式会社 Optical module and optical transmitter

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015045790A (en) * 2013-08-29 2015-03-12 富士通オプティカルコンポーネンツ株式会社 Optical module and optical transmission device
JP2015055840A (en) * 2013-09-13 2015-03-23 富士通オプティカルコンポーネンツ株式会社 Optical module and optical transmitter
CN104467980A (en) * 2013-09-13 2015-03-25 富士通光器件株式会社 Optical module and optical transmitter
CN104467980B (en) * 2013-09-13 2018-01-23 富士通光器件株式会社 Optical module and optical transmitter

Similar Documents

Publication Publication Date Title
JP5473583B2 (en) Electronic component mounting package and electronic device using the same
JP5334887B2 (en) Electronic component mounting package and electronic device using the same
JP5240726B2 (en) Connection structure between semiconductor device and circuit board
WO2013099936A1 (en) Input/output member, package for housing electronic component, and electronic apparatus
JP5241609B2 (en) Structure, connection terminal, package, and electronic device
JP5178476B2 (en) Wiring board, semiconductor element storage package, and semiconductor device
JP5309039B2 (en) High-frequency wiring board, electronic component storage package, electronic device and communication device
JP2010056203A (en) Wiring substrate and package for storing semiconductor element, and semiconductor device
JP2003152124A (en) High frequency package
JP2010103453A (en) Wiring board, package for housing semiconductor element and semiconductor device
JP2010109407A (en) Wiring board, package for semiconductor element storage, and semiconductor device
JP5404484B2 (en) Electronic component mounting package and electronic device using the same
JP2010129647A (en) Wiring board, package for semiconductor element storage, and semiconductor device
JP3702241B2 (en) Semiconductor element storage package and semiconductor device
JP3690656B2 (en) Semiconductor element storage package and semiconductor device
JP2010135712A (en) Wiring board, semiconductor element storage package and semiconductor device
JP5171751B2 (en) WIRING BOARD, ACTIVE ELEMENT STORAGE PACKAGE USING THE SAME, AND ACTIVE ELEMENT DEVICE
JP3780509B2 (en) Semiconductor element storage package and semiconductor device
JP3652278B2 (en) Semiconductor element storage package and semiconductor device
JP3805272B2 (en) Semiconductor element storage package and semiconductor device
JP3934972B2 (en) Circuit board, semiconductor element storage package, and semiconductor device
JP3934971B2 (en) Circuit board, semiconductor element storage package, and semiconductor device
JP4164011B2 (en) Semiconductor element storage package and semiconductor device
JP2002319645A (en) Package for housing semiconductor element and semiconductor device
JP2004228532A (en) Input/output terminal, semiconductor element housing package, and semiconductor device