JP2003077755A - Capacitor - Google Patents

Capacitor

Info

Publication number
JP2003077755A
JP2003077755A JP2001263253A JP2001263253A JP2003077755A JP 2003077755 A JP2003077755 A JP 2003077755A JP 2001263253 A JP2001263253 A JP 2001263253A JP 2001263253 A JP2001263253 A JP 2001263253A JP 2003077755 A JP2003077755 A JP 2003077755A
Authority
JP
Japan
Prior art keywords
capacitor
internal electrodes
dielectric layer
capacitance
ceramic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001263253A
Other languages
Japanese (ja)
Inventor
Tatsuya Inoue
竜也 井上
Hidenori Katsumura
英則 勝村
Akihito Konishi
彰仁 小西
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP2001263253A priority Critical patent/JP2003077755A/en
Publication of JP2003077755A publication Critical patent/JP2003077755A/en
Pending legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To obtain a low capacitance capacitor whose capacitance is not higher than 10 pF. SOLUTION: Dielectric layers 11 each having a specific inductive capacity of smaller than 10 and inner electrodes 12 are alternately layered to constitute a laminated unit 13. After the laminated unit 13 is baked, an outer electrode 14 is formed so as to be electrically connected with the inner electrodes 12 to obtain a capacitor whose capacitance is not larger than 10 pF.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は例えばRFモジュー
ルのカップリングやマッチング回路などに使用されるコ
ンデンサに関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a capacitor used in a coupling or matching circuit of an RF module, for example.

【0002】[0002]

【従来の技術】従来のコンデンサについて説明する。2. Description of the Related Art A conventional capacitor will be described.

【0003】容量が10pF以下というコンデンサは、
比誘電率が30〜70の誘電体層と内部電極とを交互に
積層し、内部電極の露出した端面に外部電極を形成した
ものであった。
A capacitor having a capacitance of 10 pF or less is
The dielectric layers having a relative dielectric constant of 30 to 70 and the internal electrodes were alternately laminated, and the external electrodes were formed on the exposed end faces of the internal electrodes.

【0004】この誘電体層はCaTiO3系のセラミッ
クからなるものである。また内部電極はパラジウムやニ
ッケルが一般的であった。
This dielectric layer is made of CaTiO 3 ceramic. Further, the internal electrodes were generally palladium or nickel.

【0005】[0005]

【発明が解決しようとする課題】上記構成においては、
誘電体層の比誘電率が30〜70とそれほど小さくない
ために、積層体の形成時に内部電極に位置ずれが生じる
と容量が大きく変わるため、所望の容量を有するコンデ
ンサを生産性良く得ることができないという問題点を有
していた。
In the above configuration,
Since the relative permittivity of the dielectric layer is not so small as 30 to 70, if the internal electrodes are misaligned during the formation of the laminated body, the capacitance changes greatly, so that a capacitor having a desired capacitance can be obtained with high productivity. It had a problem that it could not be done.

【0006】そこで本発明は、容量が10pF以下のコ
ンデンサを生産性良く得ることを目的とするものであ
る。
Therefore, an object of the present invention is to obtain a capacitor having a capacitance of 10 pF or less with high productivity.

【0007】[0007]

【課題を解決するための手段】上記目的を達成するため
に、以下の構成を有するものである。
In order to achieve the above object, it has the following constitution.

【0008】本発明の請求項1に記載の発明は、特に、
誘電体層の比誘電率を10未満としたものであり、多少
の内部電極の位置ずれが生じたとしても容量が10pF
以下のコンデンサを生産性良く得ることができる。
The invention according to claim 1 of the present invention is
The relative dielectric constant of the dielectric layer is less than 10, and the capacitance is 10 pF even if the internal electrodes are slightly displaced.
The following capacitors can be obtained with good productivity.

【0009】本発明の請求項2に記載の発明は、特に、
誘電体層としてガラスセラミックを用いたものであり、
内部電極に高周波帯域での損失を小さくできる銀や銅を
使用することができる。
The invention according to claim 2 of the present invention is
It uses glass ceramic as the dielectric layer,
It is possible to use silver or copper for the internal electrodes, which can reduce loss in the high frequency band.

【0010】本発明の請求項3に記載の発明は、特に、
内部電極に銀または銅を用いたものであり、高周波帯域
の損失を小さくできる。
The invention according to claim 3 of the present invention is
Since silver or copper is used for the internal electrodes, the loss in the high frequency band can be reduced.

【0011】本発明の請求項4に記載の発明は、特に、
誘電体層としてAl23−MgO−SiO2−Ge23
系組成物及びホウケイ酸ガラスを含有するものを用いた
ものであり、内部電極に高周波帯域での損失が小さい銀
または銅を使用することができる。
The invention according to claim 4 of the present invention is
As a dielectric layer, Al 2 O 3 —MgO—SiO 2 —Ge 2 O 3
The composition containing the system composition and borosilicate glass is used, and silver or copper, which has a small loss in a high frequency band, can be used for the internal electrode.

【0012】[0012]

【発明の実施の形態】以下、一実施の形態を用いて、本
発明の請求項1〜請求項4に記載の発明について説明す
る。
BEST MODE FOR CARRYING OUT THE INVENTION The invention described in claims 1 to 4 of the present invention will be described below with reference to one embodiment.

【0013】図1は一実施の形態における積層セラミッ
クコンデンサの一部切欠斜視図であり、11はAl23
−MgO−SiO2−Ge23系組成物及びホウケイ酸
ガラスを含有する比誘電率が約7の誘電体層、12はA
gまたはCuを主成分とする内部電極、13は誘電体層
11と内部電極12とを交互に積層した積層体、14は
積層体13の内部電極12の露出した両端面に設けた外
部電極である。
FIG. 1 is a partially cutaway perspective view of a monolithic ceramic capacitor according to an embodiment, and 11 is Al 2 O 3
-MgO-SiO 2 -Ge 2 O 3 based composition and dielectric constant containing borosilicate glass is approximately 7 of the dielectric layer, 12 is A
An internal electrode containing g or Cu as a main component, 13 is a laminated body in which dielectric layers 11 and internal electrodes 12 are alternately laminated, and 14 is an external electrode provided on both exposed end surfaces of the internal electrode 12 of the laminated body 13. is there.

【0014】以上のように構成された積層セラミックコ
ンデンサ(1005サイズ、0.7pF)の製造方法に
ついて説明する。
A method of manufacturing the monolithic ceramic capacitor (1005 size, 0.7 pF) configured as described above will be described.

【0015】まず、Al23−MgO−SiO2−Ge2
3系組成物及びホウケイ酸ガラスを含むセラミック材
料に、酢酸ブチル、有機バインダ、可塑剤を加えて混合
し、スラリーを得る。
First, Al 2 O 3 --MgO--SiO 2 --Ge 2
Butyl acetate, an organic binder, and a plasticizer are added to a ceramic material containing an O 3 composition and borosilicate glass and mixed to obtain a slurry.

【0016】次にこのスラリーをリバースロール法でシ
ート化し、適当な大きさに切断し、誘電体層11となる
セラミックグリーンシートを得る。
Next, the slurry is formed into a sheet by a reverse roll method and cut into a suitable size to obtain a ceramic green sheet which will become the dielectric layer 11.

【0017】次いでこのセラミックグリーンシート上に
内部電極12となるAgまたはCuを主成分とする電極
ペーストを所望の形状に印刷し、セラミックグリーンシ
ートと内部電極12が交互になるように積層して積層体
を形成し、所望のサイズの個片に切断し、積層体13を
得る。
Next, an electrode paste containing Ag or Cu as a main component to form the internal electrodes 12 is printed on the ceramic green sheets in a desired shape, and the ceramic green sheets and the internal electrodes 12 are laminated in an alternating manner. A body is formed and cut into pieces of a desired size to obtain a laminated body 13.

【0018】その後積層体13を400〜700℃で熱
処理して脱脂を行って、有機成分を飛散させた後、85
0〜950℃で焼成する。
After that, the laminated body 13 is heat-treated at 400 to 700 ° C. to degrease it to scatter the organic components, and then 85
Bake at 0-950 ° C.

【0019】次いで積層体13の表面を研磨し、内部電
極12の露出した両端面に外部電極14となるAgペー
ストを塗布し、800〜900℃で焼き付けて図1に示
すコンデンサを得る。
Next, the surface of the laminated body 13 is polished, Ag paste serving as the external electrodes 14 is applied to both exposed end surfaces of the internal electrodes 12, and baked at 800 to 900 ° C. to obtain the capacitor shown in FIG.

【0020】このようにして得たコンデンサの容量及び
Q値を(表1)、(表2)に示す。No.1は従来のコンデ
ンサであり比較例である。またこれらのコンデンサはす
べて0.7pFを有するように各5ロットずつ作製し
た。
The capacitance and Q value of the capacitors thus obtained are shown in (Table 1) and (Table 2). No. Reference numeral 1 is a conventional capacitor, which is a comparative example. Further, each of these capacitors was manufactured in 5 lots so as to have 0.7 pF.

【0021】[0021]

【表1】 [Table 1]

【0022】[0022]

【表2】 [Table 2]

【0023】(表2)には、ロット毎の容量の平均値及
びその偏差およびロット1全体の歩留まりを示してい
る。歩留まりは0.7pF±10%を良品とした時の値
である。
Table 2 shows the average value of the capacity of each lot, its deviation, and the yield of the whole lot 1. The yield is a value when 0.7 pF ± 10% is a good product.

【0024】比誘電率が60のNo.1のコンデンサ
は、各ロットの平均容量のバラツキが非常に大きくなっ
ている。これに対し、比誘電率が10以下のNo.2〜
4は全て平均容量のバラツキが小さい。また、ロット1
の歩留まりもNo.1に比べNo.2〜4では大きく改
善されていることがわかる。
No. 1 having a relative dielectric constant of 60 The capacitor No. 1 has a very large variation in the average capacity of each lot. On the other hand, in No. 2 to
All 4 have small variations in average capacity. Also, lot 1
The yield of No. No. 1 compared to 1. It can be seen that in Nos. 2 to 4, there is a great improvement.

【0025】また、内部電極12としてパラジウムを用
いたNo.2と比較すると、導電率がパラジウムの5倍
以上ある銀や銅を用いたNo.3,4の方が、1GHz
といった高周波帯域でのQ値は非常に大きい。従って損
失の少ないコンデンサとなる。
In addition, No. 1 using palladium as the internal electrode 12 In comparison with No. 2, No. 2 using silver or copper, whose conductivity is 5 times or more that of palladium. 3 and 4 are 1 GHz
The Q value in the high frequency band is very large. Therefore, the capacitor has a small loss.

【0026】このように、誘電体層11を結晶化ガラス
とセラミックを混合したガラスセラミック、例えばホウ
ケイ酸ガラスとAl23−MgO−SiO2−Ge23
系組成物を用いて形成することにより、比誘電率が10
未満と小さいので、内部電極12の形成位置に多少のず
れが発生したとしても、容量が10pFと小さいコンデ
ンサを生産性良く得ることができる。
Thus, the dielectric layer 11 is a glass-ceramic in which crystallized glass and ceramic are mixed, for example, borosilicate glass and Al 2 O 3 --MgO--SiO 2 --Ge 2 O 3
The relative permittivity is 10 when formed by using the system composition.
Therefore, even if the position where the internal electrode 12 is formed is slightly displaced, a capacitor having a small capacitance of 10 pF can be obtained with good productivity.

【0027】また従来使用していたパラジウムの5倍以
上の導電率を有する銀や銅を用いて内部電極12を形成
することにより、高周波帯域における損失の少ないコン
デンサを得ることができる。
Further, by forming the internal electrode 12 using silver or copper having a conductivity five times or more that of the conventionally used palladium, it is possible to obtain a capacitor with a small loss in a high frequency band.

【0028】[0028]

【発明の効果】以上のように本発明は、誘電体層の比誘
電率が10未満と小さくすることにより、容量が10p
F以下と低容量のコンデンサを生産性良く得ることがで
きる。
As described above, according to the present invention, the dielectric constant of the dielectric layer is as small as less than 10, so that the capacitance is 10 p.
Capacitors of F or less and low capacity can be obtained with good productivity.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施の形態における積層セラミック
コンデンサの一部切欠斜視図
FIG. 1 is a partially cutaway perspective view of a monolithic ceramic capacitor according to an embodiment of the present invention.

【符号の説明】[Explanation of symbols]

11 誘電体層 12 内部電極 13 積層体 14 外部電極 11 Dielectric layer 12 internal electrodes 13 laminate 14 External electrode

───────────────────────────────────────────────────── フロントページの続き (72)発明者 小西 彰仁 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 Fターム(参考) 5E001 AB03 AE02 AH01 AJ01 AJ02 5E082 AA01 AB03 FF05 FG06 FG25 FG26 FG46    ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Akinori Konishi             1006 Kadoma, Kadoma-shi, Osaka Matsushita Electric             Sangyo Co., Ltd. F-term (reference) 5E001 AB03 AE02 AH01 AJ01 AJ02                 5E082 AA01 AB03 FF05 FG06 FG25                       FG26 FG46

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 誘電体層と内部電極とを交互に積層した
積層体と、この積層体の表面に前記内部電極と電気的に
接続するように設けた外部電極とを備え、前記誘電体層
は比誘電率が10未満であり、容量を10pF以下とし
たコンデンサ。
1. A dielectric layer comprising: a laminated body in which dielectric layers and internal electrodes are alternately laminated; and external electrodes provided on the surface of the laminated body so as to be electrically connected to the internal electrodes. Is a capacitor having a relative dielectric constant of less than 10 and a capacitance of 10 pF or less.
【請求項2】 誘電体層は結晶化ガラスとセラミックを
混合したガラスセラミックである請求項1に記載のコン
デンサ。
2. The capacitor according to claim 1, wherein the dielectric layer is a glass ceramic obtained by mixing crystallized glass and ceramic.
【請求項3】 内部電極は銀または銅である請求項1に
記載のコンデンサ。
3. The capacitor according to claim 1, wherein the internal electrodes are silver or copper.
【請求項4】 誘電体層はAl23−MgO−SiO2
−Ge23系組成物及びホウケイ酸ガラスを含有する請
求項1に記載のコンデンサ。
4. The dielectric layer is Al 2 O 3 —MgO—SiO 2
-Ge 2 O 3 type capacitor according to claim 1 containing the composition and borosilicate glass.
JP2001263253A 2001-08-31 2001-08-31 Capacitor Pending JP2003077755A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2001263253A JP2003077755A (en) 2001-08-31 2001-08-31 Capacitor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001263253A JP2003077755A (en) 2001-08-31 2001-08-31 Capacitor

Publications (1)

Publication Number Publication Date
JP2003077755A true JP2003077755A (en) 2003-03-14

Family

ID=19090037

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001263253A Pending JP2003077755A (en) 2001-08-31 2001-08-31 Capacitor

Country Status (1)

Country Link
JP (1) JP2003077755A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100706686B1 (en) 2004-04-09 2007-04-11 티디케이가부시기가이샤 Laminated electronic parts and manufacturing method thereof
JP2013115424A (en) * 2011-11-25 2013-06-10 Samsung Electro-Mechanics Co Ltd Multilayer ceramic electronic component and manufacturing method for the same
JP2017216360A (en) * 2016-05-31 2017-12-07 太陽誘電株式会社 Multilayer ceramic capacitor
JP2017216358A (en) * 2016-05-31 2017-12-07 太陽誘電株式会社 Multilayer ceramic capacitor
JP2017216361A (en) * 2016-05-31 2017-12-07 太陽誘電株式会社 Multilayer ceramic capacitor and method for manufacturing the same

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0748171A (en) * 1993-08-04 1995-02-21 Yamamura Glass Co Ltd Composition for low-temperature baked substrate and substrate therefrom
JPH0786079A (en) * 1993-06-28 1995-03-31 Taiyo Yuden Co Ltd Chip capacitor for high frequency
JP2000247682A (en) * 1999-02-26 2000-09-12 Kyocera Corp Glass ceramic wiring board

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0786079A (en) * 1993-06-28 1995-03-31 Taiyo Yuden Co Ltd Chip capacitor for high frequency
JPH0748171A (en) * 1993-08-04 1995-02-21 Yamamura Glass Co Ltd Composition for low-temperature baked substrate and substrate therefrom
JP2000247682A (en) * 1999-02-26 2000-09-12 Kyocera Corp Glass ceramic wiring board

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100706686B1 (en) 2004-04-09 2007-04-11 티디케이가부시기가이샤 Laminated electronic parts and manufacturing method thereof
JP2013115424A (en) * 2011-11-25 2013-06-10 Samsung Electro-Mechanics Co Ltd Multilayer ceramic electronic component and manufacturing method for the same
JP2017216360A (en) * 2016-05-31 2017-12-07 太陽誘電株式会社 Multilayer ceramic capacitor
JP2017216358A (en) * 2016-05-31 2017-12-07 太陽誘電株式会社 Multilayer ceramic capacitor
JP2017216361A (en) * 2016-05-31 2017-12-07 太陽誘電株式会社 Multilayer ceramic capacitor and method for manufacturing the same
US10522291B2 (en) 2016-05-31 2019-12-31 Taiyo Yuden Co., Ltd. Multilayer ceramic capacitor and manufacturing method of multilayer ceramic capacitor

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