JP2002118199A - 半導体装置 - Google Patents
半導体装置Info
- Publication number
- JP2002118199A JP2002118199A JP2000308740A JP2000308740A JP2002118199A JP 2002118199 A JP2002118199 A JP 2002118199A JP 2000308740 A JP2000308740 A JP 2000308740A JP 2000308740 A JP2000308740 A JP 2000308740A JP 2002118199 A JP2002118199 A JP 2002118199A
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- semiconductor device
- chip
- stress buffer
- posts
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- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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Abstract
され、半導体チップはポストを突出させた状態で樹脂封
止した後に、外部端子としてポスト上に半田ボールが設
置されるタイプのCSPにおいて、半導体チップと封止
樹脂の線膨張係数の差でポストにかかる応力によるクラ
ックの発生を改良した半導体装置を得る。 【解決手段】 ポスト4に加わる応力を緩和させるため
に、ポスト4の中間に例えば、金(Au)、パラジウム
(Pd)等の低ヤング率の金属層などの応力緩衝材10
を挿入した。
Description
製造する半導体装置に関するものである。
薄型化に伴い、LSIパッケージ自体の小型化が要求さ
れており、半導体チップと同等のサイズであるチップス
ケールパッケージ(Chip Scale Package;CSP)が開
発されている。CSPは、半導体チップにプリント基板
やフィルムキャリヤが電気的かつ機械的に接続され、外
部端子としてプリント基板やフィルムキャリヤに半田ボ
ールが設置されているタイプと、プリント基板やフィル
ムキャリヤを使用せずに、半導体チップの電極パッド上
にポストが設置され、半導体チップはポストを突出させ
た状態で樹脂封止した後に、外部端子としてポスト上に
半田ボールが設置されるタイプがある。
図であって、1は半導体チップ、2は電極パッド、3は
保護絶縁膜、4はポスト(接続用導体)、5は封止樹
脂、そして6は外部端子である。後者タイプのCSPは
前者タイプのCSPと比べて樹脂封止及び外部端子を形
成するのにプリント基板やフィルムキャリヤを使用しな
いので、製造コストで有利である。
者タイプのCSPは、構造上、チップと封止樹脂の線膨
張係数の差で、ポストにかかる応力でクラックが生じる
という問題があった。
なされたものであり、本発明の目的はこのようなクラッ
クの発生を改良した半導体装置を得ることである。
体装置は、ウエハレベルで製造され、半導体チップ上に
ポストを利用した接続構造を有する半導体装置におい
て、同材料で2層以上、または2種類以上の材料により
構成されたポストを備えるものである。
ポスト間に、金またはパラジウムからなる応力緩衝材を
備えたものである。
は、ポスト間に、同種金属であって異なる硬さの金属を
重ねて形成した応力緩衝材を備えたものである。
ポスト間に、異方性導電性膜からなる応力緩衝材を備え
たものである。
は、ポスト間に、金属粒子を含んだ導電性樹脂からなる
応力緩衝材を備えたものである。
ウエハレベルで製造され、半導体チップ上にポストを利
用した接続構造を有する半導体装置において、封止樹脂
を多層にしてポストを分割し、傾斜させるように接続し
たものである。
各樹脂層のポストの径を実質的に同一にしたものであ
る。
各樹脂層のポストの径を層順に異なるようにしたもので
ある。
の実施の形態1における半導体装置を示す断面図であ
る。半導体素子を含む集積回路が形成された半導体チッ
プ1の素子面側には、電気的に集積回路と接続されるよ
うに電極パッド2が配置されている。電極パッド2の周
辺は、電極パッド2が開口されるように保護絶縁膜3が
形成されている。電極パッド2の上には、同材料で2層
以上、または2種類以上の材料にて構成されるポスト
(接続用導体)4が形成されている。
を緩和させるために、ポスト4の中間に応力緩衝材10
を挿入している。例えば、応力緩衝材10として、金
(Au)、パラジウム(Pd)等の低ヤング率の金属
層、または、導電性粒子が内在された異方性導電材料、
または、Auペーストのような金属粒子を含んだ導電性
樹脂を用いても良い。あるいは、同種金属であっても、
製造方法の違いにより、材料の硬さを変えたものを重ね
て、ポスト4を構成してもかまわない。前記ポスト4の
周囲には、ポスト4を被覆するように、封止樹脂5が形
成されている。また、ポスト4上面には、バンプ(外部
端子)6が機械的かつ電気的に接続されている。
おける半導体装置によれば、ポストの中間に応力緩衝材
10を挿入したので、ポストに加わる応力を緩和でき
る。
は、この発明の実施の形態2における半導体装置を示す
断面図である。半導体素子を含む集積回路が形成された
半導体チップ1の素子面側には、電気的に集積回路と接
続されるように、電極パッド2が配置されている。電極
パッド2の周辺は、電極パッド2が開口されるように保
護絶縁膜3が形成されている。
以上に、即ち2層以上で構成されるポスト(接続用導
体)4が設置されているが、ポスト4自体に加わる応力
を低減させるために、ポスト4を分割し、傾斜させるよ
うに形成されている。各封止樹脂層5のポスト径は、図
2(a)に示すように同一径であってもよいし、また
は、図2(b)に示すように封止樹脂層5毎にポスト径
を異なるようにしてもよい。前記ポスト4の周囲には、
ポスト4を被覆するように、封止樹脂5が形成されてい
る。また、ポスト4上面には、バンプ(外部端子)6が
機械的かつ電気的に接続されている。
ける半導体装置によれば、ポスト4を分割し傾斜させる
ように形成したので、ポスト4に加わる応力を緩和でき
る。
れているので、以下に示すような効果を奏する。
ベルで製造され、チップ上にポストを利用した接続構造
を有する半導体装置において、ポストを同材料で2層以
上、または2種類以上の材料により構成したので、ポス
ト4に加わる応力を緩和できる。
ば、ウエハレベルで製造され、半導体チップ上にポスト
を利用した接続構造を有する半導体装置において、封止
樹脂を多層にしてポストを分割し、傾斜させるように接
続したので、ポスト4に加わる応力を緩和できる。
示す断面図である。
示す断面図である。
Claims (8)
- 【請求項1】 ウエハレベルで製造され、半導体チップ
上にポストを利用した接続構造を有する半導体装置にお
いて、同材料で2層以上、または2種類以上の材料によ
り構成されたポストを備えることを特徴とする半導体装
置。 - 【請求項2】 ポスト間に、金またはパラジウムからな
る応力緩衝材を備えたことを特徴とする、請求項1に記
載の半導体装置。 - 【請求項3】 ポスト間に、同種金属であって異なる硬
さの金属を重ねて形成した応力緩衝材を備えたことを特
徴とする、請求項1に記載の半導体装置。 - 【請求項4】 ポスト間に、異方性導電性膜からなる応
力緩衝材を備えたことを特徴とする、請求項1に記載の
半導体装置。 - 【請求項5】 ポスト間に、金属粒子を含んだ導電性樹
脂からなる応力緩衝材を備えたことを特徴とする、請求
項1に記載の半導体装置。 - 【請求項6】 ウエハレベルで製造され、半導体チップ
上にポストを利用した接続構造を有する半導体装置にお
いて、封止樹脂を多層にしてポストを分割し、傾斜させ
るように接続したことを特徴とする半導体装置。 - 【請求項7】 各樹脂層のポストの径を実質的に同一に
したことを特徴とする、請求項6に記載の半導体装置。 - 【請求項8】 各樹脂層のポストの径を層順に異なるよ
うにしたことを特徴とする、請求項6に記載の半導体装
置。
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JP2000308740A JP2002118199A (ja) | 2000-10-10 | 2000-10-10 | 半導体装置 |
US09/818,906 US7141879B2 (en) | 2000-10-10 | 2001-03-28 | Semiconductor device |
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JP2000308740A JP2002118199A (ja) | 2000-10-10 | 2000-10-10 | 半導体装置 |
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JP2002118199A true JP2002118199A (ja) | 2002-04-19 |
Family
ID=18789000
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JP2000308740A Pending JP2002118199A (ja) | 2000-10-10 | 2000-10-10 | 半導体装置 |
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US (1) | US7141879B2 (ja) |
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