JP2002118199A - 半導体装置 - Google Patents

半導体装置

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Publication number
JP2002118199A
JP2002118199A JP2000308740A JP2000308740A JP2002118199A JP 2002118199 A JP2002118199 A JP 2002118199A JP 2000308740 A JP2000308740 A JP 2000308740A JP 2000308740 A JP2000308740 A JP 2000308740A JP 2002118199 A JP2002118199 A JP 2002118199A
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JP
Japan
Prior art keywords
post
semiconductor device
chip
stress buffer
posts
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000308740A
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English (en)
Inventor
Keiichiro Wakamiya
敬一郎 若宮
Satoshi Yamada
聡 山田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP2000308740A priority Critical patent/JP2002118199A/ja
Priority to US09/818,906 priority patent/US7141879B2/en
Publication of JP2002118199A publication Critical patent/JP2002118199A/ja
Pending legal-status Critical Current

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Abstract

(57)【要約】 【課題】 半導体チップの電極パッド上にポストが設置
され、半導体チップはポストを突出させた状態で樹脂封
止した後に、外部端子としてポスト上に半田ボールが設
置されるタイプのCSPにおいて、半導体チップと封止
樹脂の線膨張係数の差でポストにかかる応力によるクラ
ックの発生を改良した半導体装置を得る。 【解決手段】 ポスト4に加わる応力を緩和させるため
に、ポスト4の中間に例えば、金(Au)、パラジウム
(Pd)等の低ヤング率の金属層などの応力緩衝材10
を挿入した。

Description

【発明の詳細な説明】
【0001】
【発明の属する技術分野】この発明は、ウエハレベルで
製造する半導体装置に関するものである。
【0002】
【従来の技術】近年、LSIを使用する電子機器の小型
薄型化に伴い、LSIパッケージ自体の小型化が要求さ
れており、半導体チップと同等のサイズであるチップス
ケールパッケージ(Chip Scale Package;CSP)が開
発されている。CSPは、半導体チップにプリント基板
やフィルムキャリヤが電気的かつ機械的に接続され、外
部端子としてプリント基板やフィルムキャリヤに半田ボ
ールが設置されているタイプと、プリント基板やフィル
ムキャリヤを使用せずに、半導体チップの電極パッド上
にポストが設置され、半導体チップはポストを突出させ
た状態で樹脂封止した後に、外部端子としてポスト上に
半田ボールが設置されるタイプがある。
【0003】図3は、後者タイプの従来のCSPの断面
図であって、1は半導体チップ、2は電極パッド、3は
保護絶縁膜、4はポスト(接続用導体)、5は封止樹
脂、そして6は外部端子である。後者タイプのCSPは
前者タイプのCSPと比べて樹脂封止及び外部端子を形
成するのにプリント基板やフィルムキャリヤを使用しな
いので、製造コストで有利である。
【0004】
【発明が解決しようとする課題】上記のような従来の後
者タイプのCSPは、構造上、チップと封止樹脂の線膨
張係数の差で、ポストにかかる応力でクラックが生じる
という問題があった。
【0005】この発明はかかる問題点を解決するために
なされたものであり、本発明の目的はこのようなクラッ
クの発生を改良した半導体装置を得ることである。
【0006】
【課題を解決するための手段】第1の発明にかかる半導
体装置は、ウエハレベルで製造され、半導体チップ上に
ポストを利用した接続構造を有する半導体装置におい
て、同材料で2層以上、または2種類以上の材料により
構成されたポストを備えるものである。
【0007】また、第2の発明にかかる半導体装置は、
ポスト間に、金またはパラジウムからなる応力緩衝材を
備えたものである。
【0008】さらに、第3の発明にかかる半導体装置
は、ポスト間に、同種金属であって異なる硬さの金属を
重ねて形成した応力緩衝材を備えたものである。
【0009】また、第4の発明にかかる半導体装置は、
ポスト間に、異方性導電性膜からなる応力緩衝材を備え
たものである。
【0010】さらに、第5の発明にかかる半導体装置
は、ポスト間に、金属粒子を含んだ導電性樹脂からなる
応力緩衝材を備えたものである。
【0011】また、第6の発明にかかる半導体装置は、
ウエハレベルで製造され、半導体チップ上にポストを利
用した接続構造を有する半導体装置において、封止樹脂
を多層にしてポストを分割し、傾斜させるように接続し
たものである。
【0012】さらに、第7発明にかかる半導体装置は、
各樹脂層のポストの径を実質的に同一にしたものであ
る。
【0013】また、第8の発明にかかる半導体装置は、
各樹脂層のポストの径を層順に異なるようにしたもので
ある。
【0014】
【発明の実施の形態】実施の形態1.図1は、この発明
の実施の形態1における半導体装置を示す断面図であ
る。半導体素子を含む集積回路が形成された半導体チッ
プ1の素子面側には、電気的に集積回路と接続されるよ
うに電極パッド2が配置されている。電極パッド2の周
辺は、電極パッド2が開口されるように保護絶縁膜3が
形成されている。電極パッド2の上には、同材料で2層
以上、または2種類以上の材料にて構成されるポスト
(接続用導体)4が形成されている。
【0015】前記ポスト4には、ポスト4に加わる応力
を緩和させるために、ポスト4の中間に応力緩衝材10
を挿入している。例えば、応力緩衝材10として、金
(Au)、パラジウム(Pd)等の低ヤング率の金属
層、または、導電性粒子が内在された異方性導電材料、
または、Auペーストのような金属粒子を含んだ導電性
樹脂を用いても良い。あるいは、同種金属であっても、
製造方法の違いにより、材料の硬さを変えたものを重ね
て、ポスト4を構成してもかまわない。前記ポスト4の
周囲には、ポスト4を被覆するように、封止樹脂5が形
成されている。また、ポスト4上面には、バンプ(外部
端子)6が機械的かつ電気的に接続されている。
【0016】以上説明したように、この実施の形態1に
おける半導体装置によれば、ポストの中間に応力緩衝材
10を挿入したので、ポストに加わる応力を緩和でき
る。
【0017】実施の形態2.図2(a)及び図2(b)
は、この発明の実施の形態2における半導体装置を示す
断面図である。半導体素子を含む集積回路が形成された
半導体チップ1の素子面側には、電気的に集積回路と接
続されるように、電極パッド2が配置されている。電極
パッド2の周辺は、電極パッド2が開口されるように保
護絶縁膜3が形成されている。
【0018】電極パッド2上には、封止樹脂層5を2層
以上に、即ち2層以上で構成されるポスト(接続用導
体)4が設置されているが、ポスト4自体に加わる応力
を低減させるために、ポスト4を分割し、傾斜させるよ
うに形成されている。各封止樹脂層5のポスト径は、図
2(a)に示すように同一径であってもよいし、また
は、図2(b)に示すように封止樹脂層5毎にポスト径
を異なるようにしてもよい。前記ポスト4の周囲には、
ポスト4を被覆するように、封止樹脂5が形成されてい
る。また、ポスト4上面には、バンプ(外部端子)6が
機械的かつ電気的に接続されている。
【0019】以上説明したように、この実施の形態2お
ける半導体装置によれば、ポスト4を分割し傾斜させる
ように形成したので、ポスト4に加わる応力を緩和でき
る。
【0020】
【発明の効果】この発明は、以上説明したように構成さ
れているので、以下に示すような効果を奏する。
【0021】第1ないし第5の発明によれば、ウエハレ
ベルで製造され、チップ上にポストを利用した接続構造
を有する半導体装置において、ポストを同材料で2層以
上、または2種類以上の材料により構成したので、ポス
ト4に加わる応力を緩和できる。
【0022】また、第6、第7及び第8の発明によれ
ば、ウエハレベルで製造され、半導体チップ上にポスト
を利用した接続構造を有する半導体装置において、封止
樹脂を多層にしてポストを分割し、傾斜させるように接
続したので、ポスト4に加わる応力を緩和できる。
【図面の簡単な説明】
【図1】この発明の実施の形態1における半導体装置を
示す断面図である。
【図2】この発明の実施の形態2における半導体装置を
示す断面図である。
【図3】従来の半導体装置を示す断面図である。
【符号の説明】
1 半導体チップ 4 ポスト 5 封止樹脂 10 応力緩衝材

Claims (8)

    【特許請求の範囲】
  1. 【請求項1】 ウエハレベルで製造され、半導体チップ
    上にポストを利用した接続構造を有する半導体装置にお
    いて、同材料で2層以上、または2種類以上の材料によ
    り構成されたポストを備えることを特徴とする半導体装
    置。
  2. 【請求項2】 ポスト間に、金またはパラジウムからな
    る応力緩衝材を備えたことを特徴とする、請求項1に記
    載の半導体装置。
  3. 【請求項3】 ポスト間に、同種金属であって異なる硬
    さの金属を重ねて形成した応力緩衝材を備えたことを特
    徴とする、請求項1に記載の半導体装置。
  4. 【請求項4】 ポスト間に、異方性導電性膜からなる応
    力緩衝材を備えたことを特徴とする、請求項1に記載の
    半導体装置。
  5. 【請求項5】 ポスト間に、金属粒子を含んだ導電性樹
    脂からなる応力緩衝材を備えたことを特徴とする、請求
    項1に記載の半導体装置。
  6. 【請求項6】 ウエハレベルで製造され、半導体チップ
    上にポストを利用した接続構造を有する半導体装置にお
    いて、封止樹脂を多層にしてポストを分割し、傾斜させ
    るように接続したことを特徴とする半導体装置。
  7. 【請求項7】 各樹脂層のポストの径を実質的に同一に
    したことを特徴とする、請求項6に記載の半導体装置。
  8. 【請求項8】 各樹脂層のポストの径を層順に異なるよ
    うにしたことを特徴とする、請求項6に記載の半導体装
    置。
JP2000308740A 2000-10-10 2000-10-10 半導体装置 Pending JP2002118199A (ja)

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