WO2006035689A1 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- WO2006035689A1 WO2006035689A1 PCT/JP2005/017587 JP2005017587W WO2006035689A1 WO 2006035689 A1 WO2006035689 A1 WO 2006035689A1 JP 2005017587 W JP2005017587 W JP 2005017587W WO 2006035689 A1 WO2006035689 A1 WO 2006035689A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- post
- electrode pad
- semiconductor device
- semiconductor chip
- resin layer
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05005—Structure
- H01L2224/05008—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05569—Disposition the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13022—Disposition the bump connector being at least partially embedded in the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13024—Disposition the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0105—Tin [Sn]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
Definitions
- the present invention relates to a semiconductor device, and more particularly to a semiconductor device to which WL-CSP (Wafer Level-Chip Scale Package) is applied.
- WL-CSP Wafer Level-Chip Scale Package
- WL-CSP Wafer Level-Chip Scale Package
- a conventional semiconductor device to which WL-CSP is applied includes a semiconductor chip 101 having a functional element 101a formed on the surface, and an interlayer insulating film laminated on the surface of the semiconductor chip 101. 102, an internal wiring 103 disposed on the interlayer insulating film 102, a surface protective film 104 laminated on the interlayer insulating film 102 and the internal wiring 103, and a surface protective film 104 disposed on the surface protective film 104.
- a connection opening 108 is formed in the interlayer insulating film 102 at a position immediately above the functional element 101a, and the internal wiring 103 is connected to the functional element 101a through the connection opening 108.
- the internal wiring 103 is formed on the interlayer insulating film 102 so as to extend from the connection opening 108 toward the peripheral portion of the semiconductor chip 101.
- a pad opening 110 is formed in the peripheral portion so that a part of the internal wiring 103 serves as an electrode pad 109, and the rewiring 105 is formed through the pad opening 110. Connected to wiring 103 (electrode pad 109).
- the rewiring 105 is formed to extend to a position facing the solder ball 107 with the sealing resin layer 106 interposed therebetween, and the tip thereof is soldered via a boss 111 penetrating the sealing resin layer 106. Connected with Ball 107.
- an object of the present invention is to provide a semiconductor device that can eliminate the need for wiring for electrical connection between a functional element and an external connection terminal.
- a semiconductor device includes a semiconductor chip having a functional surface in which a functional element is formed, an electrode pad provided at a position immediately above the functional element on the functional surface of the semiconductor chip, and the semiconductor chip A protective resin layer laminated on the functional surface, an external connection terminal provided on the protective resin layer at a position facing the electrode pad, and the protective resin layer connected to the electrode pad and the external connection.
- a post is provided penetrating in a direction facing the terminal, and connecting the electrode pad and the external connection terminal.
- an electrode pad is provided immediately above the functional element, and an external connection terminal is disposed on the protective resin layer at a position facing the electrode pad.
- the electrode pad and the external connection terminal are connected through a post that penetrates the protective resin layer in the facing direction.
- the size of the post when viewed in a direction orthogonal to the functional surface of the semiconductor chip may be smaller than the size of the electrode pad when viewed in the direction.
- the post may be formed in a size smaller than the electrode pad when viewed in a direction orthogonal to the functional surface of the semiconductor chip.
- the entire end face of the post on the electrode pad side can be bonded to the electrode pad. Therefore, it is possible to prevent a surface protective film or the like from being interposed between the post and the electrode pad.
- even when stress is applied to the external connection terminals and posts when the semiconductor device is bonded to a wiring board or the like it is possible to prevent the surface protective film and the like from being damaged by the stress.
- the post may be a size when viewed in a direction perpendicular to the functional surface of the semiconductor chip.
- the post may be equal to or larger than the size of the electrode pad when viewed in the direction.
- the post may be formed in a size substantially the same as or larger than the electrode pad when viewed in a direction orthogonal to the functional surface of the semiconductor chip. In this case, even when stress is applied to the external connection terminals when this semiconductor device is bonded to a wiring board or the like, the stress can be absorbed by the boss, so that the electrode pad and the functional element are damaged. It is possible to prevent this.
- the post is preferably made of silver, tin, or gold.
- Silver, tin, or gold is more ductile than copper, so silver, tin, or gold-powered posts will deform when stressed or immediately relieve stress compared to copper-powered posts be able to. Therefore, the length of the post can be shortened compared to the case where the post also has a copper force. If the post is short, the plating time for forming the post can be shortened.
- the liquid resist can be used when forming the post, the post can be formed more easily.
- the thickness of the semiconductor device thickness in the direction orthogonal to the functional surface of the semiconductor chip) can be reduced.
- the post when the post also has gold strength, gold is a very stable element, and since the adhesive strength between the post and the protective resin layer (bonding force between gold and resin) is small, it protects the semiconductor chip. Even if a deviation due to the difference in thermal expansion coefficient occurs between the resin layer and the resin layer, the shear stress acting between the post and the electrode pad due to this deviation can be absorbed by the deformation of the post. Therefore, it is possible to prevent the electrical connection between the boss and the electrode pad from being broken.
- a plurality of the electrode pads may be provided and arranged in a lattice pattern.
- the semiconductor device may be a semiconductor device to which WL-CSP is applied.
- FIG. 1 is a plan view showing a simplified configuration of a semiconductor device according to an embodiment of the present invention.
- FIG. 2 is a simplified cross-sectional view of the semiconductor device shown in FIG. 1 taken along cutting line AA. is there.
- FIG. 3 is a diagram showing an example of electrode pad arrangement on the functional surface of the semiconductor chip of the semiconductor device shown in FIG. 1.
- FIG. 3 is a diagram showing an example of electrode pad arrangement on the functional surface of the semiconductor chip of the semiconductor device shown in FIG. 1.
- FIG. 4 is a cross-sectional view schematically showing a configuration of a semiconductor device according to another embodiment of the present invention.
- FIG. 5 is a simplified cross-sectional view showing a configuration of a conventional WL-CSP semiconductor device.
- FIG. 1 is a plan view showing a configuration of a semiconductor device according to an embodiment of the present invention.
- FIG. 2 is a simplified cross-sectional view of the semiconductor device taken along the cutting line AA shown in FIG.
- This semiconductor device is a semiconductor device to which WL-CSP (Wafer Level Chip Scale Package) is applied, and has a functional surface la in which a functional element 11 is formed, A surface protective film 2 laminated on the functional surface la of the semiconductor chip 1 and a protective resin layer 3 laminated on the surface protective film 2 are provided.
- WL-CSP Wafer Level Chip Scale Package
- each electrode pad 4 is formed in a rectangular plate shape using aluminum. Further, as shown in FIG. 2, each electrode pad 4 is arranged at a position immediately above the functional element 11 formed on the functional surface la of the semiconductor chip 1.
- a circular opening 5 is formed in the surface protective film 2 at a position opposed to each electrode pad 4 in the direction orthogonal to the functional surface 1a. The central portion of the electrode pad 4 is exposed from the surface protective film 2 through the opening 5.
- Metal ball 6 is placed on the protective resin layer 3, as an external connection terminal for connection (external connection) to a wiring board or the like at a position facing the electrode pad 4 in a direction orthogonal to the functional surface la.
- the metal ball 6 is formed into a ball shape using a metal material such as solder.
- a cylindrical post 7 having a copper force is provided so as to penetrate the protective resin layer 3.
- the post 7 has a diameter substantially equal to the diameter of the opening 5, and when viewed in a direction orthogonal to the functional surface la of the semiconductor chip 1, the size of the post 7 is an electrode pad. The size is smaller than the fourth.
- the post 7 has one end connected to the metal ball 6 and the other end inserted into the opening 5 and connected to the electrode pad 4.
- the electrode pad 4 is provided immediately above the functional element 11, and the metal ball 6 is disposed on the protective resin layer 3 at a position facing the electrode pad 4.
- a ball 6 is connected to the protective resin layer 3 through a post 7 that penetrates the protective resin layer 3 in the opposite direction.
- the structure of the semiconductor device can be simplified, the manufacturing process can be simplified, and the cost of the semiconductor device can be reduced.
- the distance between the functional element 11 (electrode pad 4) and the metal ball 6 is short, it is possible to improve element characteristics (such as operating speed).
- the post 7 is formed in a size smaller than the electrode pad 4 when viewed in a direction orthogonal to the functional surface la of the semiconductor chip 1. Therefore, since the surface protective film 2 is not interposed between the post 7 and the electrode pad 4, even if stress is applied to the metal ball 6 (both 7) when bonded to a wiring board or the like, the stress is not reduced. This prevents the surface protective film 2 from being damaged.
- the force that post 7 also has a copper force is not limited to copper.
- the post 7 which also has silver, tin (Sn), or gold (Au) may be used.
- the post 7, which also has silver, tin, or gold strength, can be deformed when stress is applied and can immediately relieve stress as compared to the post 7, which also has copper strength. Therefore, when the post 7 is formed of copper, the length (height) of the post 7 needs to be 50 to 90 ⁇ m, whereas when the post 7 is formed of silver, tin, or gold, the post 7 The length can be about 20 m. If the post 7 is short, the plating time for forming the post 7 can be shortened. In addition, since the liquid resist can be used when forming the post 7, the post 7 can be formed more easily. In addition, the thickness of the semiconductor device (thickness in the direction orthogonal to the functional surface la of the semiconductor chip 1) can be reduced.
- the post 7 when the post 7 also has a gold strength, gold is a very stable element, and the adhesive strength between the post 7 and the protective resin layer 3 (bonding strength between the gold and the resin) is small. Chip 1 and protective resin layer Even if a deviation due to the difference in thermal expansion coefficient occurs between the post 7 and the post 7, the shear stress acting between the post 7 and the electrode pad 4 can be absorbed by the deformation of the post 7. Therefore, it is possible to prevent the electrical connection between the post 7 and the electrode pad 4 from being broken.
- FIG. 4 is a cross-sectional view schematically showing a configuration of a semiconductor device according to another embodiment of the present invention.
- parts corresponding to the parts shown in FIG. 2 are denoted by the same reference numerals as in FIG.
- FIG. 4 only the parts different from the above-described embodiment will be described, and the description of the same parts as the above-described embodiment will be omitted.
- the force that takes up the configuration in which the post 7 is formed in a size smaller than the electrode pad 4 is used in the semiconductor device according to this embodiment.
- the post 7 has a size larger than that of the electrode pad 4 when viewed in a direction orthogonal to the functional surface la of the semiconductor chip 1.
- the post 7 is formed in a size larger than the electrode pad 4 when viewed in a direction orthogonal to the functional surface la of the semiconductor chip 1. Therefore, even when stress is applied to the metal ball 6 when this semiconductor device is bonded to a wiring board or the like, the stress can be absorbed by the post 7, so that the electrode pad 4 and the functional element 11 are damaged. This can be prevented.
- the force that the post 7 is formed in a size larger than the electrode pad 4 when viewed in the direction orthogonal to the functional surface la of the semiconductor chip 1 is the function of the semiconductor chip 1 Even when the post 7 and the electrode pad 4 are substantially the same size when viewed in a direction orthogonal to the plane la, the above-described effects can be obtained.
- the shapes of the electrode pad 4, the opening 5 and the post 7 are not particularly limited, and the electrode pad 4 may be formed in a circular shape, or the post 7 may be formed in a prismatic shape. Moyo. Further, the electrode pads 4 may be arranged so as to form a square frame along the periphery of the semiconductor chip 1 and to be aligned at almost equal intervals, for example.
- This application was filed with Japanese Patent Application No. 2004- 28201 6 filed with the Japan Patent Office on September 28, 2004, and October 28, 2004 [This Patent Office with Japanese Patent Application No. 2004-314395] And the Japanese Patent Application No. 2005-139955 filed with the Japan Patent Office on May 12, 2005, the entire disclosures of which are incorporated herein by reference.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Wire Bonding (AREA)
Abstract
Description
Claims
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN2005800309692A CN101019229B (zh) | 2004-09-28 | 2005-09-26 | 半导体装置 |
US11/663,856 US20080272488A1 (en) | 2004-09-28 | 2005-09-26 | Semiconductor Device |
Applications Claiming Priority (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004282016 | 2004-09-28 | ||
JP2004-282016 | 2004-09-28 | ||
JP2004-314395 | 2004-10-28 | ||
JP2004314395 | 2004-10-28 | ||
JP2005-139955 | 2005-05-12 | ||
JP2005139955A JP5129438B2 (ja) | 2004-09-28 | 2005-05-12 | 半導体装置 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2006035689A1 true WO2006035689A1 (ja) | 2006-04-06 |
Family
ID=36118835
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2005/017587 WO2006035689A1 (ja) | 2004-09-28 | 2005-09-26 | 半導体装置 |
Country Status (6)
Country | Link |
---|---|
US (1) | US20080272488A1 (ja) |
JP (1) | JP5129438B2 (ja) |
KR (1) | KR20070067090A (ja) |
CN (1) | CN101019229B (ja) |
TW (1) | TW200618234A (ja) |
WO (1) | WO2006035689A1 (ja) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008047732A (ja) | 2006-08-17 | 2008-02-28 | Sony Corp | 半導体装置及びその製造方法 |
JP5478009B2 (ja) | 2007-11-09 | 2014-04-23 | 株式会社フジクラ | 半導体パッケージの製造方法 |
JP5294611B2 (ja) * | 2007-11-14 | 2013-09-18 | スパンション エルエルシー | 半導体装置及びその製造方法 |
JP2009164442A (ja) * | 2008-01-09 | 2009-07-23 | Nec Electronics Corp | 半導体装置 |
JP6165411B2 (ja) * | 2011-12-26 | 2017-07-19 | 富士通株式会社 | 電子部品及び電子機器 |
JP5686838B2 (ja) * | 2013-04-02 | 2015-03-18 | スパンション エルエルシー | 半導体装置およびその製造方法 |
KR20220161767A (ko) | 2021-05-31 | 2022-12-07 | 삼성전자주식회사 | 반도체 패키지 장치 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002118199A (ja) * | 2000-10-10 | 2002-04-19 | Mitsubishi Electric Corp | 半導体装置 |
JP2002222898A (ja) * | 2001-01-24 | 2002-08-09 | Citizen Watch Co Ltd | 半導体装置及びその製造方法 |
JP2004095716A (ja) * | 2002-08-30 | 2004-03-25 | Toshiba Corp | 半導体装置の製造方法および半導体装置 |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06275794A (ja) * | 1993-03-18 | 1994-09-30 | Matsushita Electric Ind Co Ltd | 半導体記憶装置およびその製造方法 |
JP2000036518A (ja) * | 1998-07-16 | 2000-02-02 | Nitto Denko Corp | ウェハスケールパッケージ構造およびこれに用いる回路基板 |
JP2001068587A (ja) * | 1999-08-25 | 2001-03-16 | Hitachi Ltd | 半導体装置 |
US7242099B2 (en) * | 2001-03-05 | 2007-07-10 | Megica Corporation | Chip package with multiple chips connected by bumps |
JP2002319587A (ja) * | 2001-04-23 | 2002-10-31 | Seiko Instruments Inc | 半導体装置 |
JP4414117B2 (ja) * | 2001-08-23 | 2010-02-10 | 九州日立マクセル株式会社 | 半導体チップ及びこれを用いた半導体装置 |
US7358618B2 (en) * | 2002-07-15 | 2008-04-15 | Rohm Co., Ltd. | Semiconductor device and manufacturing method thereof |
JP2004071906A (ja) * | 2002-08-07 | 2004-03-04 | Rohm Co Ltd | 半導体装置 |
JP4093018B2 (ja) * | 2002-11-08 | 2008-05-28 | 沖電気工業株式会社 | 半導体装置及びその製造方法 |
JP3989869B2 (ja) * | 2003-04-14 | 2007-10-10 | 沖電気工業株式会社 | 半導体装置及びその製造方法 |
JP2005209861A (ja) * | 2004-01-22 | 2005-08-04 | Nippon Steel Corp | ウェハレベルパッケージ及びその製造方法 |
JP4390634B2 (ja) * | 2004-06-11 | 2009-12-24 | Okiセミコンダクタ株式会社 | 半導体装置 |
KR100697272B1 (ko) * | 2004-08-06 | 2007-03-21 | 삼성전자주식회사 | 강유전체 메모리 장치 및 그 제조 방법 |
-
2005
- 2005-05-12 JP JP2005139955A patent/JP5129438B2/ja not_active Expired - Fee Related
- 2005-09-26 US US11/663,856 patent/US20080272488A1/en not_active Abandoned
- 2005-09-26 CN CN2005800309692A patent/CN101019229B/zh not_active Expired - Fee Related
- 2005-09-26 WO PCT/JP2005/017587 patent/WO2006035689A1/ja active Application Filing
- 2005-09-26 KR KR1020077006039A patent/KR20070067090A/ko active Search and Examination
- 2005-09-28 TW TW094133771A patent/TW200618234A/zh unknown
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002118199A (ja) * | 2000-10-10 | 2002-04-19 | Mitsubishi Electric Corp | 半導体装置 |
JP2002222898A (ja) * | 2001-01-24 | 2002-08-09 | Citizen Watch Co Ltd | 半導体装置及びその製造方法 |
JP2004095716A (ja) * | 2002-08-30 | 2004-03-25 | Toshiba Corp | 半導体装置の製造方法および半導体装置 |
Also Published As
Publication number | Publication date |
---|---|
JP5129438B2 (ja) | 2013-01-30 |
TW200618234A (en) | 2006-06-01 |
US20080272488A1 (en) | 2008-11-06 |
KR20070067090A (ko) | 2007-06-27 |
CN101019229A (zh) | 2007-08-15 |
JP2006156937A (ja) | 2006-06-15 |
CN101019229B (zh) | 2010-05-05 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6621172B2 (en) | Semiconductor device and method of fabricating the same, circuit board, and electronic equipment | |
US7485490B2 (en) | Method of forming a stacked semiconductor package | |
JP3186941B2 (ja) | 半導体チップおよびマルチチップ半導体モジュール | |
KR100559664B1 (ko) | 반도체패키지 | |
US9455161B2 (en) | Semiconductor device and methods of manufacturing semiconductor devices | |
KR100461220B1 (ko) | 반도체 장치 및 그의 제조방법 | |
US20070216008A1 (en) | Low profile semiconductor package-on-package | |
US7420814B2 (en) | Package stack and manufacturing method thereof | |
US20100164088A1 (en) | Semiconductor package, manufacturing method thereof and ic chip | |
EP1662566A2 (en) | Semiconductor device and method of fabricating the same | |
WO2006035689A1 (ja) | 半導体装置 | |
JP2006287048A (ja) | 半導体装置 | |
US20070166882A1 (en) | Methods for fabricating chip-scale packages having carrier bonds | |
JP5337404B2 (ja) | 半導体装置および半導体装置の製造方法 | |
TWI237370B (en) | Chip package structure and process for fabricating the same | |
KR101345035B1 (ko) | 반도체 패키지 및 그 제조 방법 | |
US20070170571A1 (en) | Low profile semiconductor system having a partial-cavity substrate | |
KR100639556B1 (ko) | 칩 스케일 적층 패키지와 그 제조 방법 | |
JP2000091339A (ja) | 半導体装置およびその製造方法 | |
JP2007150346A (ja) | 半導体装置及びその製造方法、回路基板並びに電子機器 | |
JP2004071906A (ja) | 半導体装置 | |
KR101123797B1 (ko) | 적층 반도체 패키지 | |
JP3435116B2 (ja) | 半導体装置 | |
CN116936487A (zh) | 电子封装件及其制法 | |
JP2006287049A (ja) | 半導体装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AK | Designated states |
Kind code of ref document: A1 Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BW BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE EG ES FI GB GD GE GH GM HR HU ID IL IN IS KE KG KM KP KR KZ LC LK LR LS LT LU LV LY MA MD MG MK MN MW MX MZ NA NG NI NO NZ OM PG PH PL PT RO RU SC SD SE SG SK SL SM SY TJ TM TN TR TT TZ UA UG US UZ VC VN YU ZA ZM ZW |
|
AL | Designated countries for regional patents |
Kind code of ref document: A1 Designated state(s): GM KE LS MW MZ NA SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IS IT LT LU LV MC NL PL PT RO SE SI SK TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application | ||
WWE | Wipo information: entry into national phase |
Ref document number: 1020077006039 Country of ref document: KR Ref document number: 200580030969.2 Country of ref document: CN |
|
NENP | Non-entry into the national phase |
Ref country code: DE |
|
WWE | Wipo information: entry into national phase |
Ref document number: 11663856 Country of ref document: US |
|
122 | Ep: pct application non-entry in european phase |