JPH10233406A - Bonding device of ic chip - Google Patents
Bonding device of ic chipInfo
- Publication number
- JPH10233406A JPH10233406A JP9034819A JP3481997A JPH10233406A JP H10233406 A JPH10233406 A JP H10233406A JP 9034819 A JP9034819 A JP 9034819A JP 3481997 A JP3481997 A JP 3481997A JP H10233406 A JPH10233406 A JP H10233406A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- adhesive film
- circuit board
- another
- electrode pads
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
- H01L2224/83101—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/10155—Shape being other than a cuboid
- H01L2924/10158—Shape being other than a cuboid at the passive surface
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/321—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、回路素子の多数個
を形成したＩＣチップを、別のＩＣチップ又は回路基板
等に対して、これらにおける各電極パッドの相互間を電
気的に接続した状態で、ボンディング（接合）するため
の装置に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a state in which an IC chip on which a large number of circuit elements are formed is electrically connected to another IC chip or circuit board, etc., between respective electrode pads of the IC chip or circuit board. The present invention relates to a device for bonding (joining).
【０００２】[0002]
【従来の技術】従来、ＩＣチップを、別のＩＣチップ又
は回路基板等に対して、これらにおける各電極パッドの
相互間を電気的に接続した状態で、ボンディングするに
際しては、前記ＩＣチップに形成した各電極パッドと、
前記別のＩＣチップ又は回路基板等に形成した各電極パ
ッドのうちいずれか一方バンプを設けて、このバンプ
を、他方の電極パッドに対して圧着するか、両方の電極
パッドの各々にバンプを設けて、このバンプ同士を圧着
すると言う方法を採用している。2. Description of the Related Art Conventionally, when bonding an IC chip to another IC chip or a circuit board in a state where the electrode pads of the IC chip are electrically connected to each other, the IC chip is formed on the IC chip. Each of the electrode pads
One of the electrode pads formed on the another IC chip or the circuit board is provided with a bump, and the bump is pressed against the other electrode pad, or a bump is provided on each of the two electrode pads. Then, a method of press-bonding the bumps is adopted.
【０００３】[0003]
【発明が解決しようとする課題】しかし、この方法にお
いて、ＩＣチップと別のＩＣチップ又は回路基板等との
うちいずれか一方の電極パッドに設けたバンプを他方の
電極パッドに対して圧着するか、又は、一方の電極パッ
ドに設けたバンプを他方の電極パッドに設けたバンプに
対して圧着するには、比較的大きい押圧力を加えなけれ
ばならず、ＩＣチップ、及び電極パッド並びにバンプに
欠け又は割れが発生するおそれが大きいから、不良品の
発生率が高いと言う問題があった。However, in this method, the bump provided on one of the electrode pads of the IC chip and another IC chip or a circuit board is pressed against the other electrode pad. Or, in order to press the bump provided on one electrode pad against the bump provided on the other electrode pad, a relatively large pressing force must be applied, and the IC chip, the electrode pad, and the bump may be chipped. Alternatively, there is a problem that the rate of occurrence of defective products is high because cracks are likely to occur.
【０００４】本発明は、これらの問題を解消することを
技術的課題とするものである。An object of the present invention is to solve these problems.
【０００５】[0005]
【課題を解決するための手段】この技術的課題を達成す
るため本発明「請求項１」は、「ＩＣチップを、別のＩ
Ｃチップ又は回路基板の表面側に、当該ＩＣチップの片
面に形成した電極パッドを前記別のＩＣチップ又は回路
基板等に形成した電極パッドに対面して配設し、前記Ｉ
Ｃチップの各電極パッド及び前記別のＩＣチップ又は回
路基板等の各電極パッドのうちいずれか一方にパンプを
設け、前記ＩＣチップを、前記別のＩＣチップ又は回路
基板等に対して、その間に介挿した接着フィルムにて接
着する一方、前記接着フィルムに、粒径を当該接着フィ
ルムの厚さと略等しいか、大きくした導電粒子の多数個
を混入する。」と言う構成にした。In order to achieve this technical object, the present invention provides a semiconductor device comprising the steps of:
An electrode pad formed on one side of the IC chip or the circuit board is disposed on the front side of the C chip or the circuit board so as to face the electrode pad formed on the another IC chip or the circuit board.
A pump is provided on one of the electrode pads of the C chip and each of the electrode pads of the another IC chip or circuit board, and the IC chip is placed between the other IC chip or the circuit board and the like. While bonding with the interposed adhesive film, a large number of conductive particles having a particle size substantially equal to or larger than the thickness of the adhesive film are mixed into the adhesive film. ".
【０００６】また，本発明の「請求項２」は、「ＩＣチ
ップを、別のＩＣチップ又は回路基板の表面側に、当該
ＩＣチップの片面に形成した電極パッドを前記別のＩＣ
チップ又は回路基板等に形成した電極パッドに対面して
配設し、前記ＩＣチップの各電極パッド及び前記別のＩ
Ｃチップ又は回路基板等の各電極パッドのうちいずれか
一方にパンプを設け、前記ＩＣチップを、前記別のＩＣ
チップ又は回路基板等に対して、その間に介挿した接着
フィルムにて接着する一方、前記接着フィルムにこれを
貫通する小孔を多数個を穿設し、この各小孔内に、導電
粒子の粉末を互いに接触するように充填する。」と言う
構成にした。The present invention also relates to a second aspect of the present invention, wherein an IC chip is provided on another IC chip or a circuit board on the front surface side, and an electrode pad formed on one surface of the IC chip is provided on the other IC chip.
The electrode pads formed on the chip or the circuit board, etc., are disposed facing each other, and
A pump is provided on one of the electrode pads such as a C chip or a circuit board, and the IC chip is connected to the another IC.
While bonding to a chip or a circuit board with an adhesive film interposed therebetween, a large number of small holes penetrating the adhesive film are formed in the adhesive film, and in each of the small holes, conductive particles are formed. The powders are filled in contact with each other. ".
【０００７】[0007]
【発明の作用・効果】前記したように構成したことによ
り、ＩＣチップを、別のＩＣチップ又は回路基板に対し
て接着フィルムを介して強固にボンディングすることが
できると同時に、この接着フィルムに混入した導電粒
子、又は、この接着フィルムに穿設の小孔に充填した導
電粒子の粉末を介して電気的に接続できるのである。According to the structure described above, the IC chip can be firmly bonded to another IC chip or a circuit board via an adhesive film, and at the same time, the IC chip is mixed with the adhesive film. It is possible to electrically connect via the conductive particles thus formed or the powder of the conductive particles filled in the small holes formed in the adhesive film.
【０００８】このように、ＩＣチップを、別のＩＣチッ
プ又は回路基板等に対して、その間に介挿した接着フィ
ルムにて接着する場合において、前記接着フィルムに導
電粒子の粉末を混入することにより、この導電粒子の粉
末により電気的に接続することができると考えられる。
しかし、この接着フィルムに混入した導電粒子の粉末に
より電気的に接続するためには、接着フィルムをバンプ
にて圧縮変形することにより、各導電粒子が互いに接触
するようにしなければならないが、接着フィルムをバン
プにて圧縮変形するとき、これに混入されている導電粒
子が、バンプと電極パッドとの間の部分を逃げることに
なるから、電気的接続に不良が発生すると言うように、
電気的接続の確実性が低下することになる。[0008] As described above, when an IC chip is bonded to another IC chip or a circuit board with an adhesive film interposed therebetween, powder of conductive particles is mixed into the adhesive film. It is considered that the conductive particles can be electrically connected by the powder.
However, in order to electrically connect with the powder of the conductive particles mixed into the adhesive film, the conductive film must be compressed and deformed by bumps so that the conductive particles come into contact with each other. When the bumps are compressed and deformed by the bumps, the conductive particles mixed therein escape the portion between the bump and the electrode pad, so that a failure occurs in the electrical connection,
The reliability of the electrical connection will be reduced.
【０００９】これに対して、本発明のように、前記接着
フィルムに、粒径を当該接着フィルムの厚さと略等しい
か、大きくした導電粒子の多数個を混入するか、或い
は、前記接着フィルムにこれを貫通する小孔を多数個を
穿設し、この各小孔内に、導電粒子の粉末を互いに接触
するように充填すると言う構成にすると、前記接着フィ
ルムを圧縮変形することなく、粒径を接着フィルムの厚
さと略等しいか大きくした導電粒子、又は、接着フィル
ムに穿設の小孔に充填した導電粒子の粉末を介して電気
的に接続することができるのである。On the other hand, as in the present invention, a large number of conductive particles having a particle size substantially equal to or larger than the thickness of the adhesive film are mixed into the adhesive film, or By forming a large number of small holes penetrating therethrough and filling each of the small holes with the powder of the conductive particles so as to be in contact with each other, the adhesive film is not deformed by compression, and the particle size is reduced. Can be electrically connected via conductive particles having a thickness substantially equal to or larger than the thickness of the adhesive film, or powder of conductive particles filled into small holes formed in the adhesive film.
【００１０】従って、本発明によると、ＩＣチップを、
別のＩＣチップ又は回路基板等に対して、その電極パッ
ド同士を確実に電気的に接続した状態のもとで、強固に
ボンディングすることができるものでありながら、前記
ＩＣチップを、別のＩＣチップ又は回路基板に介して、
その間に接着フィルムを接着するだけで良いから、ボン
ディングの工程が簡単になり、これに要するコストを大
幅に低減できるのであり、しかも、前記の押圧は、従来
におけるパンプ接合のよりも遙かに軽いから、ＩＣチッ
プに欠け又は割れが発生することを大幅に低減できると
言う効果を有する。Therefore, according to the present invention, the IC chip is
This IC chip can be firmly bonded to another IC chip or a circuit board or the like in a state where the electrode pads are securely connected to each other. Via chip or circuit board,
In the meantime, since it is only necessary to bond the adhesive film, the bonding process is simplified, and the cost required for this can be greatly reduced, and the pressing is much lighter than the conventional pump bonding. Therefore, it is possible to significantly reduce the occurrence of chipping or cracking in the IC chip.
【００１１】[0011]
【発明の実施の形態】以下、本発明の実施の形態を図面
について説明する。図１〜図６は、第１の実施形態を示
す。この図において、符号１は、矩形状のチップマウン
ト部１ａと、このチップマウント部１ａにおける四つの
各辺から外向きに延びる複数本のリード端子１ｂとを備
えたリードフレームを示す。Embodiments of the present invention will be described below with reference to the drawings. 1 to 6 show a first embodiment. In this figure, reference numeral 1 denotes a lead frame including a rectangular chip mount 1a and a plurality of lead terminals 1b extending outward from four sides of the chip mount 1a.
【００１２】また、符号２は、前記リードフレーム１に
おけるチップマウント部１ａに対してダイボンディング
される第１ＩＣチップを示し、この第１ＩＣチップ２の
上面には、図示しない能動素子又は受動素子等のような
回路素子の多数個が形成されている共に、その周囲にワ
イヤボンディングパッド２ａの多数個が、その内側に後
述する第２ＩＣチップ３に対する接続用の電極パッド２
ｂの多数個が形成されている。また、この第１ＩＣチッ
プ２の上面には、前記各ワイヤボンディングパッド２ａ
及び各電極パッド２ｂの部分を除く部分に、絶縁性のパ
シベーション膜２ｃが形成されている。Reference numeral 2 denotes a first IC chip that is die-bonded to the chip mount portion 1a of the lead frame 1. On the upper surface of the first IC chip 2, an active element or a passive element (not shown) is mounted. A large number of such circuit elements are formed, and a large number of wire bonding pads 2a are provided around the plurality of circuit elements, and electrode pads 2 for connection to a second IC chip 3 described later are provided inside the wire bonding pads 2a.
b are formed. Also, on the upper surface of the first IC chip 2, each of the wire bonding pads 2a is provided.
In addition, an insulating passivation film 2c is formed in a portion excluding a portion of each electrode pad 2b.
【００１３】更にまた、符号３は、前記第１ＩＣチップ
２の上面にボンディングされる第２ＩＣチップを示し、
この第２ＩＣチップ３における表裏両面のうち少なくと
も片面には、前記第１ＩＣチップ２と同様に図示しない
能動素子又は受動素子等のような回路素子の多数個が形
成されている共に、前記第１ＩＣチップ２における各電
極パッド２ｂの各々に対応する箇所ごとに接続用の電極
パッド３ａが形成され、この各電極パッド３ａの各々に
は、バンプ３ａが設けられている。Further, reference numeral 3 denotes a second IC chip bonded to the upper surface of the first IC chip 2,
Like the first IC chip 2, a large number of circuit elements such as active elements or passive elements (not shown) are formed on at least one of the front and back surfaces of the second IC chip 3. 2, a connection electrode pad 3a is formed at a position corresponding to each of the electrode pads 2b, and each of the electrode pads 3a is provided with a bump 3a.
【００１４】そして、前記第２ＩＣチップ３を、その回
路素子、電極パッド３ａ及びバンプ３ｂを形成した片面
を下向きにして、前記第１ＩＣチップ２の上面側に配設
し、その間に接着フィルム４を介挿したのち、前記第２
ＩＣチップ３を、第１ＩＣチップ２に向かって、その間
における前記接着フィルム４を、第２ＩＣチップ３にお
ける各パンプ３ｂと第１ＩＣチップ２における各電極パ
ッド２ｂとで挟むように押圧し、この押圧を保持した状
態で、加熱等にて前記接着フィルム４を乾燥・硬化する
ことにより、前記第２ＩＣチップ３を、第１ＩＣチップ
２に対して、その間に介挿した接着フィルム４を介して
ボンディングするのである。The second IC chip 3 is disposed on the upper surface of the first IC chip 2 with its circuit element, the electrode pads 3a and the bumps 3b formed on one side facing downward, and an adhesive film 4 is placed between the two. After the insertion, the second
The IC chip 3 is pressed toward the first IC chip 2 so that the adhesive film 4 therebetween is sandwiched between the respective pumps 3b of the second IC chip 3 and the respective electrode pads 2b of the first IC chip 2, and this pressing is performed. The second IC chip 3 is bonded to the first IC chip 2 via the adhesive film 4 interposed therebetween by drying and curing the adhesive film 4 by heating or the like in the held state. is there.
【００１５】この場合において、前記接着フィルム４
に、粒径を当該接着フィルム４の厚さと略等しいか、大
きくした導電粒子４ａの多数個を、少なくとも一つ以上
の導電粒子４ａが前記バンプ３ｂに対して接触するよう
な密度にして混入するのであり、これにより、第２ＩＣ
チップ３における各パンプ３ｂと第１ＩＣチップ２にお
ける各電極パッド２ｂとの間には、図５に示すように、
前記接着フィルム４に混入されている導電粒子のうち少
なくとも一つ以上が挟まれることになるから、第２ＩＣ
チップ３における各電極パッド３ａと、第１ＩＣチップ
２における各電極パッド２ｂの相互間を電気的に確実に
接続することができるのである。In this case, the adhesive film 4
Then, a large number of conductive particles 4a having a particle diameter substantially equal to or larger than the thickness of the adhesive film 4 are mixed in such a density that at least one or more conductive particles 4a come into contact with the bump 3b. Therefore, the second IC
As shown in FIG. 5, between each pump 3b of the chip 3 and each electrode pad 2b of the first IC chip 2,
Since at least one or more of the conductive particles mixed in the adhesive film 4 is sandwiched, the second IC
The electrode pads 3a of the chip 3 and the electrode pads 2b of the first IC chip 2 can be reliably electrically connected to each other.
【００１６】このようにして、第１ＩＣチップ２に対し
て第２ＩＣチップ３をボンディングすると、この第１Ｉ
Ｃチップ２を、図６に示すように、前記リードフレーム
１におけるチップマウント部１ａに対してダイボンディ
ングし、次いで、この第１ＩＣチップ２における各ワイ
ヤボンディングパッド２ａと、リードフレーム１におけ
る各リード端子１ｂとの間を、細い金属線５によるワイ
ヤボンディングにて電気的に接続したのち、これらの全
体を、合成樹脂製のパッケージ体６にて密封することに
より、密封型の半導体装置とするのである。When the second IC chip 3 is bonded to the first IC chip 2 in this manner,
As shown in FIG. 6, the C chip 2 is die-bonded to the chip mounting portion 1a of the lead frame 1, and then each wire bonding pad 2a of the first IC chip 2 and each lead terminal of the lead frame 1. 1b is electrically connected by wire bonding with a thin metal wire 5 and the whole is sealed with a package 6 made of synthetic resin to obtain a sealed semiconductor device. .
【００１７】次に、図７は、第２の実施形態に使用する
接着フィルム４′を示すもので、この接着フィルム４′
には、小孔４ｂの多数個を、少なくとも一つ以上の小孔
４ｂが前記バンプ３ｂの箇所に位置するような密度で穿
設し、この各小孔４ｂ内に、導電粒子の粉末４ｃを、そ
の導電粒子が互いに接触するような密度で充填するので
ある。FIG. 7 shows an adhesive film 4 'used in the second embodiment.
, A large number of small holes 4b are drilled at a density such that at least one small hole 4b is located at the position of the bump 3b, and powder 4c of conductive particles is filled in each small hole 4b. The conductive particles are filled with such a density that they contact each other.
【００１８】これにより、前記第１の実施形態の場合に
同様に、第２ＩＣチップ３を、第１ＩＣチップ２に対し
て、接着フィルム４′を介して強固に接着できると同時
に、この接着フィルム４′の穿設の小孔４ｂ内に充填し
た導電粒子の粉末４ｃにて、第２ＩＣチップ３における
各電極パッド３ａと、第１ＩＣチップ２における各電極
パッド２ｂの相互間を電気的に確実に接続することがで
きるのである。Thus, similarly to the case of the first embodiment, the second IC chip 3 can be firmly adhered to the first IC chip 2 via the adhesive film 4 ', and at the same time, this adhesive film 4 ', Electrically conductive connection between each electrode pad 3a of the second IC chip 3 and each electrode pad 2b of the first IC chip 2 is ensured by the powder 4c of conductive particles filled in the small holes 4b formed by the' You can do it.
【００１９】なお、前記の説明は、バンプ３ｂを、第２
ＩＣチップ３における各電極パッド３ａに設けた場合で
あったが、これに代えて、バンプ３ｂを、第１ＩＣチッ
プ２における各電極パッド２ｂに設けた構成にしても良
く、また、本発明は、前記のように、ＩＣチップ３を、
別のＩＣチップ２に対してボンディングする場合に限ら
ず、ＩＣチップ３を、回路基板等に対してボンディング
する場合にも適用できることは言うまでもない。The above description is based on the assumption that the bump 3b is
In the case where the bumps 3b are provided on each electrode pad 2b of the first IC chip 2 instead of the case where the bumps 3b are provided on each electrode pad 3a of the IC chip 3, the present invention As described above, the IC chip 3
It goes without saying that the present invention can be applied not only to the case of bonding to another IC chip 2 but also to the case of bonding the IC chip 3 to a circuit board or the like.
【図１】本発明の第１の実施形態を示す分解斜視図であ
る。FIG. 1 is an exploded perspective view showing a first embodiment of the present invention.
【図２】図１の縦断正面図である。FIG. 2 is a vertical sectional front view of FIG.
【図３】図２の要部拡大図である。FIG. 3 is an enlarged view of a main part of FIG. 2;
【図４】第２ＩＣチップを第１ＩＣチップに対してボン
ディングした状態を示す縦断正面図である。FIG. 4 is a longitudinal sectional front view showing a state where a second IC chip is bonded to a first IC chip.
【図５】図４の要部拡大図である。FIG. 5 is an enlarged view of a main part of FIG. 4;
【図６】密封型半導体装置の縦断正面図である。FIG. 6 is a vertical sectional front view of the sealed semiconductor device.
【図７】本発明の第２の実施形態に使用する接着フィル
ムの要部拡大断面図である。FIG. 7 is an enlarged sectional view of a main part of an adhesive film used in a second embodiment of the present invention.
１ リードフレーム １ａ チップマウント部 １ｂ リード端子 ２ 第１ＩＣチップ ２ｂ 第１ＩＣチップの電極パッド ３ 第２ＩＣチップ ３ａ 第２ＩＣチップの電極パッド ３ｂ バンプ ４，４′ 接着フィルム ４ａ 導電粒子 ４ｂ 小孔 ４ｃ 導電粒子の粉末 DESCRIPTION OF SYMBOLS 1 Lead frame 1a Chip mount part 1b Lead terminal 2 1st IC chip 2b 1st IC chip electrode pad 3 2nd IC chip 3a 2nd IC chip electrode pad 3b Bump 4,4 'Adhesive film 4a Conductive particle 4b Small hole 4c Conductive particle Powder
Claims (2)
板の表面側に、当該ＩＣチップの片面に形成した電極パ
ッドを前記別のＩＣチップ又は回路基板等に形成した電
極パッドに対面して配設し、前記ＩＣチップの各電極パ
ッド及び前記別のＩＣチップ又は回路基板等の各電極パ
ッドのうちいずれか一方にパンプを設け、前記ＩＣチッ
プを、前記別のＩＣチップ又は回路基板等に対して、そ
の間に介挿した接着フィルムにて接着する一方、前記接
着フィルムに、粒径を当該接着フィルムの厚さと略等し
いか、大きくした導電粒子の多数個を混入したことを特
徴とするＩＣチップのボンディング装置。1. An IC chip having an electrode pad formed on one surface of another IC chip or circuit board facing an electrode pad formed on another IC chip or circuit board or the like. A pump is provided on one of the electrode pads of the IC chip and the electrode pads of the another IC chip or the circuit board, and the IC chip is mounted on the another IC chip or the circuit board. On the other hand, an IC characterized in that a large number of conductive particles having a particle diameter substantially equal to or larger than the thickness of the adhesive film are mixed into the adhesive film while adhering with an adhesive film interposed therebetween. Chip bonding equipment.
板の表面側に、当該ＩＣチップの片面に形成した電極パ
ッドを前記別のＩＣチップ又は回路基板等に形成した電
極パッドに対面して配設し、前記ＩＣチップの各電極パ
ッド及び前記別のＩＣチップ又は回路基板等の各電極パ
ッドのうちいずれか一方にパンプを設け、前記ＩＣチッ
プを、前記別のＩＣチップ又は回路基板等に対して、そ
の間に介挿した接着フィルムにて接着する一方、前記接
着フィルムにこれを貫通する小孔を多数個を穿設し、こ
の各小孔内に、導電粒子の粉末を互いに接触するように
充填したことを特徴とするＩＣチップのボンディング装
置。2. An IC chip having an electrode pad formed on one surface of another IC chip or a circuit board facing an electrode pad formed on another IC chip or a circuit board or the like. A pump is provided on one of the electrode pads of the IC chip and the electrode pads of the another IC chip or the circuit board, and the IC chip is mounted on the another IC chip or the circuit board. On the other hand, while adhering with an adhesive film interposed therebetween, a large number of small holes penetrating the adhesive film are formed in the adhesive film, and powder of conductive particles is brought into contact with each other in each of the small holes. A bonding apparatus for an IC chip, wherein the bonding apparatus is filled with an IC chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP03481997A JP3696360B2 (en) | 1997-02-19 | 1997-02-19 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP03481997A JP3696360B2 (en) | 1997-02-19 | 1997-02-19 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH10233406A true JPH10233406A (en) | 1998-09-02 |
| JP3696360B2 JP3696360B2 (en) | 2005-09-14 |
Family
ID=12424821
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP03481997A Expired - Fee Related JP3696360B2 (en) | 1997-02-19 | 1997-02-19 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3696360B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002093855A (en) * | 2000-09-18 | 2002-03-29 | Toshiba Corp | Semiconductor device |
| CN113937010A (en) * | 2021-12-16 | 2022-01-14 | 绍兴中芯集成电路制造股份有限公司 | Method for manufacturing semiconductor device |
-
1997
- 1997-02-19 JP JP03481997A patent/JP3696360B2/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002093855A (en) * | 2000-09-18 | 2002-03-29 | Toshiba Corp | Semiconductor device |
| CN113937010A (en) * | 2021-12-16 | 2022-01-14 | 绍兴中芯集成电路制造股份有限公司 | Method for manufacturing semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3696360B2 (en) | 2005-09-14 |
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