JP2000223634A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JP2000223634A
JP2000223634A JP1943199A JP1943199A JP2000223634A JP 2000223634 A JP2000223634 A JP 2000223634A JP 1943199 A JP1943199 A JP 1943199A JP 1943199 A JP1943199 A JP 1943199A JP 2000223634 A JP2000223634 A JP 2000223634A
Authority
JP
Japan
Prior art keywords
electrode
metal
metal member
semiconductor
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1943199A
Other languages
Japanese (ja)
Other versions
JP4260263B2 (en
Inventor
Ryoichi Kajiwara
良一 梶原
Masahiro Koizumi
正博 小泉
Toshiaki Morita
俊章 守田
Kazuya Takahashi
和弥 高橋
Munehisa Kishimoto
宗久 岸本
Shigeru Ishii
滋 石井
Toshinori Hirashima
利宣 平島
Yasushi Takahashi
靖司 高橋
Toshiyuki Namita
俊幸 波多
Hitohisa Sato
仁久 佐藤
Keiichi Okawa
啓一 大川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Renesas Eastern Japan Semiconductor Inc
Original Assignee
Hitachi Ltd
Hitachi Tohbu Semiconductor Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Hitachi Tohbu Semiconductor Ltd filed Critical Hitachi Ltd
Priority to JP01943199A priority Critical patent/JP4260263B2/en
Priority to KR1020000003672A priority patent/KR20000057810A/en
Priority to DE10003671A priority patent/DE10003671A1/en
Priority to US09/493,080 priority patent/US6774466B1/en
Publication of JP2000223634A publication Critical patent/JP2000223634A/en
Priority to US10/758,396 priority patent/US20040150082A1/en
Priority to US10/855,432 priority patent/US20040217474A1/en
Priority to US11/415,291 priority patent/US7332757B2/en
Priority to US11/415,290 priority patent/US7342267B2/en
Priority to US11/543,030 priority patent/US20070029540A1/en
Priority to US11/589,895 priority patent/US20070040250A1/en
Priority to US11/589,847 priority patent/US7400002B2/en
Priority to US11/589,849 priority patent/US7394146B2/en
Priority to US12/046,741 priority patent/US7985991B2/en
Application granted granted Critical
Publication of JP4260263B2 publication Critical patent/JP4260263B2/en
Priority to US13/189,883 priority patent/US8183607B2/en
Priority to US13/459,839 priority patent/US8455986B2/en
Priority to US13/906,771 priority patent/US8816411B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

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    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device having a package structure capable of reducing the mounting resistance. SOLUTION: First metal members (lead terminals 5, 6) are connected to a first electrode (a source electrode 2) of a semiconductor element (a semiconductor chip 1) via first metal bodies (Au bumps 8) including a noble metal, and a second metal member (a die terminal 7) is connected to a second electrode (a rear electrode 4) via second metal bodies (plated with noble metal 14 and Ag 15). Thereby, a drastic decrease in the mounting resistance such as 1 mΩ or lower can be achieved.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、半導体装置に係
り、特に実装抵抗の低減に好適な半導体パッケージ構造
に関する。The present invention relates to a semiconductor device, and more particularly to a semiconductor package structure suitable for reducing mounting resistance.

【０００２】[0002]

【従来の技術】従来のトランジスタパッケージの一例と
して、特開平8−64634号公報に開示されているものがあ
る。熱放散用のヘッダに電子回路が形成された半導体チ
ップが裏面電極側で半田により接合されている。チップ
の回路形成面側のＡｌ電極には、バンプが形成され、イ
ンナーリードが電気的及び機械的に接続されている。ま
た、ヘッダにもインナーリードが接続され、チップ及び
ヘッダとリードの一部を覆うように樹脂で封止されてい
る。このとき、バンプが半田の場合はリード側に錫（Ｓ
ｎ），金（Ａｕ），半田等をめっきしてバンプの半田を
溶融して接合し、バンプがＡｕの場合にはリード側に錫
をめっきしてＡｕ−Ｓｎ共晶反応によって接合してい
る。インナーリードは、ソース電極，ドレイン電極，ゲ
ート電極用の３本で構成され、ソース電極用リードは櫛
歯形状に加工されている。ヘッダには、樹脂まで貫通す
る開口部が形成されている。2. Description of the Related Art An example of a conventional transistor package is disclosed in Japanese Patent Application Laid-Open No. 8-64634. A semiconductor chip having an electronic circuit formed on a heat dissipation header is joined by solder on the back electrode side. Bumps are formed on the Al electrodes on the circuit forming surface side of the chip, and inner leads are electrically and mechanically connected. An inner lead is also connected to the header, and is sealed with resin so as to cover a part of the chip, the header, and the lead. At this time, if the bump is solder, tin (S
n), gold (Au), solder or the like is plated to melt the solder of the bumps and joined. If the bumps are Au, tin is plated on the lead side and joined by an Au-Sn eutectic reaction. . The inner lead is composed of three lines for a source electrode, a drain electrode and a gate electrode, and the source electrode lead is processed into a comb shape. An opening is formed in the header to penetrate the resin.

【０００３】他の従来例として、特開平5−121615 号公
報に開示されているワイヤレス構造の表面実装型半導体
パッケージがある。３つの外部接続端子が半導体チップ
の電極端子に接続されている。チップ上面の２つの電極
と外部接続端子はＡｕボールを熱圧着することにより接
続されている。配線基板への実装は、チップ搭載部から
前後に導出されたリード端子の先端領域を基板の端子に
半田付けして行われる。As another conventional example, there is a surface-mount type semiconductor package having a wireless structure disclosed in Japanese Patent Application Laid-Open No. 5-121615. Three external connection terminals are connected to the electrode terminals of the semiconductor chip. The two electrodes on the upper surface of the chip and the external connection terminals are connected by thermocompression bonding of an Au ball. The mounting on the wiring board is performed by soldering the tip end regions of the lead terminals led back and forth from the chip mounting portion to the terminals of the board.

【０００４】また、従来の標準的な表面実装型半導体パ
ッケージにおいては、ドレイン用リードのヘッダに半導
体チップが半田により接着され、半導体チップのソース
及びゲート電極と外部接続端子のソース及びゲート用リ
ード間がＡｌワイヤのボンディングにより結線されてい
る。チップ及び各リードとヘッダの一部が樹脂でモール
ドされている。樹脂パッケージの底面にヘッダが露出し
て配線基板に接続可能な構造となっており、その大きさ
は樹脂モールドのサイズより大きく設定されている。In a conventional standard surface mount type semiconductor package, a semiconductor chip is bonded to a header of a drain lead by soldering, and a source and a gate electrode of the semiconductor chip and a source and a gate lead of an external connection terminal are connected. Are connected by bonding of Al wires. A part of the chip, each lead and the header is molded with resin. The header is exposed at the bottom surface of the resin package so that the header can be connected to the wiring board, and the size is set to be larger than the size of the resin mold.

【０００５】また、半導体チップの従来のチップ・ダイ
接続構造においては、Ｃｕ基合金の部材にチップを固着
したときチップに高い応力を発生させないために、降伏
強度の低いＰｂリッチな半田やＡｇ粒子を混入した導電
性樹脂による接着構造が採用されていた。In a conventional chip-die connection structure of a semiconductor chip, when a chip is fixed to a Cu-based alloy member, high stress is not generated in the chip, so that Pb-rich solder or Ag particles having low yield strength are used. In this case, an adhesive structure made of a conductive resin mixed with is used.

【０００６】[0006]

【発明が解決しようとする課題】従来の縦型半導体素子
の表面実装型プラスチックパッケージにおけるパッケー
ジの実装抵抗は、ワイヤボンディング構造で数十〜十数
ｍΩであった。半導体技術の進歩により、素子のオン抵
抗が年々減少し、現状は数十〜数ｍΩ／cm2 のデバイス
が開発されつつあり、将来はさらに低抵抗化が進められ
ると予測される。その場合、実装抵抗がデバイス抵抗よ
り大きくなるため、半導体パッケージの性能向上を図る
ためには、実装抵抗の低減が不可欠となる。この半導体
パッケージのオン抵抗に着眼した公知例が上記特開平8
−64634号公報に開示されているが、この公知例は挿入
実装型パッケージで提案されている。挿入実装型は、パ
ッケージサイズに制約がなく、しかも基板とリードの接
合が構造的に強固であるため、厚肉で大型サイズのヘッ
ダを使用でき、リードも厚肉のものを使用できる。この
ため、実装抵抗の低減は比較的容易である。しかし、表
面実装型パッケージは、樹脂匡体の両サイドから導出さ
れたリードが、その先端部で基板の端子と小さい面積の
面同士で半田接続される構造であるため、挿入実装型に
比べて接合部の疲労強度が弱いという性質がある。この
ため、チップの発熱に伴うパッケージと基板間の熱歪み
を柔軟なリードの変形によって吸収することが必要であ
り、リードの形状を薄肉で細長い形状とすることが必要
である。この場合には、リード部分の電気抵抗が大きく
なるため、実装抵抗の低減は困難である。The package mounting resistance of a conventional surface-mount type plastic package of a vertical semiconductor device is several tens to several tens of mΩ in a wire bonding structure. With advances in semiconductor technology, the on-resistance of elements has been decreasing year by year, and currently, devices of several tens to several mΩ / cm 2 are being developed, and it is expected that the resistance will be further reduced in the future. In this case, since the mounting resistance is higher than the device resistance, it is essential to reduce the mounting resistance in order to improve the performance of the semiconductor package. A known example focusing on the on-resistance of the semiconductor package is disclosed in
As disclosed in JP-A-64634, this known example is proposed as an insertion mounting type package. In the insertion mounting type, there is no restriction on the package size, and since the connection between the substrate and the leads is structurally strong, a thick and large-sized header can be used, and a thick lead can be used. Therefore, it is relatively easy to reduce the mounting resistance. However, the surface mount type package has a structure in which the leads led out from both sides of the resin housing are soldered to the terminals of the board at the tip end with a small surface area, so it is compared to the insert mount type. There is a property that the fatigue strength of the joint is weak. For this reason, it is necessary to absorb the thermal distortion between the package and the substrate due to the heat generation of the chip by the deformation of the flexible leads, and it is necessary to make the leads thin and elongated. In this case, it is difficult to reduce the mounting resistance because the electrical resistance of the lead portion increases.

【０００７】表面実装型の場合、チップを搭載したヘッ
ダを直接配線基板に半田付けする構造にすれば、この問
題はなくなる。しかし、チップ上面の電極に接続される
リードを樹脂匡体からの導出する位置と、ヘッダを導出
する位置が高さの点で異なる場合、樹脂をモールドする
上下金型の合わせ面が３次元構造となり、金型の加工が
難しくなるという問題がある。この問題は、特にリード
フレームが、パッケージの多数個取りを目的としたマト
リックスフレーム（Ｘ，Ｙ方向に配置）の場合に顕著と
なる。ヘッダを小さくして樹脂匡体内に納めればこの問
題はなくなるが、そうすると、ヘッダを樹脂匡体の下面
に露出させるためにヘッダをモールド金型の底面に押し
付けるための加圧場所をモールド内部に設ける必要があ
る。ヘッダが大きい場合はヘッダの開口部を利用して押
し付けることが可能だが、ヘッダがチップと同等サイズ
の場合にはヘッダ部に押し付ける場所がなく、ヘッダを
下面に露出させてモールドすることが難しくなるという
問題がある。このため、ヘッダがチップと同等サイズの
小型の半導体パッケージの場合には、裏面電極の外部接
続端子を兼ねるヘッダを樹脂匡体内に納めた構造で組み
立てることが技術的に困難である。[0007] In the case of the surface mount type, this problem can be eliminated by adopting a structure in which the header on which the chip is mounted is directly soldered to the wiring board. However, if the position at which the leads connected to the electrodes on the top surface of the chip are led out of the resin housing is different from the position at which the header is led out in terms of height, the mating surfaces of the upper and lower molds for molding the resin have a three-dimensional structure. Therefore, there is a problem that machining of the mold becomes difficult. This problem is particularly remarkable when the lead frame is a matrix frame (arranged in the X and Y directions) for the purpose of obtaining a large number of packages. This problem can be solved by reducing the size of the header and placing it inside the resin housing.However, in this case, there is a pressurized place inside the mold to press the header against the bottom of the mold to expose the header to the lower surface of the resin housing. Must be provided. If the header is large, it can be pressed using the opening of the header, but if the header is the same size as the chip, there is no place to press on the header, making it difficult to expose the header on the lower surface and mold it There is a problem. For this reason, when the header is a small semiconductor package having the same size as the chip, it is technically difficult to assemble the header in the resin housing, which also serves as the external connection terminal of the back electrode.

【０００８】一方、従来において、チップ裏面とヘッダ
やダイ等の外部接続端子との接続は、半田接続かあるい
は導電性樹脂による接着構造が採用されてきた。半田接
続は、電気抵抗や熱抵抗及び耐熱信頼性に優れた接続構
造であるが、近年の環境問題の観点からＰｂレス化が要
求されており、従来のＰｂ入半田から新たなＰｂレス接
合材料に変える必要が生じている。しかし、固相温度が
２５０℃以下のＰｂレス半田材料は種々あるものの、パ
ッケージの基板への搭載に耐えるような固相温度２７０
℃以上を持つ適当なＰｂレス半田材料はないのが実情で
ある。唯一、固相温度３７０℃のＡｕ−Ｓｉ半田がある
が、この半田は、コストが高いこと、降伏強度が高いた
めチップサイズが大きい場合は半田付け後の冷却過程で
チップが割れてしまうという２つの理由によってチップ
裏面電極用半田材として採用困難である。すなわち、現
状、Ｐｂレスの代替半田材がないという問題がある。一
方、導電性樹脂による接着は、耐熱的には短時間であれ
ば実装に必要な２７０℃に耐えることができるが、接着
強度が樹脂で保たれているため強度的に弱く、モールド
樹脂の硬化収縮力で密着を補強しているものの、大面積
のチップや高温で使用されるパッケージでは、経年変化
や温度サイクルによる樹脂の劣化によって接合部の電気
抵抗や熱抵抗が増加するという問題がある。特に、ヘッ
ダやダイ（外部接続端子）が樹脂匡体の表面に露出して
いる片面モールド構造では、チップ裏面にモールド樹脂
による押し付け力が得られない構造となるため、導電性
樹脂接着部の長期信頼性がさらに低くなるという問題が
ある。On the other hand, conventionally, the connection between the back surface of the chip and external connection terminals such as a header and a die has been made by solder connection or an adhesive structure using a conductive resin. Although the solder connection has a connection structure excellent in electric resistance, heat resistance and heat resistance reliability, Pb-free is required from the viewpoint of environmental problems in recent years, and a new Pb-less joining material is used instead of the conventional Pb-containing solder. Needs to be changed. However, although there are various Pb-less solder materials having a solidus temperature of 250 ° C. or less, the solidus temperature 270 which can withstand the mounting of the package on the substrate is used.
In fact, there is no suitable Pb-less solder material having a temperature of ℃ or more. There is only an Au-Si solder having a solid phase temperature of 370 ° C., but this solder is expensive and has a high yield strength. If the chip size is large, the chip will break during the cooling process after soldering. For these reasons, it is difficult to adopt it as a solder material for a chip back surface electrode. That is, there is a problem that there is no Pb-less alternative solder material at present. On the other hand, bonding with a conductive resin can withstand 270 ° C. required for mounting for a short time in terms of heat resistance. However, since the bonding strength is maintained by the resin, the bonding strength is weak, and the curing of the molding resin is difficult. Although the adhesion is reinforced by the shrinkage force, the large-area chip and the package used at a high temperature have a problem that the electrical resistance and the thermal resistance of the joint increase due to deterioration of the resin due to aging and temperature cycling. In particular, in a single-sided mold structure in which the header and die (external connection terminals) are exposed on the surface of the resin housing, the pressing force of the molding resin cannot be obtained on the back surface of the chip, so that the conductive resin bonding portion has a long term. There is a problem that reliability is further reduced.

【０００９】本発明は、上記の問題点を考慮してなされ
たものであり、実装抵抗の低減が可能なパッケージ構造
を有する半導体装置を提供する。The present invention has been made in consideration of the above problems, and provides a semiconductor device having a package structure capable of reducing mounting resistance.

【００１０】[0010]

【課題を解決するための手段】本発明による半導体装置
は、まず、半導体基板と、半導体基板の表面に設けられ
る第１の電極と、半導体基板の裏面に設けられる第２の
電極とを有する半導体素子を備える。さらに、第１の金
属部材が、第１の貴金属を含む第１の金属体を介して、
半導体素子の第１の電極と接続され、かつ、第２の金属
部材が、第２の貴金属を含む第２の金属体を介して、第
２の電極と接続される。A semiconductor device according to the present invention comprises a semiconductor device having a semiconductor substrate, a first electrode provided on the front surface of the semiconductor substrate, and a second electrode provided on the back surface of the semiconductor substrate. Device. Further, the first metal member is provided via a first metal body including the first noble metal,
The second metal member is connected to the first electrode of the semiconductor element, and the second metal member is connected to the second electrode via the second metal body including the second noble metal.

【００１１】本発明によれば、第１及び第２の金属部材
が、それぞれ貴金属を含む金属体を介して半導体素子の
電極と接続されるので、半導体パッケージの実装抵抗を
低減することができる。According to the present invention, since the first and second metal members are connected to the electrodes of the semiconductor element via the metal bodies each containing a noble metal, the mounting resistance of the semiconductor package can be reduced.

【００１２】上記の構成において、好ましくは、外部配
線と接続するための第１の金属部材の表面部分及び第２
の金属部材の表面部分を略同じ平面内に位置させる。こ
こで、略同じ平面とは、例えば、各種電子装置における
配線基板や回路基板の電子部品取り付け面である。これ
により、半導体装置を、配線基板や回路基板などに、面
実装することができる。In the above configuration, preferably, the surface portion of the first metal member and the second metal member for connection to the external wiring are provided.
The surface portion of the metal member is located in substantially the same plane. Here, the substantially same plane is, for example, an electronic component mounting surface of a wiring board or a circuit board in various electronic devices. Thus, the semiconductor device can be surface-mounted on a wiring board, a circuit board, or the like.

【００１３】第１の金属体としては、半導体素子の第１
の電極または第１の金属部材から突出する突起状電極が
ある。突起状電極としては、金（Ａｕ）または銀（Ａ
ｇ）などの貴金属のバンプ電極やボール状電極などが適
用できる。さらに、実装抵抗を低減するために好ましく
は、複数の突起状電極を、第１の電極と前記第１の金属
部材との接合界面の略全面において、略等間隔に配列す
る。The first metal body may be a first metal body.
Or a protruding electrode protruding from the first metal member. As the protruding electrodes, gold (Au) or silver (A
g) and other noble metal bump electrodes and ball-shaped electrodes. Further, in order to reduce the mounting resistance, preferably, the plurality of protruding electrodes are arranged at substantially equal intervals over substantially the entire bonding interface between the first electrode and the first metal member.

【００１４】第２の金属体としては、第２の電極と第２
の金属部材との接合界面に位置する金属層がある。好ま
しくは、金属層を、第２の電極の接合表面側及び第２の
金属部材の接合表面側に位置する各貴金属層が互いに接
合したものとする。貴金属層の材料としては、金（Ａ
ｕ），銀（Ａｇ），白金（Ｐｔ），パラジウム（Ｐｄ）
などから選択される貴金属、あるいはそれを最も多く含
む主成分とする合金が適用できる。また、複数種の貴金
属層あるいは合金層が多層化されていても良い。さら
に、第２の電極側に位置する貴金属層と、第２の金属部
材側に位置する貴金属層との間に、金（Ａｕ）または銀
（Ａｇ）などの貴金属のバンプ電極やボール状電極，樹
脂と混合された銀（Ａｇ）粒子，板状またはシート状あ
るいは網目状の銀(Ａｇ)部材，凹凸あるいは空隙部を有
する板状あるいはシート状の銀部材のいずれかが介在し
ても良い。好ましい他の金属層としては、貴金属を主成
分とする固相温度４００℃以上の合金層がある。このよ
うな合金層としては、銀(Ａｇ)を主成分とする銀（Ａ
ｇ）と錫（Ｓｎ）との合金を適用できる。The second metal member includes a second electrode and a second electrode.
There is a metal layer located at the bonding interface with the metal member. Preferably, the noble metal layers located on the bonding surface side of the second electrode and the bonding surface side of the second metal member are bonded to each other. As a material of the noble metal layer, gold (A
u), silver (Ag), platinum (Pt), palladium (Pd)
For example, a noble metal selected from the group consisting of a noble metal and an alloy containing the most noble metal as a main component can be used. Further, a plurality of types of noble metal layers or alloy layers may be multilayered. Further, a noble metal bump electrode or a ball-shaped electrode such as gold (Au) or silver (Ag) is provided between the noble metal layer located on the second electrode side and the noble metal layer located on the second metal member side. Any of silver (Ag) particles mixed with a resin, a plate-shaped or sheet-shaped or mesh-shaped silver (Ag) member, and a plate-shaped or sheet-shaped silver member having irregularities or voids may be interposed. As another preferable metal layer, there is an alloy layer containing a noble metal as a main component and having a solid phase temperature of 400 ° C. or higher. As such an alloy layer, silver (A) containing silver (Ag) as a main component is used.
An alloy of g) and tin (Sn) can be applied.

【００１５】半導体素子の第１及び第２の電極、並びに
第１及び第２の金属部材においては、これらの接合表面
に貴金属層を設けても良い。この貴金属層の材料として
は、金（Ａｕ），銀（Ａｇ），白金（Ｐｔ），パラジウ
ム（Ｐｄ）などから選択される貴金属、あるいはそれを
最も多く含む主成分とする合金が適用できる。半導体素
子における第１及び第２の電極の材料としては、アルミ
ニウム、またはアルミシリコンのようなアルミニウム合
金が適用できる。In the first and second electrodes of the semiconductor element and the first and second metal members, a noble metal layer may be provided on the joint surface thereof. As a material of the noble metal layer, a noble metal selected from gold (Au), silver (Ag), platinum (Pt), palladium (Pd), or the like, or an alloy containing a major component of the noble metal can be used. As a material of the first and second electrodes in the semiconductor element, aluminum or an aluminum alloy such as aluminum silicon can be used.

【００１６】また、第１及び第２の金属部材は、半導体
素子の第１及び第２の電極を外部の電極，配線基板，回
路基板などと電気的に接続する。例えば、第１及び第２
の金属部材は、半導体パッケージの一部であるリード
線，リード電極、またはダイ端子など、あるいはこれら
の一部である。そして、実装抵抗を低減するために好ま
しくは、第１の金属部材が、第１の電極との接合部を有
する部分から延びる複数の部分を有し、この複数の部分
の各々が、外部配線と接続するための表面部分を有する
構成とする。このような半導体装置が接続される回路基
板または配線基板においては、第１の金属部材における
上記のような各表面部分毎に、電気的接続のための導体
部（例えば銅箔）が設けられ、かつこれらの導体部は、
回路基板上または配線基板上で電気的に接続されてい
る。例えば、このような導体部としては、プリント基板
における、連続した導体（例えば銅）パターンが適用で
きる。上述したような、本発明による半導体装置の構成
は、いわゆる樹脂封止型または樹脂モールド型の半導体
装置のように、半導体素子と第１及び第２の金属部材と
が絶縁体によって被覆される半導体装置にも実施でき
る。この場合、第１の金属部材における第１の電極との
接合面の裏面が、外部配線と接続するための露出部分を
有することが好ましい。このような構成に加え、半導体
素子の接合面側を回路形成面（たとえば縦型半導体スイ
ッチング素子の一方の主電流電極と制御電極が形成され
ている面）とし、第１の電極を主電流電極とすると良
い。なお、半導体素子と第１及び第２の金属部材とが絶
縁体によって被覆される半導体装置においては、第２の
金属部材における第２の電極との接合面の裏面が、外部
配線と接続するための露出部分を有していても良い。な
お、絶縁体の材料としては、各種樹脂の他、セラミック
スなどの他の絶縁性材料も適用できる。The first and second metal members electrically connect the first and second electrodes of the semiconductor element to external electrodes, a wiring board, a circuit board, and the like. For example, the first and second
Is a lead wire, a lead electrode, a die terminal, or the like which is a part of a semiconductor package, or a part thereof. Then, in order to reduce the mounting resistance, preferably, the first metal member has a plurality of portions extending from a portion having a joint with the first electrode, and each of the plurality of portions is connected to an external wiring. It has a surface portion for connection. In a circuit board or a wiring board to which such a semiconductor device is connected, a conductor portion (for example, a copper foil) for electrical connection is provided for each surface portion of the first metal member as described above, And these conductors are
They are electrically connected on a circuit board or a wiring board. For example, as such a conductor, a continuous conductor (for example, copper) pattern on a printed circuit board can be applied. As described above, the configuration of the semiconductor device according to the present invention is such that the semiconductor element and the first and second metal members are covered with an insulator like a so-called resin-sealed or resin-molded semiconductor device. It can be implemented in an apparatus. In this case, it is preferable that the back surface of the bonding surface of the first metal member with the first electrode has an exposed portion for connecting to an external wiring. In addition to such a configuration, the bonding surface side of the semiconductor element is a circuit forming surface (for example, a surface on which one main current electrode and a control electrode of a vertical semiconductor switching element are formed), and the first electrode is a main current electrode. It is good to In a semiconductor device in which the semiconductor element and the first and second metal members are covered with an insulator, the back surface of the bonding surface of the second metal member with the second electrode is connected to an external wiring. May be exposed. As a material of the insulator, other insulating materials such as ceramics can be applied in addition to various resins.

【００１７】上述した各構成は、適宜併用することがで
きる。また、次に述べる本発明による他の半導体装置の
ように、単独でも実装抵抗を低減する作用・効果を有す
る構成もある。The components described above can be used in combination as appropriate. Also, there is a configuration having an action and an effect of reducing the mounting resistance by itself, as in another semiconductor device according to the present invention described below.

【００１８】すなわち、本発明による他の半導体装置と
しては、半導体基板の表面及び裏面にそれぞれ第１の電
極及び第２の電極とを有する半導体素子が収納される半
導体パッケージにおいて、上述したような、１）第２の
電極と第２の金属部材とが、第２の電極の接合表面及び
前記第２の金属部材の接合表面に設けられる貴金属層が
互いに接合した金属層を介して接合される構成、２）第
２の電極と前記第２の金属部材とが、貴金属を主成分と
する固相温度４００℃以上の合金層を介して接合される
構成、３）第１の金属部材が、第１の電極との接合部か
ら延びる複数の部分を有し、複数の部分の各々が、外部
配線と接続するための表面部分を有する構成、のいずれ
かを実施したものがある。また、１）または２）の構成
と、３）の構成を併せて実施しても良い。That is, another semiconductor device according to the present invention is a semiconductor package in which a semiconductor element having a first electrode and a second electrode on the front and back surfaces of a semiconductor substrate is housed as described above. 1) A structure in which a second electrode and a second metal member are joined via a metal layer in which a joining surface of the second electrode and a noble metal layer provided on a joining surface of the second metal member are joined to each other. 2) a structure in which the second electrode and the second metal member are joined via an alloy layer containing a noble metal as a main component and having a solid phase temperature of 400 ° C. or higher; There is a configuration in which a plurality of portions extending from a joint portion with one electrode are provided, and each of the plurality of portions has a surface portion for connecting to an external wiring. Further, the configuration of 1) or 2) and the configuration of 3) may be implemented together.

【００１９】上述した本発明による各半導体装置は、Ｍ
ＯＳ（Metal Oxide Semiconductor)電界効果トランジス
タ，ＭＩＳ(Metal Insulator Semiconductor）電界効果
トランジスタ，バイポーラトランジスタ，絶縁ゲートバ
イポーラトランジスタ，ダイオード、あるいは集積回路
などの各種の半導体素子に適用できる。また、本発明に
よる各半導体装置の構成は、第１及び第２の電極を一対
の主電流電極とする半導体素子、並びに第１及び第２の
電極を主電流電極とし、主電流が、表面側の第１の電極
から裏面側の第２の電極へ向かう方向あるいはその逆方
向に向かって、半導体基板中を縦方向に流れる、パワー
ＭＯＳＦＥＴやパワートランジスタのような縦型半導体
素子に好適である。この場合、半導体素子の低オン抵抗
特性とあいまって、パッケージを含めた端子間のオン抵
抗またはオン電圧を低減できる。Each of the semiconductor devices according to the present invention described above has M
The present invention can be applied to various semiconductor elements such as an OS (Metal Oxide Semiconductor) field effect transistor, a MIS (Metal Insulator Semiconductor) field effect transistor, a bipolar transistor, an insulated gate bipolar transistor, a diode, and an integrated circuit. Further, the configuration of each semiconductor device according to the present invention includes a semiconductor element in which the first and second electrodes are a pair of main current electrodes, and a semiconductor device in which the first and second electrodes are main current electrodes, and the main current is on the front side. It is suitable for a vertical semiconductor device such as a power MOSFET or a power transistor, which flows vertically through a semiconductor substrate in a direction from the first electrode toward the second electrode on the back surface side or the reverse direction. In this case, the on-resistance or on-voltage between terminals including the package can be reduced in combination with the low on-resistance characteristic of the semiconductor element.

【００２０】[0020]

【発明の実施の形態】第１の一実施形態は、トランジス
タチップのゲート電極及びソース電極と外部接続用金属
部材（リード）間の接続を最適に配置した複数のＡｕバ
ンプを介して直接接合し、チップ裏面のドレイン電極と
外部接続用金属部材（ダイ）を電気的及び熱的に結合
し、ソース電極及びゲート電極用金属部材（リード）ま
たはドレイン電極用金属部材（ダイ）のいずれか一方が
多面体のパッケージの内部に納まる構造とし、パッケー
ジ内に納めた金属部材の面を配線基板の端子面に半田接
合できる構造としたものである。さらに好ましくは、パ
ッケージから導出するリードまたはダイの導出部をパッ
ケージの側面２面からとる構造とし、パッケージ内部に
納めた金属部材をモールド金型の底面に押し付ける方法
を、パッケージから導出した金属部材を介して行える構
造とする。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In a first embodiment, the connection between a gate electrode and a source electrode of a transistor chip and a metal member (lead) for external connection is directly joined via a plurality of Au bumps optimally arranged. The drain electrode on the back surface of the chip and the external connection metal member (die) are electrically and thermally coupled, and one of the source electrode and gate electrode metal member (lead) or the drain electrode metal member (die) is connected. The structure is such that it is housed inside a polyhedral package, and the surface of the metal member housed in the package can be soldered to the terminal surface of the wiring board. More preferably, a lead or die lead-out portion derived from the package is formed from two side surfaces of the package, and a method of pressing a metal member housed inside the package against the bottom surface of a mold is described in the following. And a structure that can be performed through

【００２１】また、第２の実施形態は、ドレイン電極と
貴金属めっきを施した金属部材（ダイ）とを貴金属バン
プあるいは貴金属のメッシュシートあるいは貴金属粒子
あるいは硬さ３５Ｈｖ以下の厚い貴金属めっきを介して
直接あるいは貴金属を主成分とする固相温度４００℃以
上の合金層を介して接合した構造である。この接合部
は、加熱と超音波振動を用いた圧接で得ることができ
る。さらに好ましくは、チップサイズが大きい場合に、
チップ上回路形成面のソース電極とゲート電極にＡｕバ
ンプを形成し、貴金属めっきを施したリードとを直接接
合する構造とし、さらにソース電極側のリードとチップ
裏面のダイの大きさを同等としてチップに曲げ応力がか
からないように部材を対称形に配置した構造とする。In the second embodiment, the drain electrode and the metal member (die) plated with the noble metal are directly connected via a noble metal bump, a noble metal mesh sheet, a noble metal particle, or a thick noble metal plating having a hardness of 35 Hv or less. Alternatively, the structure is such that bonding is performed via an alloy layer containing a noble metal as a main component and having a solid phase temperature of 400 ° C. or higher. This joint can be obtained by pressure welding using heating and ultrasonic vibration. More preferably, when the chip size is large,
Au bumps are formed on the source and gate electrodes on the circuit formation surface on the chip, and the noble metal-plated leads are directly joined. The leads on the source electrode and the die on the back of the chip are made equal in size The members are arranged symmetrically so that no bending stress is applied to them.

【００２２】また、第３の実施形態は、チップ上面のソ
ース及びゲートＡｌ電極上に予めＡｕバンプを多数形成
し、貴金属めっきした各リードに位置合わせしてチップ
を搭載し、その上にＡｕバンプより硬さの小さい貴金属
部材、さらにその上に貴金属めっきしたダイを搭載し、
ダイの上に加圧と超音波振動を加える接合ツールを配置
して、加熱と荷重と超音波により各接合界面を一括して
接合する構造及び方法とした。In the third embodiment, a large number of Au bumps are previously formed on the source and gate Al electrodes on the upper surface of the chip, the chip is mounted in alignment with each of the noble metal plated leads, and the Au bump is formed thereon. A noble metal member with a smaller hardness, and a die plated with a noble metal on it,
A bonding tool for applying pressure and ultrasonic vibration is arranged on the die, and the bonding interface is collectively bonded by heating, load and ultrasonic waves.

【００２３】まず、第１の実施形態について、詳細に説
明する。図２０に、半導体パッケージの電流経路モデル
を示す。図において、１８４：ドレイン用外部接続端
子、１８６：接合部、１８２：チップ裏面電極、１８
０：チップ、１８１：Ａｌ電極、１８５：金属バンプ、
１８３：ソース用外部接続端子（リード）である。ソー
ス／ドレイン用外部接続端子間の電気抵抗Ｒは（１）式
で表わされる。First, the first embodiment will be described in detail. FIG. 20 shows a current path model of the semiconductor package. In the drawing, 184: external connection terminal for drain, 186: junction, 182: chip back surface electrode, 18
0: chip, 181: Al electrode, 185: metal bump,
183: External connection terminal (lead) for source. The electric resistance R between the source / drain external connection terminals is represented by the following equation (1).

【００２４】…（１） （１）式でチップの内部抵抗Ｒ４を除いた部分が実装抵
抗となる。バンプの抵抗Ｒ６は、 Ｒ６＝（ρ×ｈ／Ｓ）／ｎ …（２） (ここでρ：バンプの固有抵抗，ｈ：バンプ高さ，Ｓ：
断面積，ｎ：バンプ数）で表わされる。Ａｕバンプの寸
法は、Ａｌパッド上にバンプを低コストで直接形成でき
るワイヤのボールボンディングで作るとすると、直径：
１５０μｍ，厚さ：２０μｍが標準的な寸法になる。こ
の場合のバンプの抵抗は（０．０２６／ｎ)ｍΩとな
り、十分小さくできる。次にＡｌ電極膜の抵抗Ｒ５は、 Ｒ５≒（ρ／４πｔ）ｌｎ（ｒ２／ｒ１） …（３） （ここで、ρ：電極膜の固有抵抗，ｔ：電極膜厚，ｒ
２：電極外径，ｒ１：バンプ径）で表わされる。電極外
径ｒ２は、バンプを均等にｎ個配置した場合ほぼ１／
(ｎ1/2）に比例するためｎ数を増せばｒ２／ｒ１は１に
近づき、電極膜厚を厚くしてバンプ数を多くすれば、Ｒ
５は十分に小さくできる。外部接続端子の抵抗（Ｒ１＋
Ｒ７）は、単純に （Ｒ１＋Ｒ７）＝ρ×Ｌ／Ｓ …（４） （ここでρ：リードの固有抵抗，Ｌ：リードの通電長
さ，Ｓ：通電断面積）で表わされ、前述したように標準
的な表面実装用のＳＯＰパッケージの場合（厚さ：０.
１６mm／幅：０.３mm／長さ：２mm×２)で１.４ｍΩ程
度になる。すなわち、実装抵抗が１ｍΩ以下のレベルで
は、単にバンプ構造を採用するだけでは実装抵抗を下げ
られず、外部接続端子の抵抗を下げる構造を採用しなけ
ればならない。そこで、本発明による半導体装置におい
ては、外部接続端子の抵抗を下げると同時に、外部接続
端子と配線基板の接続部の信頼性を確保し得る構造とし
た。(1) The portion of the equation (1) excluding the internal resistance R4 of the chip is the mounting resistance. R6 = (ρ × h / S) / n (2) (where ρ: specific resistance of bump, h: height of bump, S:
(N: number of bumps). Assuming that the size of the Au bump is made by ball bonding of a wire that can directly form the bump on the Al pad at low cost, the diameter is as follows:
Standard dimensions are 150 μm and thickness: 20 μm. In this case, the resistance of the bump is (0.026 / n) mΩ, which can be sufficiently reduced. Next, the resistance R5 of the Al electrode film is as follows: R5 ≒ (ρ / 4πt) ln (r2 / r1) (3) (where, ρ: specific resistance of the electrode film, t: electrode film thickness, r
2: electrode outer diameter, r1: bump diameter). The electrode outer diameter r2 is approximately 1/1 when n bumps are evenly arranged.
Since it is proportional to (n 1/2 ), if the number of n is increased, r2 / r1 approaches 1, and if the electrode thickness is increased and the number of bumps is increased, R2 / r1 is increased.
5 can be made sufficiently small. External connection terminal resistance (R1 +
R7) is simply expressed as (R1 + R7) = ρ × L / S (4) (where ρ: the specific resistance of the lead, L: the conductive length of the lead, and S: the conductive sectional area), as described above. In the case of a standard SOP package for surface mounting, as shown in FIG.
16 mm / width: 0.3 mm / length: 2 mm × 2) is about 1.4 mΩ. That is, when the mounting resistance is at a level of 1 mΩ or less, the mounting resistance cannot be reduced simply by employing the bump structure, and a structure for lowering the resistance of the external connection terminal must be employed. Therefore, the semiconductor device according to the present invention has a structure capable of lowering the resistance of the external connection terminal and securing the reliability of the connection between the external connection terminal and the wiring board.

【００２５】図２１に、本発明による半導体装置１の基
本構造を示す。外部接続端子の抵抗を下げるには、単純
に通路断面を増して流路を短縮する以外に方法がないた
め、外部接続端子の一方は端子の板厚方向に電流経路を
取る構造する。この場合、通電距離（０.１〜０.２mm）
に比べて通電断面が数〜数十mm2 と十分大きいため、こ
の第１外部接続端子部１９４の抵抗は１μΩ以下にでき
る。他方の第２外部接続端子１９３は、チップの側面か
ら降ろして配線基板の端子と接続する構造となるため通
電距離が数mmとなるが、パッケージの両側から導通をと
ることで、２倍の通電断面積を確保できる。また本構造
では、後で述べる理由によって、第２外部接続端子に幅
広で厚肉の部材を使うことができるため、さらに数倍の
通電断面積を確保することができ、従来に比べて十数分
の１程度まで電気抵抗を下げることが可能となる。FIG. 21 shows the basic structure of the semiconductor device 1 according to the present invention. There is no other way to reduce the resistance of the external connection terminal than simply increasing the cross section of the passage and shortening the flow path. Therefore, one of the external connection terminals is configured to take a current path in the thickness direction of the terminal. In this case, the energizing distance (0.1 to 0.2 mm)
Since the current-carrying cross section is sufficiently large, ie, several to several tens of mm 2 , the resistance of the first external connection terminal portion 194 can be reduced to 1 μΩ or less. The other second external connection terminal 193 has a structure in which it is lowered from the side surface of the chip and connected to the terminal of the wiring board, so that the energization distance becomes several mm. A cross-sectional area can be secured. Further, in this structure, for the reason described later, a wide and thick member can be used for the second external connection terminal, so that a several times larger current-carrying cross-sectional area can be secured. The electric resistance can be reduced to about one-half.

【００２６】従来のパッケージ構造では、第２接続端子
の剛性が高くなると配線基板との接続部の長期信頼性が
低下するという問題があるが、本発明の構造において
は、樹脂匡体の腹部の第１外部接続端子面積が十分大き
く熱源のチップと配線基板が近接した構造であるため基
板との温度差が小さく、また接続端子の材質がＣｕ合金
であるため基板と熱膨張率が近くて熱歪みが小さいこと
により、第１及び第２接続端子と基板との接合部に発生
する熱歪みの絶対値が小さくなり、第２接続端子の剛性
が高くても温度サイクル信頼性を確保できるのである。
また、第２接続端子と基板との接続部には、チップを内
蔵する樹脂匡体と折曲げた足に相当するＣｕ部材の高さ
方向の熱膨張の差によって温度上昇時に押し付け力が働
き、この効果によっても従来のパッケージに比べて温度
サイクル信頼性が向上し、第２接続端子の剛性を高くで
きる。In the conventional package structure, there is a problem that if the rigidity of the second connection terminal is increased, the long-term reliability of the connection portion with the wiring board is reduced. However, in the structure of the present invention, the abdomen of the resin housing is reduced. The first external connection terminal has a sufficiently large area and the heat source chip and the wiring board are close to each other, so that the temperature difference between the substrate and the wiring board is small, and since the connection terminal is made of a Cu alloy, the coefficient of thermal expansion is close to that of the substrate. Since the strain is small, the absolute value of the thermal strain generated at the joint between the first and second connection terminals and the substrate becomes small, and the temperature cycle reliability can be secured even if the rigidity of the second connection terminal is high. .
In addition, a pressing force acts on the connection portion between the second connection terminal and the substrate when the temperature rises due to a difference in thermal expansion in the height direction between the resin housing containing the chip and the Cu member corresponding to the bent leg, This effect also improves the temperature cycle reliability as compared with the conventional package, and can increase the rigidity of the second connection terminal.

【００２７】また、図２１のパッケージを組み立てるた
めのモールド工程において、第２接続端子１９３を上金
型の側壁で押し下げることにより、貴金属バンプ１９５
を介して第１接続端子部材１９４をモールド金型の底面
に押し付けることが可能となり、金型に特別な工夫を加
えることなく樹脂匡体の腹部に接続端子が確実に露出し
たパッケージを組み立てることが可能となるのである。
この場合、特に重要なポイントとなるのは、バンプを介
して接続された第２接続端子部材を樹脂匡体の両側から
出していることである。第２端子部材の両側から押し下
げることにより、第１端子部材の傾きの発生やバンプの
剥がれを防いで、確実で歩留りの高い樹脂モールドが可
能となっている。もし片側で押し下げる構造では、押し
下げた第２端子部材の金型接触部と第１端子部材の下金
型接触部間でモーメントが発生し、一部のバンプ接合部
に引張力が発生して接合部剥がれが発生したり、第１端
子部材の片側が浮いて接合面に樹脂が回り込む不良を発
生したりするため、確実で歩留りの高い樹脂モールドが
できない。Also, in the molding step for assembling the package shown in FIG. 21, the second connection terminal 193 is pushed down by the side wall of the upper mold, so that the noble metal bump 195 is formed.
, The first connection terminal member 194 can be pressed against the bottom surface of the mold, and the package in which the connection terminals are securely exposed on the abdomen of the resin housing can be assembled without adding special measures to the mold. It is possible.
In this case, a particularly important point is that the second connection terminal members connected via the bumps are protruded from both sides of the resin housing. By pressing down from both sides of the second terminal member, occurrence of inclination of the first terminal member and peeling of the bumps can be prevented, and a reliable and high-yield resin molding can be achieved. If the structure is depressed on one side, a moment is generated between the depressed mold contact portion of the second terminal member and the lower die contact portion of the first terminal member. Partial peeling occurs, or a defect that one side of the first terminal member floats and the resin wraps around the joint surface occurs, so that a reliable and high-yield resin molding cannot be performed.

【００２８】次に、第２の実施形態について詳細に説明
する。チップ裏面の接合に要求される特性は、１）電気
的導通が取れて外部接続端子（ダイ）への熱伝導性が高
いこと、２）温度サイクル寿命が高いこと、３）パッケ
ージを基板に搭載するときの半田付け温度に耐えること
と、４）チップ裏面の広い領域の接合が量産ラインの短
いタクトで可能であり、チップへの悪影響がないことの
４点である。Ｐｂレスの適当な高融点半田材料がないた
め、半田以外の材料を使って上記特性を満たす接合を行
う必要がある。貴金属材料を接合材料に用いた場合、材
料の熱伝導率が従来半田の１０倍程度あるため、同一接
合厚さにした場合でも接合箇所がチップ裏面に均等に分
散していれば１／１０の接合面積で同じ伝熱特性が得ら
れる。つまり熱放散性において、非常に有利である。温
度サイクル寿命に関しては、チップの熱膨張と外部接続
端子（ダイ）の熱膨張差に伴う熱歪みをどこの変形で吸
収するかが大きく影響する。従来の半田では、半田の降
伏強度が低かったため、歪みのほとんどを半田の変形で
吸収し、半田部で破壊していた。この場合、チップに歪
みがほとんど加わらないためチップ特性の安定性や信頼
性が高いという利点はあった。これに対して貴金属部材
で接合した場合は、降伏強度が半田よりは高く、Ｓｉや
Ｃｕよりは小さいため、チップやダイの歪みは増すが接
合部の寿命は長くなる。チップに加わる歪みの大きさ
は、貴金属層の中に放熱性が問題とならない程度に空洞
を設けることで調整することができる。具体的に空洞を
設ける手段としては、接合部材にメッシュシートや粒子
や凹凸のあるシートやめっき膜を用いることで空洞が得
られる。Next, a second embodiment will be described in detail. The characteristics required for bonding on the back of the chip are: 1) high electrical conductivity and high thermal conductivity to external connection terminals (die); 2) high temperature cycle life; 3) mounting the package on the board. And 4) bonding of a wide area on the back surface of the chip is possible with a short tact of the mass production line, and there is no adverse effect on the chip. Since there is no Pb-less suitable high melting point solder material, it is necessary to perform joining satisfying the above characteristics using a material other than solder. When a noble metal material is used as the bonding material, the thermal conductivity of the material is about 10 times that of the conventional solder. Therefore, even if the bonding thickness is the same, if the bonding portions are evenly distributed on the back surface of the chip, it is reduced to 1/10. The same heat transfer characteristics can be obtained at the joint area. That is, it is very advantageous in heat dissipation. Regarding the temperature cycle life, the deformation which absorbs the thermal strain caused by the difference between the thermal expansion of the chip and the thermal expansion of the external connection terminal (die) has a great effect. In the conventional solder, since the yield strength of the solder was low, most of the distortion was absorbed by the deformation of the solder, and the solder was broken at the solder portion. In this case, almost no distortion is applied to the chip, and there is an advantage that the stability and reliability of the chip characteristics are high. On the other hand, in the case of joining with a noble metal member, the yield strength is higher than that of solder and smaller than that of Si or Cu, so that the distortion of the chip or die increases, but the life of the joint becomes longer. The magnitude of the strain applied to the chip can be adjusted by providing a cavity in the noble metal layer to such an extent that heat dissipation does not matter. Specifically, as a means for providing a cavity, a cavity can be obtained by using a mesh sheet, a sheet having particles or irregularities, or a plating film as a joining member.

【００２９】耐熱性に関しては問題ない。最も重要なの
は接合組み立て性である。貴金属同士を従来の熱圧着法
で接合する場合には、短時間で接合するために加熱温度
を４００〜５００℃にする必要があった。この方法で
は、室温との温度差が大きいため冷却過程の熱歪み量が
大きくなりチップサイズがそれほど大きくない場合でも
破損する危険が大きいという問題があった。本発明にお
いては、その問題を解決するために接合温度を２５０℃
以下とし、その温度で確実な接合を達成するために超音
波振動を利用する方法を採用した。しかしチップをダイ
に超音波接合する場合には、ダイとチップを硬質のヒー
トステージと硬質の接合ツールで挟んで加圧しつつ超音
波振動を加えるため、チップの回路形成面と硬質の接合
治具が接触した部分でチップが破損するという問題が生
じる。この問題に対して、本発明ではチップの回路形成
側の電極にＡｕバンプを形成し、回路形成側にもダイと
同等サイズの外部接続端子部材（リード）を合わせて配
置し、チップと硬質の接合治具が直接接触しない構造と
してチップの破損を防いだ。チップの上下２ヵ所に接合
箇所がある場合、接合の程度にばらつき（片側がよく接
合されて、片側が接合されない状態）が生じることが懸
念されるが、超音波接合において接合箇所が接合治具に
対して直列に配置されている場合には、片側の接合が進
行するとその部分の相対振動が押えられ、接合されてい
ない部分の相対振動が大きくなってそこの接合が進行す
るという自己調整機能が働くため、２ヵ所とも同程度の
強度の接合部が得られるのである。ただし、接合面積を
放熱の点からチップ裏面側で広くしたい場合は、チップ
上下の接合材料を変えてチップの回路形成面側を降伏強
度が高くチップ裏面側を降伏強度が低い材料にして接合
することで、接合面積に差をつけることが可能である。
以上の接合構造と接合方法を採用することにより、Ｐｂ
レスで高性能・高信頼性のチップ裏面接合が可能とな
る。There is no problem with respect to heat resistance. Most important is the joint assemblability. When precious metals are joined to each other by a conventional thermocompression bonding method, it is necessary to set the heating temperature to 400 to 500 ° C. in order to join them in a short time. In this method, the temperature difference from the room temperature is large, so that the amount of thermal distortion in the cooling process is large, and there is a problem that even if the chip size is not so large, there is a high risk of breakage. In the present invention, in order to solve the problem, the joining temperature is set to 250 ° C.
In the following, a method using ultrasonic vibration was employed to achieve reliable bonding at that temperature. However, when ultrasonic bonding a chip to a die, the die and the chip are sandwiched between a hard heat stage and a hard bonding tool, and ultrasonic vibration is applied while applying pressure. However, there is a problem that the chip is broken at a portion where the contact is made. In order to solve this problem, in the present invention, an Au bump is formed on the electrode on the circuit formation side of the chip, and external connection terminal members (leads) of the same size as the die are also arranged on the circuit formation side, so that the chip and the hard bump are formed. The structure prevents the joining jig from directly contacting, preventing chip breakage. If there are two places at the top and bottom of the chip, there is a concern that the degree of bonding may vary (one side is well bonded and one side is not bonded). When the joints are arranged in series, the self-adjustment function suppresses the relative vibration of that part when the joining of one side progresses, and the relative vibration of the part that is not joined increases and the joining proceeds there Works, so that a joint having the same strength can be obtained in both places. However, if it is desired to increase the bonding area on the back side of the chip from the viewpoint of heat dissipation, the bonding material at the top and bottom of the chip is changed and bonding is performed using a material having a high yield strength on the circuit forming side of the chip and a low yield strength on the back side of the chip. This makes it possible to make a difference in the bonding area.
By employing the above joining structure and joining method, Pb
And high-performance, high-reliability chip backside bonding is possible.

【００３０】なお、第３の実施形能の作用・効果につい
ては、第２の実施形態に記述した通りである。実際の接
合時間は、ワークの移動や位置決めの時間を除くと数百
ｍｓ程度で、現行の複数本のワイヤボンディングに要し
ている時間より短い時間である。予めＡｕバンプをチッ
プのＡｌ電極に形成しておく必要があるが、生産タクト
の点で影響がなく、チップ・ダイ接続とボンディングを
同時に行える点で従来より生産タクトの短縮が可能とな
る。The operation and effect of the third embodiment are as described in the second embodiment. The actual joining time is about several hundred ms, excluding the time for moving and positioning the work, which is shorter than the time currently required for a plurality of wire bondings. It is necessary to previously form an Au bump on the Al electrode of the chip, but there is no effect on the production tact, and the chip-die connection and bonding can be performed at the same time, so that the production tact can be shortened as compared with the related art.

【００３１】（実施例）以下、上記の実施形態の具体的
構造を示す本発明の実施例を図面を用いて詳細に説明す
る。(Example) An example of the present invention showing a specific structure of the above embodiment will be described in detail with reference to the drawings.

【００３２】図１は、本発明による半導体パッケージの
一実施例を示す。（ａ）は樹脂部を除去し外部接続端子
を透視した上面図、（ｂ）は断面図、（ｃ）は下面図で
ある。図において、半導体チップ１は４×２mmの大きさ
の縦型ＭＯＳトランジスタであり、ソース及びゲート用
Ａｌ電極２，３の膜厚は約４μｍ、ドレン電極となる裏
面電極４の最表面にはＡｕが蒸着されている。チップの
ソース及びゲート電極には多数または複数Ａｕバンプ８
が、ボールボンディング法によって、均等にすなわち各
電極の全面にほぼ等間隔に配置されて形成されている。
ソース及びゲート用リード端子５，６は、Ｃｕコア１１
にＰｄ／Ａｕの貴金属めっき１２が施された構造で、板
厚０.２mm である。ソース用リード端子５の幅は、ソー
ス電極２とほぼ同じ大きさである。すなわち、ソース用
リード端子５はソース電極２のほぼ全面を覆う。チップ
上のＡｕバンプと各リード端子のＰｄ／Ａｕ面は２３０
℃の加熱温度でダイレクトに超音波圧着されている。圧
着されたＡｕバンプの大きさは、ほぼ１５０μｍΦ×２
０μｍである。外部接続用ダイ端子７は、Ｃｕコア１３
にＰｄ／Ａｕの貴金属めっき１４が施された構造で、片
面にはさらに約１０μｍのＡｇめっき１５が施されてい
る。チップ裏面電極のＡｕ面とダイ端子のＡｇめっき面
はＡｕバンプ／リード端子の場合と同様に２３０℃の加
熱温度でダイレクトに超音波接合されている。ソース用
リード端子は、モールドされた樹脂匡体１６の左右の側
壁から外に導出され、かつ折り曲げ加工が施されてお
り、左右に取り出された幅広のリード端子にはスリット
１０が設けられ、また、チップ上に位置する部分にはい
くつかの開口部９が設けられている。ゲート用リード端
子も樹脂匡体１６の左右の側壁から外に導出されてい
る。ドレイン用ダイ端子は樹脂匡体の底面に露出してい
る。ダイ端子の下面（配線基板上接続端子との接続面）
と曲げ加工されたソース及びゲート用リード端子の下面
（同接続面）は同じ高さすなわち同一平面になるように
加工されている。FIG. 1 shows an embodiment of a semiconductor package according to the present invention. (A) is a top view in which the resin portion is removed and the external connection terminal is seen through, (b) is a cross-sectional view, and (c) is a bottom view. In the figure, a semiconductor chip 1 is a vertical MOS transistor having a size of 4 × 2 mm, the thickness of the source and gate Al electrodes 2 and 3 is about 4 μm, and the outermost surface of a back electrode 4 serving as a drain electrode is formed of Au. Has been deposited. Multiple or multiple Au bumps 8 on the source and gate electrodes of the chip
Are formed evenly, that is, at substantially equal intervals over the entire surface of each electrode by a ball bonding method.
The source and gate lead terminals 5 and 6 are made of Cu core 11
And a Pd / Au noble metal plating 12 with a thickness of 0.2 mm. The width of the source lead terminal 5 is substantially equal to the width of the source electrode 2. That is, the source lead terminal 5 covers almost the entire surface of the source electrode 2. The Au bump on the chip and the Pd / Au surface of each lead terminal are 230
Ultrasonic pressure bonding is performed directly at a heating temperature of ° C. The size of the pressed Au bump is approximately 150 μmΦ × 2
0 μm. The external connection die terminal 7 is a Cu core 13
And a Pd / Au noble metal plating 14 is applied thereon, and an Ag plating 15 of about 10 μm is further applied on one surface. The Au surface of the back electrode of the chip and the Ag-plated surface of the die terminal are directly ultrasonically bonded at a heating temperature of 230 ° C. as in the case of the Au bump / lead terminal. The source lead terminals are led out from the left and right side walls of the molded resin housing 16 and are subjected to a bending process. The slits 10 are provided in the wide lead terminals extracted to the left and right, and Some openings 9 are provided in a portion located on the chip. The gate lead terminals are also led out from the left and right side walls of the resin housing 16. The drain die terminal is exposed on the bottom surface of the resin housing. Lower surface of die terminal (connection surface with connection terminal on wiring board)
The lower surfaces (the same connection surfaces) of the source and gate lead terminals that have been bent are processed to have the same height, that is, the same plane.

【００３３】本実施例によれば、ソース電極とソース用
リード端子が、均等配置された多数のＡｕバンプによっ
て接続され、幅広のリード端子が左右から導出された構
造であること、ダイ端子が裏面電極とＡｇめっき膜によ
って直接接合され、配線基板までの流路断面が大きくか
つ通電距離が非常に短い（板厚分）構造であることか
ら、パッケージの実装抵抗を大幅に下げることができ
る。これにより、実装抵抗１ｍΩ以下という従来にはな
い低実装抵抗の半導体パッケージを備える新規な半導体
装置が得られる。また、チップとＣｕ端子との接合部に
は回路面側は厚さ２０μｍのＡｕバンプ、チップ裏面側
は厚さ１０μｍのＡｇめっきが介在しており、それらが
Ｃｕ端子材に比べて柔らかい（降伏強度が低い）材料で
あるためクッション材の役割を果たし、チップに大きな
力が加わることを防ぐ効果があること、ＡｕやＡｇは半
田に比べて温度サイクル寿命が長いことのために、半導
体パッケージとしての長期信頼性に優れるという利点が
ある。また、配線基板に搭載した場合には、ダイ端子の
広い面積で基板と接合され、発熱体のチップと最短距離
で良好な熱伝導状態で接続されるため基板とパッケージ
の温度差が小さく、基板の熱膨張率とＣｕ端子の熱膨張
率は近いため両者の間に発生する熱歪みは小さい。この
ため、半導体パッケージと配線基板間の接合部は温度サ
イクル寿命が長く、長期信頼性に優れる利点がある。さ
らには、チップ上に位置するソース用リード端子に開口
部を設けているため、Ａｕバンプが潰れてリード端子と
チップの間隙が小さくなった場合でも、開口部から樹脂
の侵入が生じること、開口部からガス抜きが行われるこ
との２つの効果で樹脂モールド工程におけるボイドの発
生を防ぐことが可能となり、パッケージの信頼性を損な
うことがない。According to the present embodiment, the source electrode and the source lead terminal are connected by a number of Au bumps arranged evenly, the wide lead terminal has a structure derived from the left and right, and the die terminal has a rear surface. Since the electrode and the Ag plating film are directly joined to each other, the cross section of the flow path to the wiring board is large, and the conduction distance is very short (equivalent to the plate thickness), so that the mounting resistance of the package can be significantly reduced. As a result, a novel semiconductor device including a semiconductor package having a low mounting resistance, which is not conventionally known, having a mounting resistance of 1 mΩ or less can be obtained. Also, at the junction between the chip and the Cu terminal, a Au bump with a thickness of 20 μm is interposed on the circuit surface side and an Ag plating with a thickness of 10 μm is interposed on the back surface side of the chip, which are softer than the Cu terminal material (yield). (Low strength) It plays a role of cushioning material because it has the effect of preventing a large force from being applied to the chip. Au and Ag have a longer temperature cycle life than solder, so they are used as semiconductor packages. Has the advantage of excellent long-term reliability. Also, when mounted on a wiring board, the die terminal is bonded to the board over a large area and connected to the chip of the heating element in the shortest distance with good heat conduction. And the thermal expansion coefficient of the Cu terminal are close to each other, so that the thermal strain generated between them is small. Therefore, the junction between the semiconductor package and the wiring board has an advantage that the temperature cycle life is long and the long-term reliability is excellent. Further, since the opening is provided in the source lead terminal located on the chip, even if the Au bump is crushed and the gap between the lead terminal and the chip is reduced, intrusion of resin from the opening occurs, With the two effects of degassing from the part, it is possible to prevent the occurrence of voids in the resin molding process, and the package reliability is not impaired.

【００３４】また、チップの裏面電極とダイ端子との接
続構造として、Ａｇめっき膜を介してＡｕ／Ａｇの超音
波接合を行っており、半田レス接合としているため、耐
熱性が高く温度サイクル信頼性の高い接続構造を持つ半
導体パッケージを提供できる。Further, as a connection structure between the back electrode of the chip and the die terminal, an Au / Ag ultrasonic bonding is performed via an Ag plating film, and a solderless bonding is used, so that heat resistance is high and temperature cycle reliability is high. A semiconductor package having a connection structure with high reliability can be provided.

【００３５】なお、ここではＡｕバンプのサイズとして
１５０μｍΦとしたが、バンプの形成が可能であれば数
百μｍΦと大きくする方がよい。バンプサイズを大型化
すると、さらに低抵抗化が図れ、また接合強度を向上で
きるためパッケージ組み立て時の外力によるバンプ接合
部の剥がれ発生を防止するのに有効となり、製造歩留り
を向上できるという効果がある。Although the size of the Au bump is 150 μmΦ here, it is better to increase the size to several hundred μmΦ if the bump can be formed. When the bump size is increased, the resistance can be further reduced, and the bonding strength can be improved. Therefore, it is effective to prevent the occurrence of peeling of the bump bonding portion due to an external force at the time of assembling the package, which has the effect of improving the manufacturing yield. .

【００３６】図２は、本発明による半導体パッケージに
おいて、Ａｇバンプ圧着方式をチップ・ダイ接続に採用
した場合の一実施例を示す。図において半導体チップ２
１のＡｌ電極２２と貴金属めっき２５を施されたリード
端子２６はＡｕバンプ３０によって強固に接合されてい
る。チップの裏面電極２３と貴金属めっきを施されたダ
イ端子２９はＡｇバンプ３１によって接合されている。
リード端子は片側が樹脂匡体３２の側壁近傍で切断さ
れ、片側は配線基板の端子と接続するために曲げ加工が
施されてダイと同じ高さに揃えられている。FIG. 2 shows an embodiment in which the Ag bump compression bonding method is adopted for the chip-die connection in the semiconductor package according to the present invention. In the figure, a semiconductor chip 2
The first Al electrode 22 and the lead terminal 26 provided with the noble metal plating 25 are firmly joined by the Au bump 30. The back electrode 23 of the chip and the die terminal 29 plated with noble metal are joined by an Ag bump 31.
One side of the lead terminal is cut near the side wall of the resin housing 32, and one side is subjected to a bending process so as to be connected to the terminal of the wiring board, and is arranged at the same height as the die.

【００３７】本実施例によれば、チップとダイ端子間が
Ａｇバンプで接続されているため構造的に変位を吸収可
能でる。このため、ダイ端子／チップ間の接合部の温度
サイクル寿命が格段に長く、Ｐｂレスで環境にやさしく
信頼性の高い半導体パッケージを提供できる。また、配
線基板の接続端子との半田接合部には、熱歪みがほとん
ど加わらないため、実装信頼性を大幅に向上できる。ま
た、パッケージをチップと同等なサイズにまで小型化で
き、パッケージの厚みも１mm程度に薄型化することがで
き、高密度実装に適した小型の表面実装用半導体パッケ
ージを提供できる。According to this embodiment, since the chip and the die terminal are connected by the Ag bump, the displacement can be structurally absorbed. For this reason, the temperature cycle life of the junction between the die terminal and the chip is extremely long, and a Pb-free, environmentally friendly and highly reliable semiconductor package can be provided. Also, since thermal distortion is hardly applied to the solder joints with the connection terminals of the wiring board, mounting reliability can be greatly improved. Further, the size of the package can be reduced to the same size as the chip, the thickness of the package can be reduced to about 1 mm, and a small surface-mount semiconductor package suitable for high-density mounting can be provided.

【００３８】図３は、本発明による半導体パッケージに
おいて、Ａｇペースト接着方式をチップ・ダイ接続に用
いた場合の一実施例を示す。図において半導体チップ３
５のＡｌ電極３６と貴金属めっき３９されたリード端子
４０はＡｕバンプ４５によって強固に接合されている。
チップの裏面電極３７とダイ端子４３はＡｇペースト４
６によって接着されている。ダイ端子はＣｕコア４１に
Ｐｄ／Ａｕめっき４２された構造で、周囲にはモールド
樹脂へのアンカー効果が働くように端面のザグリ加工処
理が施されている。リード端子は樹脂匡体４７の両サイ
ドから取り出されている。FIG. 3 shows an embodiment in which an Ag paste bonding method is used for chip-die connection in a semiconductor package according to the present invention. In the figure, a semiconductor chip 3
The Al electrode 36 of No. 5 and the lead terminal 40 plated with the noble metal 39 are firmly joined by an Au bump 45.
The back electrode 37 of the chip and the die terminal 43 are made of Ag paste 4
6 are adhered. The die terminal has a structure in which a Cu core 41 is plated with Pd / Au 42, and a peripheral surface of the die terminal is subjected to a counterbore processing so that an anchor effect to a mold resin is exerted. The lead terminals are taken out from both sides of the resin housing 47.

【００３９】本実施例によれば、図１の実施例と同様の
効果が得られる。また、ダイ端子の端面に樹脂に食い込
む形状の加工を施したため、モールド樹脂の収縮力でダ
イ端子をチップ裏面に押し付けることができ、組み立て
が簡便に行えるＡｇペーストによるチップ・ダイ接続方
式を採用しても信頼性のある半導体パッケージを提供で
きる。According to this embodiment, the same effects as those of the embodiment of FIG. 1 can be obtained. In addition, since the end surface of the die terminal is processed so as to cut into the resin, the die terminal can be pressed against the back surface of the chip by the shrinkage force of the mold resin, and a chip-die connection method using Ag paste that can be easily assembled is adopted. However, a reliable semiconductor package can be provided.

【００４０】図４は、本発明による半導体パッケージに
おいて、回路形成面を配線基板に向けた実装が可能なパ
ッケージ構造の一実施例を示す。図において、半導体チ
ップ５０の回路形成面側の主電流用及び制御用Ａｌ電極
５１，５２には、図１の実施例と同様に各々複数のＡｕ
バンプ５７が形成され、各電極サイズと同等で樹脂匡体
５９面内に納まる大きさの主電流用外部接続端子５５と
制御用外部接続端子５６が超音波熱圧着されている。各
外部接続端子表面にはＰｄ／Ａｕフラッシュめっきが施
されている。チップ裏面には最表面がＡｕまたはＡｇ蒸
着膜で構成された裏面電極５３が形成され、Ｃｕ表面に
Ｐｄ／Ａｕフラッシュめっきが施された裏面電極用外部
接続端子５４が表面に０.１〜５μｍ 厚さのＳｎめっき
が施されたＡｇメッシュシート５８を挟んで超音波熱圧
着されている。主電流用及び制御用外部接続端子は樹脂
匡体表面に露出した状態でモールドされ、裏面電極用外
部接続端子は樹脂匡体の左右側面から導出されて片側が
切断除去され他方が折曲げ加工されている。FIG. 4 shows an embodiment of a package structure in which a semiconductor package according to the present invention can be mounted with a circuit forming surface facing a wiring board. In the drawing, a plurality of Au electrodes are respectively provided on the main current and control Al electrodes 51 and 52 on the circuit forming surface side of the semiconductor chip 50 as in the embodiment of FIG.
A bump 57 is formed, and an external connection terminal 55 for main current and an external connection terminal 56 for control having the same size as each electrode and contained within the surface of the resin housing 59 are subjected to ultrasonic thermocompression bonding. Pd / Au flash plating is applied to the surface of each external connection terminal. On the back surface of the chip, a back surface electrode 53 whose outermost surface is formed of an Au or Ag vapor-deposited film is formed, and external connection terminals 54 for back surface electrodes having a Cu surface plated with Pd / Au flash plating have a surface of 0.1 to 5 μm. Ultrasonic thermocompression bonding is performed with an Ag mesh sheet 58 having a thickness of Sn plating applied therebetween. The main current and control external connection terminals are molded in a state exposed on the surface of the resin housing, and the external connection terminals for the back electrode are led out from the left and right side surfaces of the resin housing, one side is cut and removed, and the other is bent. ing.

【００４１】本実施例によれば、図１と同様の効果が得
られる。さらに、チップの発熱面である回路形成面側か
ら配線基板に最も効率的に放熱できる構造であるため、
パッケージの冷却が最も効率的に行われてＡｌ電極部の
温度上昇が小さく抑えられ、その結果、外部接続端子と
チップ間に発生する熱歪みを小さくできかつＡｌ電極膜
とＡｕボール間の化合物の成長を抑制できるため、実使
用環境下での製品寿命を大幅に改善できるのである。According to the present embodiment, the same effects as in FIG. 1 can be obtained. Furthermore, because it is the structure that can radiate heat to the wiring board most efficiently from the circuit forming surface side, which is the heating surface of the chip,
The cooling of the package is performed most efficiently, and the temperature rise of the Al electrode portion is suppressed to be small. As a result, the thermal strain generated between the external connection terminal and the chip can be reduced, and the compound between the Al electrode film and the Au ball can be cooled. Because growth can be suppressed, the product life in an actual use environment can be significantly improved.

【００４２】図５は、本発明による半導体パッケージを
組み立てるのに用いるソース及びゲート電極用マトリッ
クスリードフレームの一実施例、図６は、図５のＡ−
Ａ′断面から見たパッケージ組み立て時の接合方法、図
７は、接合後のマトリックスリードフレームの外観、図
８は、樹脂モールド方法を示す図である。図５におい
て、ソース用リード６１とゲート用リード６２が対とな
ったユニットがＸ−Ｙ方向に配置されている。次の図６
において、マトリックスリードフレームのソース用及び
ゲート用リード６１，６２上に、半導体チップ６５のＡ
ｌ電極６６，６７上に予め形成されたＡｕバンプ７１が
位置合わせされて搭載され、さらにチップ裏面電極６８
上には、予めＡｇバンプ７０が形成されたドレイン用ダ
イ端子６９が搭載されている。マトリックスリードフレ
ームを載せるヒートステージ７４を２００℃に加熱し、
ダイ端子の上から超音波振動７６を加える接合ツール７
３で１バンプ当り５０〜５００ｇの力で加圧し、チップ
上下の接合部を同時に接合している。超音波接合では、
バンプの潰れ量を制御して接合し、リードとダイ端子の
高さを所定の範囲内の精度に抑えている。超音波の振動
方向は、リードの剛性が高い長手方向（図５の上下方
向）に加え、リードの共振による接合不良の発生を防い
でいる。ダイ端子は、個別に切り離して組み立てるの
で、貴金属めっきした大きなＣｕ板から打抜き加工して
製作している。接合を完了したマトリックスリードフレ
ーム（図７）を、モールド金型にセットした状態が図８
である。図８は、図７のＡ−Ａ′断面方向から見た場合
の断面構造である。図８において、モールド金型８０，
８１のキャビティ８２は、マトリックスリードフレーム
の配置に合わせて、Ｘ−Ｙ方向に配列して形成されてい
る。また、リード吊が納まる逃げ空間８３も設けられて
いる。下金型８１のキャビティに半導体チップ６５が納
まるように位置合わせしてマトリックスリードフレーム
をセットし、その上から上金型を載せて押し付ける。キ
ャビティから外に出るソース及びゲートリードの高さ
は、下金型のキャビティの深さと同等かわずかに高くし
てあり、上金型のキャビティ側壁部分でリードを挟んだ
ときに、ダイ端子がビャビティ底面に押し付けられる構
造としている。リードはチップ部を中心として左右で押
し下げられることになるが、押し込み量が大きいとリー
ドが曲げ変形を受け、チップ中央のＡｕバンプ接合部に
引張り力が発生する。このため、上金型のリード抑え部
はナイフ状に加工し、下金型は内側が低くて外側が高い
段差を持たせ、リードをＷ形状に変形させてチップ中央
の凸状の曲げ変形が小さくなるように工夫している。モ
ールド樹脂は、熱膨張を下げるシリカ粒子のサイズを細
かくし、バンプ接合部の隙間１０〜２０μｍの空隙への
充填性を上げ、圧入プロセスで樹脂ボイドの発生を防止
している。FIG. 5 is an embodiment of a matrix lead frame for source and gate electrodes used to assemble a semiconductor package according to the present invention. FIG.
FIG. 7 is a diagram illustrating a joining method at the time of assembling the package viewed from the A ′ cross section, FIG. 7 is a diagram illustrating an appearance of the matrix lead frame after joining, and FIG. In FIG. 5, a unit in which a source lead 61 and a gate lead 62 are paired is arranged in the XY direction. Next figure 6
Of the semiconductor chip 65 on the source and gate leads 61 and 62 of the matrix lead frame.
Au bumps 71 formed in advance on the electrodes 66 and 67 are mounted in alignment with each other.
On the upper side, a drain die terminal 69 on which an Ag bump 70 is formed in advance is mounted. The heat stage 74 on which the matrix lead frame is placed is heated to 200 ° C.
Joining tool 7 for applying ultrasonic vibration 76 from above the die terminal
In step 3, the pressure is applied with a force of 50 to 500 g per bump, and the upper and lower bonding portions of the chip are simultaneously bonded. In ultrasonic bonding,
Bonding is performed by controlling the amount of crushing of the bump, and the height of the lead and the die terminal is suppressed to an accuracy within a predetermined range. The vibration direction of the ultrasonic wave prevents the occurrence of bonding failure due to the resonance of the lead in addition to the longitudinal direction (the vertical direction in FIG. 5) where the rigidity of the lead is high. Since the die terminals are individually cut and assembled, they are manufactured by punching a large Cu plate plated with a noble metal. FIG. 8 shows a state in which the joined matrix lead frame (FIG. 7) is set in a mold.
It is. FIG. 8 is a cross-sectional structure viewed from the AA 'cross-sectional direction in FIG. 8, a mold 80,
The cavities 82 of the 81 are arranged in the X-Y direction in accordance with the arrangement of the matrix lead frame. An escape space 83 for accommodating lead suspension is also provided. A matrix lead frame is set in such a manner that the semiconductor chip 65 is positioned in the cavity of the lower die 81, and the upper die is placed thereon and pressed. The height of the source and gate leads out of the cavity is equal to or slightly higher than the depth of the cavity in the lower mold, and when the leads are sandwiched between the side walls of the cavity in the upper mold, the die terminals are not It is structured to be pressed against the bottom. The lead is pushed down on the left and right around the chip portion. However, if the pushing amount is large, the lead is subjected to bending deformation, and a tensile force is generated at the Au bump joint at the center of the chip. For this reason, the lead holding part of the upper mold is processed into a knife shape, and the lower mold has a step with a low inside and a high outside, and the lead is deformed into a W shape, and the convex bending deformation at the center of the chip is reduced. We are trying to make it smaller. The mold resin reduces the size of the silica particles that reduce the thermal expansion, increases the fillability of the gaps between the bump joints of 10 to 20 μm, and prevents the occurrence of resin voids in the press-fitting process.

【００４３】本実施例のリードフレーム及び製法によれ
ば、組み立て用のリードフレームにＩＣユニットをマト
リックス状に配置し、１リードフレームから取れるパッ
ケージの個数を増して生産性を上げることができるこ
と、金型はリード抑え部を除いて平面研削加工により合
わせ面の加工精度を出せるためコストを上げないで金型
を製造できること、チップ・ダイ接続と回路形成面側の
接続を一回の接合工程で行えるため生産工程の短縮が可
能となること、等の効果により低コスト半導体パッケー
ジを提供できる。同時に構造的な特徴として、チップサ
イズに近い大きさの小型かつ薄型の半導体パッケージを
提供できる。According to the lead frame and the manufacturing method of the present embodiment, the IC units are arranged in a matrix on the lead frame for assembly, and the number of packages that can be taken from one lead frame can be increased to improve productivity. Except for the lead holding part, the mold can be manufactured without increasing the cost because it can achieve the machining accuracy of the mating surface by surface grinding except for the lead holding part, and the chip-die connection and the connection on the circuit forming surface side can be done in one joining process Therefore, the production process can be shortened, and a low-cost semiconductor package can be provided. At the same time, as a structural feature, a small and thin semiconductor package having a size close to the chip size can be provided.

【００４４】図９は、本発明による半導体パッケージの
組み立てフローに関する一実施例である。図において、
組み立てには４つ部品が用いられる。半導体チップは、
ウェーハレベルでＡｕバンプが形成され、それからダイ
シングにより個片に切断される。Ａｕバンプの形成は、
ボールボンディング法，めっき法，Ａｕボール転写法の
いずれでもよい。ソース及びゲート用外部接続端子は、
Ｃｕ合金板からマトリックスリードフレーム状に打抜き
法あるいはエッチング法により加工整形され、表面にＮ
ｉ下地めっきを施した後、Ｐｄを０.０２〜１μｍ 程度
めっきし、最表面にＡｕを０.００１〜１μｍ 程度めっ
きして仕上げられる。ドレイン用外部接続端子は、Ｃｕ
条テープにＮｉ下地めっきを施した後、Ｐｄを０.０２
〜１μｍ程度めっきしてさらに最表面にＡｕを０.００
１〜１μｍ 程度めっきし、最後にチップと同等サイズ
の個片に切断加工される。チップ・ダイ接続用のＡｇシ
ートは、厚さ１０〜１００μｍのＡｇテープにプレス加
工を加えて片面あるいは両面に凹凸を形成し、その表面
にＳｎを０.１〜５μｍ 厚さ程度めっきする。このとき
の厚さは、Ａｇとの重量比が２０ｗｔ％以下となる厚さ
にしている。最後に、ドレイン用外部接続端子やチップ
と同等サイズの個片に切断している。各部品は、マトリ
ックスリードフレームをボンディングステージに載せて
から、半導体チップ，Ａｇシート，ドレイン用外部接続
端子の順に位置合わせして積層し、加熱と荷重と超音波
振動を加えて、１ＩＣ単位で一括接合を行う。マトリッ
クス全てを接合完了したら、樹脂モールド工程に入り、
図８と同様の要領で樹脂モールドを行う。最後に、マト
リックス状に繋がった半導体パッケージを個別に切断分
離し、リードの折曲げ整形加工を施して完成する。FIG. 9 is an embodiment relating to a flow of assembling a semiconductor package according to the present invention. In the figure,
Four parts are used for assembly. Semiconductor chips are
Au bumps are formed at the wafer level and then cut into individual pieces by dicing. The formation of the Au bump
Any of a ball bonding method, a plating method, and an Au ball transfer method may be used. External connection terminals for source and gate
Machining from a Cu alloy plate into a matrix lead frame by punching or etching.
After i-base plating, Pd is plated to a thickness of about 0.02 to 1 μm, and Au is plated to the outermost surface by a thickness of about 0.001 to 1 μm. The external connection terminal for the drain is Cu
After applying Ni underplating to the strip tape, Pd is adjusted to 0.02.
め っ き 1 μm plating and Au on the outermost surface
Plating is performed to about 1 to 1 μm, and finally, individual pieces of the same size as the chip are cut. The Ag sheet for chip-die connection is formed by pressing a Ag tape having a thickness of 10 to 100 μm to form irregularities on one or both sides, and plating the surface with Sn to a thickness of about 0.1 to 5 μm. The thickness at this time is such that the weight ratio with Ag is 20 wt% or less. Finally, it is cut into pieces each having the same size as the external connection terminal for drain and the chip. After placing the matrix lead frame on the bonding stage, the components are laminated and aligned in the order of semiconductor chip, Ag sheet, and external connection terminal for drain. Perform bonding. After joining all the matrices, enter the resin molding process,
The resin molding is performed in the same manner as in FIG. Lastly, the semiconductor packages connected in a matrix are individually cut and separated, and the leads are bent and shaped to complete.

【００４５】本実施例によれば、部品加工工程が並列ラ
インで多数個の一括生産が可能であり、また組み立てラ
インに入ってからの工程が（１）部品セット＋接合、
（２）樹脂モールド、（３）リードの切断整形の３工程
であり、従来のチップ・ダイ接続とワイヤボンディング
のプロセスに比べて１工程短縮でき、さらに組み立ての
タクトも（１）の工程がワイヤボンディングと同等のタ
クト以下で接合できるため、トータルの生産タクトの短
縮が可能で、生産性の大幅な向上が図れる。According to the present embodiment, a large number of parts can be batch-manufactured in parallel in the parts processing step, and the steps after entering the assembly line are (1) parts set + joining,
(2) Resin molding, (3) Lead cutting and shaping are three steps, which can be shortened by one step as compared with the conventional chip-die connection and wire bonding processes. Since bonding can be performed with less than the same tact as bonding, total production tact can be shortened and productivity can be greatly improved.

【００４６】図１０は、本発明によるチップ裏面電極接
合構造の一実施例を示す。リードフレームはソース・ゲ
ート用リードフレームとドレイン用リードフレームの２
種類のリードフレームを用いて組み立てる。図におい
て、ソース用リード９１とゲート用リード９２を形成し
たＣｕ合金のリードフレーム、及びドレイン用ダイ９５
を形成したリードフレームは、全面にＰｄ／Ａｕめっき
が施されている。ドレイン用ダイの上には、Ａｇボール
バンプ１０１がボールボンディング法により形成されて
いる。この２種のリードフレームの間に、Ａｌ電極９８
に予めＡｕボールバンプ１００を形成した裏面電極１０
２付きの半導体チップ９７を挟み、チップの上下２ヵ所
を同時に接合できる構造である。図１１は、この接合体
を樹脂モールドしてリードを整形加工した半導体パッケ
ージ構造の一例を示す。図において、樹脂匡体１０３の
側壁の片側からソース及びゲートリード９１，９２が導
出され、対向する他方の側壁からドレイン用リード１０
４が導出され、折曲げ加工されている。樹脂匡体内のリ
ードには局部的に細くなったネック部９３を設けてお
り、リードの折曲げ加工時に発生する応力がバンプ接合
部に伝わり難い構造としている。リードの導出位置の高
さは、左右で異なっている。従って、上下モールド金型
の合わせ面も段違いに加工されている。チップ裏面はＡ
ｕ蒸着膜／Ａｇバンプ１０１／Ｐｄ／Ａｕめっきダイ９
５の圧着構造、チップ上面はＡｌ電極９８，９９／Ａｕ
バンプ１００／Ｐｄ／Ａｕめっきリード９１，９２の圧
着構造となっている。FIG. 10 shows an embodiment of a chip back electrode bonding structure according to the present invention. The lead frame consists of a source / gate lead frame and a drain lead frame.
Assemble using different types of lead frames. In the figure, a lead frame made of a Cu alloy in which a source lead 91 and a gate lead 92 are formed, and a drain die 95 are formed.
Is formed on the entire surface of the lead frame, which is plated with Pd / Au. An Ag ball bump 101 is formed on the drain die by a ball bonding method. Between these two types of lead frames, an Al electrode 98 is provided.
Back electrode 10 on which Au ball bumps 100 are formed in advance
With the semiconductor chip 97 attached with the two, the upper and lower two parts of the chip can be simultaneously bonded. FIG. 11 shows an example of a semiconductor package structure in which this joined body is resin-molded to form leads. In the figure, source and gate leads 91 and 92 are led out from one side of a side wall of a resin housing 103, and a drain lead 10 is drawn from the other side wall facing the same.
4 is led out and bent. The lead in the resin housing is provided with a locally thin neck portion 93, so that the stress generated at the time of bending the lead is hardly transmitted to the bump joint. The height of the lead out position is different between the left and right. Therefore, the mating surfaces of the upper and lower molds are also processed stepwise. The back of the chip is A
u evaporated film / Ag bump 101 / Pd / Au plating die 9
5 pressure bonding structure, chip upper surface is Al electrode 98, 99 / Au
The bump 100 / Pd / Au plating leads 91 and 92 have a pressure bonding structure.

【００４７】本実施例において、チップ・ダイ接続構造
がＡｇバンプを介した貴金属同士の直接接合となってい
るので、耐熱性が高く、チップ／ダイ間の熱歪みをＡｇ
バンプが緩和してくれるため温度サイクル信頼性が高
く、Ｐｂレスで環境にやさしい半導体パッケージを提供
できる。また、リードは貴金属めっきが施されているた
め半田の濡れ性がよく、その結果、パッケージ組み立て
後の半田めっきが不要となるため、パッケージ組み立て
工程が短縮されて生産性が向上する。また、チップサイ
ズぎりぎりに樹脂をモールドすることが可能となるた
め、小型で薄型の半導体パッケージを提供できるという
効果もある。In this embodiment, since the chip-die connection structure is a direct bonding between noble metals via Ag bumps, the heat resistance is high, and the thermal distortion between the chip and the die is reduced by Ag.
Since the bumps relax, the temperature cycle reliability is high, and a Pb-free and environmentally friendly semiconductor package can be provided. In addition, since the leads are plated with a noble metal, the wettability of the solder is good. As a result, the solder plating after the package is assembled becomes unnecessary, so that the package assembling process is shortened and the productivity is improved. In addition, since resin can be molded almost to the chip size, a small and thin semiconductor package can be provided.

【００４８】図１２は、チップとダイを接合するための
接合シートの一実施例である。図において、シート１１
０は厚さ２０μｍの純Ａｇ製で、片面に深さ１０μｍの
溝１１１を形成している。溝の形成は、プレス加工ある
いはダイシングブレードによるハーフカット加工により
行っている。Ａｇシートの硬さは、圧延加工→溝加工を
終えた後、３５Ｈｖ以下になるように焼鈍処理してい
る。FIG. 12 shows an embodiment of a joining sheet for joining a chip and a die. In the figure, sheet 11
Numeral 0 is made of pure Ag having a thickness of 20 μm, and has a groove 111 with a depth of 10 μm formed on one surface. The grooves are formed by pressing or half-cutting with a dicing blade. After finishing the rolling and grooving, the hardness of the Ag sheet is annealed so as to be 35 Hv or less.

【００４９】本実施例の接合シートを用いてチップ／ダ
イの超音波圧接を行えば、接合中のＡｇシートの組成変
形が溝空間の存在と材料の柔らかさによって低い応力で
容易に進行し、Ｓｉチップに加わる応力が小さい条件で
接合界面での新生面の形成が行われて接合が進むため、
チップに損傷を与えないで強固で耐熱性の高い接合を達
成することが可能となる。また、パッケージの使用時に
は、チップの発熱に伴うチップ／ダイ間の熱歪みを、柔
らかくて溝空間のあるＡｇシートが吸収してくれるた
め、温度サイクル信頼性の高い半導体パッケージを提供
できる。When the chip / die is subjected to ultrasonic pressure welding using the bonding sheet of this embodiment, the composition deformation of the Ag sheet during bonding easily proceeds with low stress due to the existence of the groove space and the softness of the material. Since the new surface is formed at the bonding interface under the condition that the stress applied to the Si chip is small, the bonding proceeds,
It is possible to achieve a strong and highly heat-resistant joint without damaging the chip. In addition, when the package is used, the soft Ag-sheet with the groove space absorbs the thermal distortion between the chip and the die due to the heat generation of the chip, so that a semiconductor package with high temperature cycle reliability can be provided.

【００５０】図１３は、チップとダイを接合するための
接合シートの他の一実施例である。図において、接合シ
ートのコア部１１２は、図１２と同じ加工処理を施した
Ａｇシートである。その表面に、厚さ０.３〜２.０μｍ
のＳｎめっき１１３を施している。FIG. 13 shows another embodiment of a joining sheet for joining a chip and a die. In the figure, the core portion 112 of the joining sheet is an Ag sheet subjected to the same processing as in FIG. The surface has a thickness of 0.3 to 2.0 μm.
Sn plating 113 is applied.

【００５１】本実施例の接合シートを用いてチップ／ダ
イの超音波加熱圧接を行えば、加熱温度２２０℃以上の
条件下でＡｇ−Ｓｎ反応によって液相が形成されるため
シート表面が薄い膜の液体で覆われ、ダイあるいはチッ
プ裏面電極に押し付けられた領域は液体が外に排出され
て高融点部材同士の接合が容易に進行するため、低い加
圧条件で確実かつ強固な接合が容易に行えるという利点
がある。また接合界面から排出された低融点のＡｇ−Ｓ
ｎ層には、加熱時にコアから次々に溶解や拡散によって
Ａｇが供給されるため、最終的なＡｇ−Ｓｎ層の融点は
４７０℃以上に高めることができ、耐熱性の高い接合部
とすることができるのである。半導体パッケージとして
の信頼性に関しては、図１２と同様の効果が得られる。When the chip / die is subjected to ultrasonic heating and pressure welding using the bonding sheet of this embodiment, a liquid phase is formed by an Ag-Sn reaction under a heating temperature of 220 ° C. or more, so that the sheet surface is thin. In the area covered with the liquid and pressed against the die or chip back electrode, the liquid is discharged to the outside and the joining of the high melting point members proceeds easily, so that reliable and strong joining can be easily performed under low pressure conditions. There is an advantage that it can be performed. Also, the low melting point Ag-S discharged from the bonding interface
Ag is supplied to the n-layer one after another by melting and diffusion from the core during heating, so that the final melting point of the Ag-Sn layer can be increased to 470 ° C. or higher, and a heat-resistant joint is formed. You can do it. Regarding the reliability as a semiconductor package, the same effect as that of FIG. 12 can be obtained.

【００５２】図１４は、チップとダイを接合するための
接合シートの他の一実施例である。図において、接合シ
ートはＡｇワイヤ１１４，１１５を縦横に編んだメッシ
ュ状シートである。FIG. 14 shows another embodiment of a joining sheet for joining a chip and a die. In the figure, the joining sheet is a mesh sheet in which Ag wires 114 and 115 are knitted vertically and horizontally.

【００５３】本実施例によれば、ワイヤが重なった部分
の厚みは厚くてそれ以外の部分は薄いという凹凸のある
シートであるため、厚い部分の組成変形が容易に進行し
て図１２と同様の効果が得られるのである。According to this embodiment, since the sheet where the wires overlap is thick and the other portions are thin and uneven, the composition deformation of the thick portion easily progresses and the same as in FIG. The effect is obtained.

【００５４】図１５は、本発明による半導体パッケージ
において、チップ・ダイ間の接合にＡｇ粒子を用いた場
合の一実施例を示す。図において、半導体チップ１２０
の回路形成面側にはＡｌ電極１２１が形成され、その上
には複数のＡｇバンプ１２５が形成されている。チップ
の裏面には、最表面がＡｇめっき膜の裏面電極１２２が
形成されている。回路形成面側の貴金属めっきされたリ
ード１２３とＡｇバンプは直接、超音波熱圧着されてい
る。チップ裏面電極と貴金属めっきされたダイ端子１２
４は、樹脂１２７と９０vol％ 以上の比率で混合された
Ａｇ粒子１２６を挟んで、超音波熱圧着されている。樹
脂の量は、圧着時に押し出された樹脂がダイ端子の側面
から圧着ステージに流れ落ちない程度に少ない量とし、
混合体を粘性流体として扱える程度に多い量としてい
る。樹脂の性質は熱硬化性で、接合時の加熱により硬化
する種類の樹脂としている。Ａｇ粒子とチップ裏面のＡ
ｇ蒸着膜、およびＡｇ粒子とダイ端子、Ａｇ粒子同士は
接触部分の領域で部分的に金属接合が達成されている。
ダイ端子の寸法は、樹脂匡体１２８の底面の中に納まる
大きさであり、チップと同等である。チップより、わず
かに大きくても小さいくてもよい。FIG. 15 shows an embodiment in which Ag particles are used for bonding between a chip and a die in a semiconductor package according to the present invention. In the figure, a semiconductor chip 120 is shown.
An Al electrode 121 is formed on the circuit forming surface side, and a plurality of Ag bumps 125 are formed thereon. On the back surface of the chip, a back electrode 122 whose outermost surface is made of an Ag plating film is formed. The noble metal-plated lead 123 and the Ag bump on the circuit forming surface side are directly subjected to ultrasonic thermocompression bonding. Chip back electrode and die terminal 12 plated with noble metal
No. 4 is subjected to ultrasonic thermocompression bonding with the Ag particles 126 mixed with the resin 127 at a ratio of 90 vol% or more. The amount of resin should be small enough that the resin extruded during crimping does not flow down from the side of the die terminal to the crimping stage,
The amount is large enough to handle the mixture as a viscous fluid. The resin has a thermosetting property, and is a type of resin that is cured by heating at the time of joining. Ag particles and A on the back of the chip
The metal deposition is partially achieved in the region of the contact portion between the g-deposited film, the Ag particles and the die terminal, and the Ag particles.
The size of the die terminal is a size that fits in the bottom surface of the resin housing 128, and is equivalent to that of the chip. It may be slightly larger or smaller than the tip.

【００５５】本実施例によれば、低実装抵抗，小型・薄
型，Ｐｂレスの半導体パッケージを提供できる。また、
Ａｇ粒子が樹脂と混合されているので、樹脂の粘着性に
よってＡｇ粒子の飛散がなくなり、接合部へのＡｇ粒子
の供給が容易となって生産性が向上できる。また、接合
後のＡｇ粒子間の狭い隙間を混合された樹脂が埋めるた
め、モールド樹脂で隙間を埋める必要がなくなり、樹脂
ボイドの発生を大幅に低減できて歩留りを向上できると
いう効果もある。さらに、接合材が樹脂とＡｇ粒子の混
合体ではあるが、超音波を併用した加熱圧着を行ってい
るため、金属同士の接合界面から樹脂が排出され、接合
部では金属同士の強固な接合が達成されるため、接合信
頼性はＡｇペーストの接着に比べて格段に向上できると
いう効果もある。According to this embodiment, a semiconductor package having low mounting resistance, small size, thin shape, and Pb-less can be provided. Also,
Since the Ag particles are mixed with the resin, the Ag particles are not scattered due to the adhesiveness of the resin, and the supply of the Ag particles to the joint is facilitated, so that the productivity can be improved. Further, since the mixed resin fills the narrow gap between the Ag particles after joining, it is not necessary to fill the gap with the mold resin, and there is also an effect that the generation of resin voids can be greatly reduced and the yield can be improved. Furthermore, although the bonding material is a mixture of resin and Ag particles, since heat and pressure are applied together with the use of ultrasonic waves, the resin is discharged from the bonding interface between the metals, and a strong bonding between the metals at the bonding portion. Since this is achieved, there is also an effect that the joining reliability can be remarkably improved as compared with the bonding of the Ag paste.

【００５６】図１６は、本発明による半導体パッケージ
において、チップ／ダイ間の接合に溝を形成したＡｇシ
ートを用いた場合の一実施例を示す。図において、チッ
プ１３０のＡｌ電極１３１にはＡｕボール１３９が形成
され、裏面電極１３２の最表面にはＡｇ蒸着膜が形成さ
れている。リード端子１３５とダイ端子１３８の表面に
はＰｄめっきが施されている。チップ裏面とダイ端子間
には溝１４１を形成したＡｇシート１４０が挿入されて
いる。各接合部は、超音波併用の加熱圧着によりダイレ
クトに接合されている。リード端子は、樹脂匡体の１側
面から導出され、曲げ加工されている。FIG. 16 shows an embodiment in a case where an Ag sheet having a groove formed in a junction between a chip and a die is used in a semiconductor package according to the present invention. In the figure, an Au ball 139 is formed on the Al electrode 131 of the chip 130, and an Ag vapor deposition film is formed on the outermost surface of the back electrode 132. Pd plating is applied to the surfaces of the lead terminal 135 and the die terminal 138. An Ag sheet 140 having a groove 141 is inserted between the back surface of the chip and the die terminal. Each joint is directly joined by thermocompression bonding using ultrasonic waves. The lead terminals are led out from one side surface of the resin housing and are bent.

【００５７】本実施例によれば、図２と同様の効果が得
られる他に、リード端子が片側からのみ出ているので、
リード端子の上下の樹脂連結面積が大きく取れ、樹脂の
硬化収縮力によるリード／チップ間への圧縮力を高める
ことができるため、Ａｌ電極／Ａｕボール／リード端子
の各接合部の熱歪み等による破損を低減することがで
き、半導体パッケージの信頼性を向上することができ
る。According to this embodiment, in addition to obtaining the same effects as in FIG. 2, since the lead terminals are protruded from only one side,
Since the resin connecting area above and below the lead terminal can be increased, and the compressive force between the lead and the chip due to the curing shrinkage force of the resin can be increased, the thermal distortion of each joint of the Al electrode / Au ball / lead terminal can be caused. Breakage can be reduced, and the reliability of the semiconductor package can be improved.

【００５８】図１７は、本発明による半導体パッケージ
において、リード端子の一部が樹脂匡体の上面に露出し
ている場合の一実施例を示す。図において、チップ１４
５のＡｌ電極１４６にはＡｕボール１５４が形成され、
裏面電極１４７の最表面にはＡｇ蒸着膜が形成されてい
る。リード端子１５０とダイ端子１５３の表面にはＰｄ
／Ａｕめっき１４９，１５２が施されている。チップ裏
面とダイ端子間には溝１５６を形成したＡｇシート１５
５が挿入されている。各接合部は、超音波併用の加熱圧
着によりダイレクトに接合されている。リード端子は、
樹脂匡体の１側面から導出されて曲げ加工されており、
上面はリード端子が露出している。FIG. 17 shows an embodiment in which a part of the lead terminals is exposed on the upper surface of the resin housing in the semiconductor package according to the present invention. In the figure, chip 14
The Au ball 154 is formed on the Al electrode 146 of No. 5,
An Ag vapor deposition film is formed on the outermost surface of the back electrode 147. Pd is applied to the surfaces of the lead terminal 150 and the die terminal 153.
/ Au plating 149, 152 is applied. Ag sheet 15 with groove 156 formed between chip back surface and die terminal
5 has been inserted. Each joint is directly joined by thermocompression bonding using ultrasonic waves. The lead terminals are
It is drawn out from one side of the resin housing and bent.
The lead terminals are exposed on the upper surface.

【００５９】本実施例によれば、図２と同様の効果が得
られる他に、パッケージ上面に露出した広い面積のリー
ド端子から効率よく熱が放散されるため、半導体パッケ
ージの熱抵抗を大幅に低減することができる。According to this embodiment, in addition to obtaining the same effects as in FIG. 2, heat is efficiently dissipated from the lead terminals having a large area exposed on the upper surface of the package, so that the thermal resistance of the semiconductor package is greatly reduced. Can be reduced.

【００６０】図１８は、本発明による半導体パッケージ
を搭載するための配線基板の一実施例を示す。図におい
て、配線基板１６０はガラスエポキシシートにＣｕ箔パ
ターンが形成された基板を積層した多層有機基板であ
る。基板表面には、各種半導体パッケージや受動素子の
接続端子１６５，１６９，１７０，１７１が形成されて
いる。本発明の半導体パッケージを搭載するための接続
端子は、パッケージの腹部に納まる大きさのドレイン用
接続端子１６１，１６８，ソース用接続端子164,１６
７，ゲート用接続端子１６２，１６３，１６６から構成
される。図１９は、図１８の配線基板に、本発明の半導
体パッケージやＬＳＩパッケージや素子を搭載した電子
装置の一実施例を示す。図において、配線基板１６０に
は信号処理用のＬＳＩパッケージ１７６，１７７，１７
８と縦型半導体パッケージ１７２，１７５と抵抗及びコ
ンデンサの受動素子１７３，１７４が半田接続により搭
載されている。FIG. 18 shows an embodiment of a wiring board for mounting a semiconductor package according to the present invention. In the figure, a wiring board 160 is a multilayer organic board in which a board in which a Cu foil pattern is formed on a glass epoxy sheet is laminated. Connection terminals 165, 169, 170, 171 for various semiconductor packages and passive elements are formed on the surface of the substrate. The connection terminals for mounting the semiconductor package of the present invention include drain connection terminals 161 and 168 and source connection terminals 164 and 16 which are large enough to fit in the abdomen of the package.
7, gate connection terminals 162, 163 and 166. FIG. 19 shows an embodiment of an electronic device in which the semiconductor package, the LSI package, and the element of the present invention are mounted on the wiring board of FIG. In the figure, a wiring board 160 includes LSI packages 176, 177, and 17 for signal processing.
8, vertical semiconductor packages 172 and 175, and passive elements 173 and 174 of resistors and capacitors are mounted by soldering.

【００６１】本実施例によれば、パワー半導体パッケー
ジと基板間の接続面積が大きく、発熱体であるチップと
基板間が最短距離で接続されるため、基板とパッケージ
の温度差が小さくなり、半田接続部に発生する応力が低
減されて信頼性の高い電子装置を提供することができ
る。また、パッケージの発熱を低減しているため、特別
な放熱機構を設けなくてもデバイス温度が正常な動作温
度領域を超えて温度上昇することがなく、電子装置の構
造を簡略化できてコストを抑えられ、温度上昇が低くな
ることから電子装置の寿命を向上できるという効果もあ
る。According to the present embodiment, the connection area between the power semiconductor package and the substrate is large, and the chip, which is a heating element, and the substrate are connected with the shortest distance. It is possible to provide a highly reliable electronic device in which stress generated in the connection portion is reduced. Also, since the heat generation of the package is reduced, the device temperature does not rise beyond the normal operating temperature range without providing a special heat radiation mechanism, and the structure of the electronic device can be simplified and the cost can be reduced. Since the temperature rise is suppressed and the temperature rise is reduced, there is also an effect that the life of the electronic device can be improved.

【００６２】[0062]

【発明の効果】以上詳述したように、本発明によれば、
パッケージの実装抵抗を低減することができる。As described in detail above, according to the present invention,
The mounting resistance of the package can be reduced.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明による半導体パッケージの一実施例。FIG. 1 shows an embodiment of a semiconductor package according to the present invention.

【図２】本発明による半導体パッケージの他の一実施
例。FIG. 2 shows another embodiment of the semiconductor package according to the present invention.

【図３】本発明による半導体パッケージの他の一実施
例。FIG. 3 is another embodiment of the semiconductor package according to the present invention.

【図４】本発明による半導体パッケージの他の一実施
例。FIG. 4 shows another embodiment of the semiconductor package according to the present invention.

【図５】本発明による半導体パッケージに用いるリード
フレームの一実施例。FIG. 5 is an embodiment of a lead frame used for a semiconductor package according to the present invention.

【図６】本発明による半導体パッケージの組み立て構造
及び方法の一実施例。FIG. 6 shows an embodiment of a semiconductor package assembly structure and method according to the present invention.

【図７】本発明による半導体パッケージの組み立て途中
のリードフレーム構造。FIG. 7 is a lead frame structure during the assembly of a semiconductor package according to the present invention.

【図８】本発明による半導体パッケージの樹脂モールド
方法の一実施例。FIG. 8 shows an embodiment of a resin molding method for a semiconductor package according to the present invention.

【図９】本発明による半導体パッケージの組み立てフロ
ーの一実施例。FIG. 9 is an embodiment of an assembling flow of a semiconductor package according to the present invention.

【図１０】本発明によるＰｂレス半導体パッケージの組
み立て構造の一実施例。FIG. 10 is an embodiment of an assembly structure of a Pb-less semiconductor package according to the present invention.

【図１１】本発明によるＰｂレス半導体パッケージの一
実施例。FIG. 11 shows an embodiment of a Pb-less semiconductor package according to the present invention.

【図１２】本発明によるチップ裏面電極のＰｂレス接合
部材の一実施例。FIG. 12 shows an embodiment of a Pb-less joining member for a chip back electrode according to the present invention.

【図１３】本発明によるチップ裏面電極のＰｂレス接合
部材の他の一実施例。FIG. 13 shows another embodiment of the Pb-less joining member of the chip back surface electrode according to the present invention.

【図１４】本発明によるチップ裏面電極のＰｂレス接合
部材の他の一実施例。FIG. 14 shows another embodiment of the Pb-less joining member of the chip back surface electrode according to the present invention.

【図１５】本発明による半導体パッケージの他の一実施
例。FIG. 15 shows another embodiment of the semiconductor package according to the present invention.

【図１６】本発明による半導体パッケージの他の一実施
例。FIG. 16 shows another embodiment of the semiconductor package according to the present invention.

【図１７】本発明による半導体パッケージの他の一実施
例。FIG. 17 shows another embodiment of the semiconductor package according to the present invention.

【図１８】本発明による半導体パッケージを搭載する配
線基板の一実施例。FIG. 18 shows an embodiment of a wiring board on which a semiconductor package according to the present invention is mounted.

【図１９】本発明による半導体パッケージを搭載した電
子装置の一実施例。FIG. 19 is an embodiment of an electronic device equipped with a semiconductor package according to the present invention.

【図２０】半導体パッケージの電流経路モデル。FIG. 20 is a current path model of a semiconductor package.

【図２１】本発明の半導体パッケージの基本構造の一
例。FIG. 21 is an example of a basic structure of a semiconductor package of the present invention.

【符号の説明】[Explanation of symbols]

１，２１，３５，５０，６５，９７，１２０，１３０，
１４５，１９０…半導体チップ、２…ソース用Ａｌ電
極、３…ゲート用Ａｌ電極、４，３７，５３，６８，１
０２，１２２，１３２，１４７，１９２…裏面電極、５
…ソース用リード端子、６…ゲート用リード端子、７，
６９…ドレイン用ダイ端子、８，３０，４５，５７，７
１，１３９，１５４…Ａｕバンプ、９…開口部、１０…
スリット、１１，１３，２４，２７，３８，４１，１３
４，１３７，１４８，１５１…Ｃｕコア、１２，１４，
４２，１４９，１５２…Ｐｄ／Ａｕめっき、１５…Ａｇ
めっき、１６，３２，４７，５９，１０３，１２８，１
４２，１５７，１９７…樹脂匡体、２２，３６，６６，
６７，９８，９９，１２１，１３１，１４６，１８１，
１９１…Ａｌ電極、２５，２８，３９…貴金属めっき、
２６，４０，１３５，１５０…リード端子、２９，４
３，１２４，１３８，１５３…ダイ端子、３１，７０，
１２５…Ａｇバンプ、４４…ザグリ加工部、４６…Ａｇ
ペースト、５１…主電流用Ａｌ電極、５２…制御用Ａｌ
電極、５４…裏面電極用外部接続端子、５５…主電流用
外部接続端子、５６…制御用外部接続端子、５８…Ａｇ
メッシュシート、６１，９１…ソース用リード、６２，
９２…ゲート用リード、６３…リード吊、６４，９４，
９６…リード枠、７３…接合ツール、７４…ヒートステ
ージ、７５…ヒータ、７６…超音波振動、８０…モール
ド上金型、８１…モールド下金型、８２…キャビティ、
８３…逃げ空間、９３…ネック部、９５…ドレイン用ダ
イ、１００…Ａｕボールバンプ、１０１…Ａｇボールバ
ンプ、104…ドレイン用リード、１１０，１４０，１５
５…Ａｇシート、１１１，１４１，１５６…溝、１１２
…Ａｇコア、１１３…Ｓｎめっき、１１４，１１５…Ａ
ｇワイヤ、１２３…リード、１２６…Ａｇ粒子、１２７
…樹脂、１３３，１３６…Ｐｄめっき、１６０…多層有
機基板、１６１，１６８…ドレイン用接続端子、１６
２、１６３，１６６…ゲート用接続端子、１６４，１６
７…ソース用接続端子、１６５…受動素子用接続端子、
１６９，１７０，１７１…ＬＳＩパッケージ用接続端
子、１７２，１７５…縦型半導体パッケージ、１７３…
抵抗素子、174…コンデンサ素子、１７６,１７７,１７
８…ＬＳＩパッケージ、１８０…チップ、１８２…チッ
プ裏面電極、１８３…ソース用外部接続端子、１８４…
ドレイン用外部接続端子、１８５…金属バンプ、１８６
…接合部、１９３…第２外部接続端子、１９４…第１外
部接続端子、１９５…貴金属バンプ、１９６…貴金属接
合部材、１９８…第３外部接続端子。1, 21, 35, 50, 65, 97, 120, 130,
145, 190: semiconductor chip, 2: Al electrode for source, 3: Al electrode for gate, 4, 37, 53, 68, 1
02, 122, 132, 147, 192 ... back electrode, 5
... lead terminal for source, 6 ... lead terminal for gate, 7,
69 ... Die terminal for drain, 8, 30, 45, 57, 7
1,139,154: Au bump, 9: Opening, 10 ...
Slits, 11, 13, 24, 27, 38, 41, 13
4,137,148,151 ... Cu core, 12,14,
42, 149, 152: Pd / Au plating, 15: Ag
Plating, 16, 32, 47, 59, 103, 128, 1
42,157,197 ... Resin housing, 22,36,66,
67, 98, 99, 121, 131, 146, 181,
191 ... Al electrode, 25,28,39 ... noble metal plating,
26, 40, 135, 150 ... lead terminal, 29, 4
3, 124, 138, 153 ... die terminal, 31, 70,
125: Ag bump, 44: Counterbored part, 46: Ag
Paste, 51: Al electrode for main current, 52: Al for control
Electrodes, 54: External connection terminal for back electrode, 55: External connection terminal for main current, 56: External connection terminal for control, 58: Ag
Mesh sheet, 61, 91 ... lead for source, 62,
92: gate lead, 63: lead suspension, 64, 94,
Reference numeral 96: lead frame, 73: joining tool, 74: heat stage, 75: heater, 76: ultrasonic vibration, 80: upper mold, 81: lower mold, 82: cavity,
83: Escape space, 93: Neck, 95: Die for drain, 100: Au ball bump, 101: Ag ball bump, 104: Lead for drain, 110, 140, 15
5: Ag sheet, 111, 141, 156: groove, 112
... Ag core, 113 ... Sn plating, 114,115 ... A
g wire, 123 ... lead, 126 ... Ag particle, 127
... Resin, 133,136 ... Pd plating, 160 ... Multilayer organic substrate, 161,168 ... Drain connection terminal, 16
2, 163, 166: gate connection terminal, 164, 16
7 Connection terminal for source, 165 Connection terminal for passive element,
169, 170, 171 ... Connection terminals for LSI package, 172, 175 ... Vertical semiconductor package, 173 ...
Resistance element, 174 ... Capacitor element, 176,177,17
8 LSI package, 180 chip, 182 chip back electrode, 183 external connection terminal for source, 184
External connection terminal for drain, 185 ... metal bump, 186
.., Junction 193, second external connection terminal, 194, first external connection terminal, 195, noble metal bump, 196, noble metal bonding member, 198, third external connection terminal.

───────────────────────────────────────────────────── フロントページの続き (72)発明者 小泉 正博 茨城県日立市大みか町七丁目１番１号 株 式会社日立製作所日立研究所内 (72)発明者 守田 俊章 茨城県日立市大みか町七丁目１番１号 株 式会社日立製作所日立研究所内 (72)発明者 高橋 和弥 茨城県日立市大みか町七丁目１番１号 株 式会社日立製作所日立研究所内 (72)発明者 岸本 宗久 東京都小平市上水本町五丁目20番１号 株 式会社日立製作所半導体事業部内 (72)発明者 石井 滋 東京都小平市上水本町五丁目20番１号 株 式会社日立製作所半導体事業部内 (72)発明者 平島 利宣 東京都小平市上水本町五丁目20番１号 株 式会社日立製作所半導体事業部内 (72)発明者 高橋 靖司 東京都小平市上水本町五丁目20番１号 株 式会社日立製作所半導体事業部内 (72)発明者 波多 俊幸 埼玉県入間郡毛呂山町旭台15番地 日立東 部セミコンダクタ株式会社内 (72)発明者 佐藤 仁久 埼玉県入間郡毛呂山町旭台15番地 日立東 部セミコンダクタ株式会社内 (72)発明者 大川 啓一 埼玉県入間郡毛呂山町旭台15番地 日立東 部セミコンダクタ株式会社内 Ｆターム(参考） 5F036 AA01 BB08 BB21 BC05 BD01 BE01  ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Masahiro Koizumi 7-1-1, Omikacho, Hitachi City, Ibaraki Prefecture Inside Hitachi Research Laboratory, Hitachi, Ltd. (72) Inventor Toshiaki Morita 7-1 Omikamachi, Hitachi City, Ibaraki Prefecture No. 1 Inside Hitachi, Ltd., Hitachi Research Laboratory (72) Inventor Kazuya Takahashi 7-1-1, Omika-cho, Hitachi City, Ibaraki Prefecture Inside Hitachi, Ltd., Hitachi Research Laboratory (72) Inventor Munehisa Kishimoto, Kodaira, Tokyo 5-2-1 Mizumotocho, Semiconductor Division, Hitachi, Ltd. (72) Inventor Shigeru Ishii 5-2-1-1, Kamimizuhonmachi, Kodaira City, Tokyo Semiconductor Division, Hitachi, Ltd. (72) Hirashima, Inventor Toshinori 5-20-1, Josuihonmachi, Kodaira-shi, Tokyo Inside Semiconductor Division, Hitachi, Ltd. (72) Inventor Yasushi Takahashi Kodaira, Tokyo Hitachi, Ltd.Semiconductor Division, Hitachi, Ltd. (72) Inventor Toshiyuki 15, Toroyuki, Moroma-gun, Iruma-gun, Saitama Prefecture Hitachi East Division Semiconductor Co., Ltd. (72) Inventor Yoshihisa Sato Saitama Saitama 15 Asahidai, Moroyama-cho, Iruma-gun, Hitachi (72) Inventor Keiichi Okawa 15 Asahidai, Moroyama-cho, Iruma-gun, Saitama F-term (reference) 5F036 AA01 BB08 BB21 BC05

Claims (15)

【特許請求の範囲】[Claims] 【請求項１】半導体基板と、前記半導体基板の表面に設
けられる第１の電極と、前記半導体基板の裏面に設けら
れる第２の電極とを有する半導体素子と、 前記第１の電極に接続される第１の金属部材と、 前記第２の電極に接続される第２の金属部材と、を備
え、 前記第１の電極と前記第１の金属部材とが第１の貴金属
を含む第１の金属体を介して接続され、前記第２の電極
と前記第２の金属部材とが第２の貴金属を含む第２の金
属体を介して接続されることを特徴とする半導体装置。A semiconductor element having a semiconductor substrate, a first electrode provided on a front surface of the semiconductor substrate, and a second electrode provided on a back surface of the semiconductor substrate; and a semiconductor element connected to the first electrode. A first metal member, and a second metal member connected to the second electrode, wherein the first electrode and the first metal member include a first noble metal. A semiconductor device, wherein the semiconductor device is connected via a metal body, and the second electrode and the second metal member are connected via a second metal body including a second noble metal. 【請求項２】請求項１において、外部配線と接続するた
めの前記第１の金属部材の表面部分及び前記第２の金属
部材の表面部分が略同じ平面内に位置することを特徴と
する半導体装置。2. The semiconductor device according to claim 1, wherein a surface portion of said first metal member and a surface portion of said second metal member for connecting to an external wiring are located in substantially the same plane. apparatus. 【請求項３】請求項１または２において、前記第１の金
属体が、前記第１の電極または前記第１の金属部材から
突出する突起状電極であることを特徴とする半導体装
置。3. The semiconductor device according to claim 1, wherein the first metal body is a protruding electrode projecting from the first electrode or the first metal member. 【請求項４】請求項１または２において、前記第１の金
属体が、前記第１の電極または前記第１の金属部材から
突出する複数の突起状電極であり、前記複数の突起状電
極が、前記第１の電極と前記第１の金属部材との接合界
面の略全面において、略等間隔に配列されていることを
特徴とする半導体装置。4. The method according to claim 1, wherein the first metal body is a plurality of protruding electrodes protruding from the first electrode or the first metal member, and the plurality of protruding electrodes are A semiconductor device, which is arranged at substantially equal intervals over substantially the entire bonding interface between the first electrode and the first metal member. 【請求項５】請求項１乃至４のいずれか１項において、
前記第１の金属部材の接合表面に貴金属層が設けられる
ことを特徴とする半導体装置。5. The method according to claim 1, wherein
A semiconductor device, wherein a noble metal layer is provided on a bonding surface of the first metal member. 【請求項６】請求項１または２において、前記第２の金
属体が、前記第２の電極と前記第２の金属部材との接合
界面に位置する金属層であることを特徴とする半導体装
置。6. The semiconductor device according to claim 1, wherein the second metal body is a metal layer located at a bonding interface between the second electrode and the second metal member. . 【請求項７】請求項６において、前記金属層が前記第２
の電極の接合表面側及び前記第２の金属部材の接合表面
側に位置する貴金属層が互いに接合したものであること
を特徴とする半導体装置。7. The semiconductor device according to claim 6, wherein the metal layer is the second metal layer.
A noble metal layer located on a bonding surface side of the electrode and a bonding surface side of the second metal member are bonded to each other. 【請求項８】請求項６において、前記金属層が貴金属を
主成分とする固相温度４００℃以上の合金層であること
を特徴とする半導体装置。8. The semiconductor device according to claim 6, wherein said metal layer is an alloy layer containing a noble metal as a main component and having a solid phase temperature of 400 ° C. or higher. 【請求項９】請求項１において、前記第１の金属部材
が、前記第１の電極との接合部を有する部分から延びる
複数の部分を有し、前記複数の部分の各々が、外部配線
と接続するための表面部分を有することを特徴とする半
導体装置。9. The semiconductor device according to claim 1, wherein the first metal member has a plurality of portions extending from a portion having a joint with the first electrode, and each of the plurality of portions is connected to an external wiring. A semiconductor device having a surface portion for connection. 【請求項１０】請求項３において、さらに、前記半導体
素子と前記第１及び第２の金属部材とを被覆する絶縁体
を有し、前記第１の金属部材における前記第１の電極と
の接合面の裏面が、外部配線と接続するための露出部分
を有することを特徴とする半導体装置。10. The semiconductor device according to claim 3, further comprising an insulator covering said semiconductor element and said first and second metal members, wherein said first metal member is bonded to said first electrode. A semiconductor device, wherein the back surface has an exposed portion for connecting to an external wiring. 【請求項１１】請求項１０において、前記半導体素子の
前記接合面側が回路形成面であり、前記第１の電極が主
電流電極であることを特徴とする半導体装置。11. The semiconductor device according to claim 10, wherein said bonding surface side of said semiconductor element is a circuit formation surface, and said first electrode is a main current electrode. 【請求項１２】請求項６において、さらに、前記半導体
素子と前記第１及び第２の金属部材とを被覆する絶縁体
を有し、前記第２の金属部材における前記第２の電極と
の接合面の裏面が、外部配線と接続するための露出部分
を有することを特徴とする半導体装置。12. The semiconductor device according to claim 6, further comprising an insulator covering said semiconductor element and said first and second metal members, wherein said second metal member is bonded to said second electrode. A semiconductor device, wherein the back surface has an exposed portion for connecting to an external wiring. 【請求項１３】半導体基板と、前記半導体基板の表面に
設けられる第１の電極と、前記半導体基板の裏面に設け
られる第２の電極とを有する半導体素子と、 前記第１の電極に接続される第１の金属部材と、 前記第２の電極に接続される第２の金属部材と、を備
え、 前記第２の電極と前記第２の金属部材とが貴金属を含む
金属層を介して接続され、 前記金属層が、前記第２の電極の接合表面及び前記第２
の金属部材の接合表面に設けられる貴金属層が互いに接
合したものであることを特徴とする半導体装置。13. A semiconductor element having a semiconductor substrate, a first electrode provided on a front surface of the semiconductor substrate, and a second electrode provided on a back surface of the semiconductor substrate, and a semiconductor element connected to the first electrode. A first metal member, and a second metal member connected to the second electrode, wherein the second electrode and the second metal member are connected via a metal layer containing a noble metal. Wherein the metal layer comprises a bonding surface of the second electrode and the second electrode.
Wherein the noble metal layers provided on the bonding surface of the metal member are bonded to each other. 【請求項１４】半導体基板と、前記半導体基板の表面に
設けられる第１の電極と、前記半導体基板の裏面に設け
られる第２の電極とを有する半導体素子と、 前記第１の電極に接続される第１の金属部材と、 前記第２の電極に接続される第２の金属部材と、を備
え、 前記第２の電極と前記第２の金属部材とが貴金属を含む
金属層を介して接続され、 前記金属層が、貴金属を主成分とする固相温度４００℃
以上の合金層であることを特徴とする半導体装置。14. A semiconductor element having a semiconductor substrate, a first electrode provided on a front surface of the semiconductor substrate, and a second electrode provided on a back surface of the semiconductor substrate, and a semiconductor element connected to the first electrode. A first metal member, and a second metal member connected to the second electrode, wherein the second electrode and the second metal member are connected via a metal layer containing a noble metal. The metal layer has a solid phase temperature of 400 ° C. containing a noble metal as a main component.
A semiconductor device comprising the above alloy layer. 【請求項１５】半導体基板と、前記半導体基板の表面に
設けられる第１の電極と、前記半導体基板の裏面に設け
られる第２の電極とを有する半導体素子と、 前記第１の電極に接続される第１の金属部材と、 前記第２の電極に接続される第２の金属部材と、を備
え、 前記第１の金属部材が、前記第１の電極との接合部から
延びる複数の部分を有し、前記複数の部分の各々が、外
部配線と接続するための表面部分を有することを特徴と
する半導体装置。15. A semiconductor element having a semiconductor substrate, a first electrode provided on a front surface of the semiconductor substrate, and a second electrode provided on a back surface of the semiconductor substrate, and a semiconductor element connected to the first electrode. A first metal member, and a second metal member connected to the second electrode, wherein the first metal member includes a plurality of portions extending from a joint with the first electrode. A semiconductor device, wherein each of the plurality of portions has a surface portion for connecting to an external wiring.
JP01943199A 1999-01-28 1999-01-28 Semiconductor device Expired - Fee Related JP4260263B2 (en)

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JP01943199A JP4260263B2 (en) 1999-01-28 1999-01-28 Semiconductor device
KR1020000003672A KR20000057810A (en) 1999-01-28 2000-01-26 Semiconductor device
DE10003671A DE10003671A1 (en) 1999-01-28 2000-01-28 Semiconductor component, especially a surface mountable semiconductor package, has front and back face electrodes connected to metal parts by precious metal-containing bodies or layers
US09/493,080 US6774466B1 (en) 1999-01-28 2000-01-28 Semiconductor device
US10/758,396 US20040150082A1 (en) 1999-01-28 2004-01-16 Semiconductor device
US10/855,432 US20040217474A1 (en) 1999-01-28 2004-05-28 Semiconductor device
US11/415,291 US7332757B2 (en) 1999-01-28 2006-05-02 MOSFET package
US11/415,290 US7342267B2 (en) 1999-01-28 2006-05-02 MOSFET package
US11/543,030 US20070029540A1 (en) 1999-01-28 2006-10-05 Semiconductor device
US11/589,895 US20070040250A1 (en) 1999-01-28 2006-10-31 Semiconductor device
US11/589,847 US7400002B2 (en) 1999-01-28 2006-10-31 MOSFET package
US11/589,849 US7394146B2 (en) 1999-01-28 2006-10-31 MOSFET package
US12/046,741 US7985991B2 (en) 1999-01-28 2008-03-12 MOSFET package
US13/189,883 US8183607B2 (en) 1999-01-28 2011-07-25 Semiconductor device
US13/459,839 US8455986B2 (en) 1999-01-28 2012-04-30 Mosfet package
US13/906,771 US8816411B2 (en) 1999-01-28 2013-05-31 Mosfet package

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JP2003086737A (en) * 2001-09-11 2003-03-20 Toshiba Corp Semiconductor device
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JP2006520103A (en) * 2003-03-10 2006-08-31 フェアチャイルド・セミコンダクター・コーポレーション Flip chip coated metal stud bumps made of coated wire
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