JP2001339057A - Method of manufacturing three-dimensional image processor - Google Patents
Method of manufacturing three-dimensional image processorInfo
- Publication number
- JP2001339057A JP2001339057A JP2000160330A JP2000160330A JP2001339057A JP 2001339057 A JP2001339057 A JP 2001339057A JP 2000160330 A JP2000160330 A JP 2000160330A JP 2000160330 A JP2000160330 A JP 2000160330A JP 2001339057 A JP2001339057 A JP 2001339057A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- dimensional image
- embedded wiring
- image processing
- electrically connected
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 41
- 239000000758 substrate Substances 0.000 claims abstract description 189
- 238000000034 method Methods 0.000 claims abstract description 32
- 238000006243 chemical reaction Methods 0.000 claims description 82
- 230000003321 amplification Effects 0.000 claims description 38
- 238000003199 nucleic acid amplification method Methods 0.000 claims description 38
- 238000013500 data storage Methods 0.000 claims description 37
- 238000005498 polishing Methods 0.000 claims description 21
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 28
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 23
- 229910052710 silicon Inorganic materials 0.000 abstract description 23
- 239000010703 silicon Substances 0.000 abstract description 23
- 239000003822 epoxy resin Substances 0.000 abstract description 5
- 229920000647 polyepoxide Polymers 0.000 abstract description 5
- 239000000853 adhesive Substances 0.000 abstract description 2
- 230000001070 adhesive effect Effects 0.000 abstract description 2
- 229920001721 polyimide Polymers 0.000 abstract description 2
- 239000009719 polyimide resin Substances 0.000 abstract description 2
- 239000002861 polymer material Substances 0.000 abstract description 2
- 239000004065 semiconductor Substances 0.000 description 30
- 239000010408 film Substances 0.000 description 28
- 239000010410 layer Substances 0.000 description 27
- 239000012535 impurity Substances 0.000 description 15
- 235000012239 silicon dioxide Nutrition 0.000 description 12
- 239000000377 silicon dioxide Substances 0.000 description 12
- 229910052782 aluminium Inorganic materials 0.000 description 8
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 8
- 239000004020 conductor Substances 0.000 description 7
- 238000002955 isolation Methods 0.000 description 6
- 239000013078 crystal Substances 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 4
- 229910052721 tungsten Inorganic materials 0.000 description 4
- 239000010937 tungsten Substances 0.000 description 4
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 3
- 230000000149 penetrating effect Effects 0.000 description 3
- 239000010409 thin film Substances 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- 239000004850 liquid epoxy resins (LERs) Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 229910001020 Au alloy Inorganic materials 0.000 description 1
- 229910000846 In alloy Inorganic materials 0.000 description 1
- 102000004129 N-Type Calcium Channels Human genes 0.000 description 1
- 108090000699 N-Type Calcium Channels Proteins 0.000 description 1
- 235000010724 Wisteria floribunda Nutrition 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 238000009616 inductively coupled plasma Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000001953 recrystallisation Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0232—Optical elements or arrangements associated with the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14625—Optical elements or arrangements associated with the device
- H01L27/14627—Microlenses
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14634—Assemblies, i.e. Hybrid structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、３次元画像処理装
置の製造方法に関する。The present invention relates to a method for manufacturing a three-dimensional image processing apparatus.
【０００２】[0002]
【従来の技術】近年、半導体集積回路装置の高集積化・
高密度化等の目的から、複数の回路機能ブロックを立体
的に集積した３次元半導体集積回路装置の開発が進めら
れている。特に、イメージセンサとその信号を処理する
ための信号処理回路を一体化した３次元画像処理装置
（インテリジェントイメージプロセッサ）は、光センサ
から得られる画像データを並列に高速処理し、高画質画
像をリアルタイムで得ることが可能になることから、多
くの期待が寄せられている。2. Description of the Related Art In recent years, high integration of semiconductor integrated circuit devices has been realized.
For the purpose of higher density and the like, development of a three-dimensional semiconductor integrated circuit device in which a plurality of circuit function blocks are three-dimensionally integrated has been promoted. In particular, a three-dimensional image processing device (intelligent image processor) that integrates an image sensor and a signal processing circuit for processing the signal thereof performs high-speed processing of image data obtained from an optical sensor in parallel, and outputs a high-quality image in real time. There are a lot of expectations that it will be available at
【０００３】これら３次元半導体集積回路装置は、当初
はレ−ザ再結晶化等によるＳＯＩ（Silicon On Insulat
or）技術を利用してＳＯＩ基板形成とＳＯＩ基板への半
導体装置の形成を繰り返すモノリシック法によりその製
造が検討されてきたが、ＳＯＩを多層に積層するには、
結晶性の確保が難しい、製造時間が長い等の問題があっ
た。[0003] Initially, these three-dimensional semiconductor integrated circuit devices are manufactured by SOI (Silicon On Insulat) by laser recrystallization or the like.
or) A monolithic method of repeating formation of an SOI substrate and formation of a semiconductor device on the SOI substrate using technology has been studied. However, in order to stack SOI in multiple layers,
There are problems such as difficulty in securing crystallinity and long manufacturing time.
【０００４】このため、半導体装置または半導体集積回
路装置が予め作製された単結晶半導体基板同士を貼り合
わせる貼り合わせ技術による３次元半導体集積回路装置
の製造方法が種々検討されている。[0004] For this reason, various methods of manufacturing a three-dimensional semiconductor integrated circuit device by a bonding technique of bonding single crystal semiconductor substrates in which a semiconductor device or a semiconductor integrated circuit device has been manufactured in advance have been studied.
【０００５】月刊セミコンダクターワールド（林善宏
等、１９９０年９月号ｐ５８〜６４）には、貼り合わせ
技術の一種として、研磨により薄膜化した半導体基板を
貼り合わせるＣＵＢＩＣ技術が提案されている。ＣＵＢ
ＩＣ技術では、まずシリコン基板上に半導体素子が形成
された第１の半導体基板を支持基板に接着した後、余分
なシリコン基板をポリッシングして薄膜化する。次に、
埋め込み配線、裏面配線、バンプ／プールからなるコン
タクト部材等のデバイスの縦方向の接続に必要な配線を
形成し、第１の半導体基板とシリコン基板上に半導体素
子の形成された第２の半導体基板とを貼り合わせる。そ
して最後に支持基板を取り外して多層構造の半導体装置
が完成する。[0005] Monthly Semiconductor World (Yoshihiro Hayashi et al., September 1990, pp. 58-64) proposes a CUBIC technology for bonding a semiconductor substrate thinned by polishing as a kind of bonding technology. CUB
In the IC technology, first, a first semiconductor substrate having a semiconductor element formed on a silicon substrate is bonded to a supporting substrate, and then an excess silicon substrate is polished to reduce the thickness. next,
A second semiconductor substrate on which a semiconductor element is formed on a first semiconductor substrate and a silicon substrate by forming wiring necessary for vertical connection of devices, such as a buried wiring, a back wiring, and a contact member including a bump / pool; And stick them together. Finally, the support substrate is removed to complete a semiconductor device having a multilayer structure.
【０００６】また、特開平６−２６０５９４号公報に
は、貼り合わせ技術による３次元半導体集積回路装置の
製造方法が開示されている。この方法は、シリコン基板
上に半導体素子が形成された第１の半導体基板を支持基
板に接着した後、余分なシリコン基板をポリッシングし
て薄膜化する点はＣＵＢＩＣ技術と共通しているが、第
１の半導体基板に予め埋め込み配線を形成するための深
溝が設けられている点、及び第１の半導体基板とシリコ
ン基板上に半導体素子の形成された第２の半導体基板と
を貼り合わせ、貼り合わせ後に支持基板を取り除き埋め
込み配線を形成する点で、ＣＵＢＩＣ技術とは異なって
いる。Japanese Unexamined Patent Publication No. Hei 6-260594 discloses a method for manufacturing a three-dimensional semiconductor integrated circuit device by a bonding technique. This method is similar to the CUBIC technology in that a first semiconductor substrate having a semiconductor element formed on a silicon substrate is bonded to a support substrate, and then an excess silicon substrate is polished to a thin film. A point in which a deep groove for previously forming an embedded wiring is provided in one semiconductor substrate, and a first semiconductor substrate and a second semiconductor substrate having a semiconductor element formed on a silicon substrate are bonded to each other. This is different from the CUBIC technology in that the supporting substrate is later removed to form the embedded wiring.
【０００７】[0007]
【発明が解決しようとする課題】しかしながら、いずれ
の製造方法も、第１の半導体基板を支持基板に貼り合わ
せ、研磨した後に支持基板から第１の半導体基板を剥離
する工程を含んでおり、製造工程が煩雑であるという問
題があった。特に、３次元画像処理装置を製造する場合
には、支持基板を取り除いた後にその表面にイメージセ
ンサを構成するマイクロレンズを備えた透明基板を設け
る必要があるため、なおさら製造工程が煩雑になる。However, any of the manufacturing methods includes a step of attaching the first semiconductor substrate to the supporting substrate, polishing the resultant, and then peeling the first semiconductor substrate from the supporting substrate. There is a problem that the process is complicated. In particular, in the case of manufacturing a three-dimensional image processing apparatus, it is necessary to provide a transparent substrate provided with a microlens constituting an image sensor on the surface after removing the supporting substrate, which further complicates the manufacturing process.
【０００８】また、ＣＵＢＩＣ技術では、余分なシリコ
ン基板をポリッシングして薄膜化した後に支持基板を取
り除くため、支持基板を取り除く際に半導体基板上に形
成された集積回路が破損するという問題があった。In addition, in the CUBIC technique, since an excess silicon substrate is polished and thinned by polishing to remove the support substrate, there is a problem that an integrated circuit formed on the semiconductor substrate is damaged when the support substrate is removed. .
【０００９】また、特開平６−２６０５９４号公報に記
載された方法では、埋め込み配線を形成するための深溝
が予め設けられた第１の半導体基板を支持基板に接着す
るため、深溝に入り込んだ接着剤の除去が困難であると
いう問題や、第１の半導体基板と第２の半導体基板とを
接着した後に深溝の側壁を酸化して絶縁膜を形成するた
め、接着剤の耐熱温度以上に酸化温度を上げることがで
きず、信頼性のある絶縁膜を形成することができないと
いう問題があった。In the method described in JP-A-6-260594, a first semiconductor substrate provided with a deep groove for forming a buried wiring is bonded to a supporting substrate. The problem is that it is difficult to remove the agent. Also, since the first semiconductor substrate and the second semiconductor substrate are bonded to each other, the sidewalls of the deep groove are oxidized to form an insulating film. Therefore, there is a problem that a reliable insulating film cannot be formed.
【００１０】本発明は上記従来技術の問題点に鑑みなさ
れたものであり、本発明の目的は、支持基板の着脱工程
が不要で製造工程を大幅に簡略化することができ、簡素
かつ容易な工程により３次元画像処理装置を製造するこ
とができる３次元画像処理装置の製造方法を提供するこ
とにある。また、本発明の他の目的は、信頼性の高い絶
縁膜で囲まれた埋め込み配線を形成することができる３
次元画像処理装置の製造方法を提供することにある。The present invention has been made in view of the above-mentioned problems of the prior art, and an object of the present invention is to eliminate the step of attaching and detaching a support substrate, greatly simplifying the manufacturing process, and making the method simple and easy. It is an object of the present invention to provide a method for manufacturing a three-dimensional image processing apparatus that can manufacture a three-dimensional image processing apparatus by a process. Another object of the present invention is to form a buried wiring surrounded by a highly reliable insulating film.
An object of the present invention is to provide a method for manufacturing a three-dimensional image processing apparatus.
【００１１】[0011]
【課題を解決するための手段】上記目的を達成するため
に、請求項１に記載の３次元画像処理装置の製造方法
は、光を集光するレンズを備えた透明基板と、主面に光
電変換素子が形成されると共に該光電変換素子に電気的
に接続された埋め込み配線が形成された光電変換基板と
を、透明基板の裏面と光電変換基板の主面とが対向する
ように接着して、３次元画像処理装置を製造することを
特徴とする。According to a first aspect of the present invention, there is provided a method of manufacturing a three-dimensional image processing apparatus, comprising: a transparent substrate having a lens for condensing light; The photoelectric conversion substrate, on which the conversion element is formed and the embedded wiring electrically connected to the photoelectric conversion element is formed, is bonded so that the back surface of the transparent substrate and the main surface of the photoelectric conversion substrate face each other. A three-dimensional image processing apparatus is manufactured.
【００１２】請求項１の発明では、支持基板等を用いる
ことなく、光を集光するレンズを備えた透明基板と、主
面に光電変換素子が形成されると共に該光電変換素子に
電気的に接続された埋め込み配線が形成された光電変換
基板とを、透明基板の裏面と光電変換基板の主面とが対
向するように接着するため、透明基板をそのままイメー
ジセンサの透明基板として使用することができ、支持基
板への接着工程、支持基板からの除去工程、及び透明基
板の形成工程が不要であり、３次元画像処理装置の製造
工程を大幅に簡略化することができる。また、光電変換
基板に埋め込み配線を形成した後に透明基板と貼り合わ
せるため、信頼性の高い絶縁膜で囲まれた埋め込み配線
を形成することができる。According to the first aspect of the present invention, a transparent substrate provided with a lens for condensing light, a photoelectric conversion element is formed on a main surface, and the photoelectric conversion element is electrically connected to the transparent substrate without using a support substrate or the like. Since the photoelectric conversion substrate on which the connected embedded wiring is formed is bonded so that the back surface of the transparent substrate and the main surface of the photoelectric conversion substrate face each other, the transparent substrate can be used as it is as the transparent substrate of the image sensor. Therefore, the step of bonding to the support substrate, the step of removing from the support substrate, and the step of forming the transparent substrate are unnecessary, and the manufacturing process of the three-dimensional image processing apparatus can be greatly simplified. Further, since the embedded wiring is formed on the photoelectric conversion substrate and then bonded to the transparent substrate, the embedded wiring surrounded by a highly reliable insulating film can be formed.
【００１３】請求項２に記載の３次元画像処理装置の製
造方法は、請求項１の発明において、前記光電変換基板
の裏面側を研磨して前記埋め込み配線を露出させ、該光
電変換基板の裏面に、主面に増幅器及びアナログ／デジ
タル変換器が形成されると共に該増幅器及びアナログ／
デジタル変換器に電気的に接続された埋め込み配線が形
成された増幅変換基板を、該増幅器及びアナログ／デジ
タル変換器が前記埋め込み配線の露出部に電気的に接続
されるように接着して、３次元画像処理装置を製造する
ことを特徴とする。According to a second aspect of the present invention, in the method for manufacturing a three-dimensional image processing apparatus according to the first aspect, the back surface of the photoelectric conversion substrate is polished to expose the embedded wiring, and the back surface of the photoelectric conversion substrate is exposed. An amplifier and an analog / digital converter are formed on the main surface, and the amplifier and the analog / digital
An amplification conversion board having an embedded wiring electrically connected to the digital converter is adhered so that the amplifier and the analog / digital converter are electrically connected to the exposed portion of the embedded wiring. A three-dimensional image processing apparatus is manufactured.
【００１４】請求項２の発明によれば、透明基板及び光
電変換基板からなるイメージセンサ部に、研磨及び接着
という簡素かつ容易な工程により、増幅器及びアナログ
／デジタル変換器に電気的に接続された埋め込み配線が
形成された増幅変換基板を積層した３次元画像処理装置
を製造することができる。According to the second aspect of the present invention, the image sensor section including the transparent substrate and the photoelectric conversion substrate is electrically connected to the amplifier and the analog / digital converter by simple and easy steps of polishing and bonding. It is possible to manufacture a three-dimensional image processing apparatus in which amplification conversion substrates on which embedded wiring is formed are stacked.
【００１５】請求項３に記載の３次元画像処理装置の製
造方法は、請求項２の発明において、前記増幅変換基板
の裏面側を研磨して前記埋め込み配線を露出させ、 該
増幅変換基板の裏面に、主面にデータ記憶装置が形成さ
れると共に該データ記憶装置に電気的に接続された埋め
込み配線が形成されたデータ記憶基板を、該データ記憶
装置が前記埋め込み配線の露出部に電気的に接続される
ように接着して、３次元画像処理装置を製造することを
特徴とする。According to a third aspect of the present invention, in the method for manufacturing a three-dimensional image processing apparatus according to the second aspect of the present invention, the back side of the amplification conversion board is polished to expose the embedded wiring. A data storage substrate having a data storage device formed on the main surface and having a buried wiring electrically connected to the data storage device formed thereon is electrically connected to an exposed portion of the buried wiring by the data storage device. The three-dimensional image processing apparatus is manufactured by bonding so as to be connected.
【００１６】請求項３の発明によれば、透明基板及び光
電変換基板からなるイメージセンサ部に研磨と接着とに
より増幅変換基板が形成された積層体に、研磨及び接着
という簡素かつ容易な工程により、主面に記憶装置が形
成されると共にデータ記憶装置に電気的に接続された埋
め込み配線が形成されたデータ記憶基板を積層した３次
元画像処理装置を製造することができる。According to the third aspect of the present invention, the laminate in which the amplification conversion substrate is formed by polishing and bonding to the image sensor portion including the transparent substrate and the photoelectric conversion substrate is formed by a simple and easy process of polishing and bonding. In addition, it is possible to manufacture a three-dimensional image processing apparatus in which a data storage substrate on which a storage device is formed on a main surface and on which a buried wiring electrically connected to the data storage device is formed is stacked.
【００１７】請求項４に記載の３次元画像処理装置の製
造方法は、請求項２の発明において、前記データ記憶基
板の裏面側を研磨して前記埋め込み配線を露出させ、該
データ記憶基板の裏面に、主面にデータ処理装置が形成
されると共に該データ処理装置に電気的に接続された埋
め込み配線が形成されたデータ処理基板を、該データ処
理装置が前記埋め込み配線の露出部に電気的に接続され
るように接着して、３次元画像処理装置を製造すること
を特徴とする。According to a fourth aspect of the present invention, in the method for manufacturing a three-dimensional image processing apparatus according to the second aspect, the back side of the data storage substrate is polished to expose the embedded wiring, and the back surface of the data storage substrate is exposed. A data processing board formed with a data processing device on the main surface and having an embedded wiring electrically connected to the data processing device, the data processing device electrically connecting the exposed portion of the embedded wiring to the data processing substrate. The three-dimensional image processing apparatus is manufactured by bonding so as to be connected.
【００１８】請求項４の発明によれば、透明基板及び光
電変換基板からなるイメージセンサ部に研磨と接着とに
より増幅変換基板及びデータ記憶基板が形成された積層
体に、研磨及び接着という簡素かつ容易な工程により、
主面にデータ処理装置が形成されると共に該データ処理
装置に電気的に接続された埋め込み配線が形成されたデ
ータ処理基板を積層した３次元画像処理装置を製造する
ことができる。According to the fourth aspect of the present invention, the laminated body in which the amplification conversion substrate and the data storage substrate are formed by polishing and bonding to the image sensor portion composed of the transparent substrate and the photoelectric conversion substrate is simply and polished and bonded. With easy process,
It is possible to manufacture a three-dimensional image processing apparatus in which a data processing apparatus is formed on the main surface and a data processing board on which a buried wiring electrically connected to the data processing apparatus is formed is stacked.
【００１９】請求項５に記載の３次元画像処理装置の製
造方法は、請求項４の発明において、前記データ処理基
板の裏面側を研磨して前記埋め込み配線を露出させ、該
データ処理基板の裏面に、主面に出力回路が形成される
と共に該出力回路に電気的に接続された埋め込み配線が
形成された出力回路基板を、該出力回路が前記埋め込み
配線の露出部に電気的に接続されるように接着して、３
次元画像処理装置を製造することを特徴とする。According to a fifth aspect of the present invention, in the method for manufacturing a three-dimensional image processing apparatus according to the fourth aspect, the back side of the data processing substrate is polished to expose the embedded wiring, and the back surface of the data processing substrate is exposed. An output circuit board on which an output circuit is formed on the main surface and on which an embedded wiring electrically connected to the output circuit is formed, wherein the output circuit is electrically connected to an exposed portion of the embedded wiring; Glued together, 3
A three-dimensional image processing apparatus is manufactured.
【００２０】請求項５の発明によれば、透明基板及び光
電変換基板からなるイメージセンサ部に研磨と接着とに
より増幅変換基板、データ記憶基板、及びデータ処理装
置が形成された積層体に、研磨及び接着という簡素かつ
容易な工程により、主面に出力回路が形成されると共に
該出力回路に電気的に接続された埋め込み配線が形成さ
れた出力回路基板を積層した３次元画像処理装置を製造
することができる。According to the fifth aspect of the present invention, the laminated body on which the amplification conversion substrate, the data storage substrate, and the data processing device are formed is polished and adhered to the image sensor portion composed of the transparent substrate and the photoelectric conversion substrate by polishing and bonding. A three-dimensional image processing apparatus in which an output circuit is formed on the main surface and an output circuit board on which a buried wiring electrically connected to the output circuit is formed by a simple and easy process of bonding. be able to.
【００２１】[0021]
【発明の実施の形態】以下、本発明の３次元画像処理装
置の製造方法を、図面を参照しつつ具体的に説明する。
図１〜図５は、本発明の３次元画像処理装置の製造方法
の各工程を示す断面図である。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a method for manufacturing a three-dimensional image processing apparatus according to the present invention will be specifically described with reference to the drawings.
1 to 5 are cross-sectional views showing each step of a method for manufacturing a three-dimensional image processing apparatus according to the present invention.
【００２２】まず、図１に示すように、光電変換基板２
０に、多数のマイクロレンズ１２が２次元状に形成され
た石英ガラス製の透明基板１０を、光電変換基板２０の
主面と透明基板１０の裏面とが対向するように、エポキ
シ樹脂やポリイミド樹脂等の高分子材料からなる接着剤
１４を介して接着する。First, as shown in FIG.
The transparent substrate 10 made of quartz glass on which a large number of microlenses 12 are formed two-dimensionally is placed on an epoxy resin or a polyimide resin so that the main surface of the photoelectric conversion substrate 20 and the back surface of the transparent substrate 10 face each other. Are bonded via an adhesive 14 made of a polymer material such as.
【００２３】上記で用いる光電変換基板２０は、内部に
ニ酸化ケイ素からなる絶縁層３６が挿入されたｎ型シリ
コン結晶基板１６上に、フォトダイオードとＭＯＳトラ
ンジスタとを形成したものである。フォトダイオード
は、光電変換基板２０のｎ型シリコン結晶基板１６上に
ｐ型不純物層１８を形成し、ｐ型不純物層１８表層のマ
イクロレンズ１２の焦点位置に対応する領域にｎ型不純
物層２２を設けることにより形成されている。また、Ｍ
ＯＳトランジスタは、ｐ型不純物層１８表層の撮像領域
以外の部分にソース及びドレインとなるｎ型不純物層２
２を設け、このｎ型不純物層２２間のｐ型不純物層１８
上に絶縁膜２４Ａにより相互に絶縁されたポリシリコン
からなるゲート電極２６を設けることにより形成されて
いる。なお、隣接するＭＯＳトランジスタはニ酸化ケイ
素からなる素子分離膜３０で分離されている。The photoelectric conversion substrate 20 used above has a structure in which a photodiode and a MOS transistor are formed on an n-type silicon crystal substrate 16 in which an insulating layer 36 made of silicon dioxide is inserted. In the photodiode, a p-type impurity layer 18 is formed on an n-type silicon crystal substrate 16 of a photoelectric conversion substrate 20, and an n-type impurity layer 22 is formed in a region corresponding to the focal position of the microlens 12 on the surface of the p-type impurity layer 18. It is formed by providing. Also, M
The OS transistor includes an n-type impurity layer 2 serving as a source and a drain in a portion of the surface layer of the p-type impurity layer 18 other than the imaging region.
2 and the p-type impurity layer 18 between the n-type impurity layers 22.
It is formed by providing a gate electrode 26 made of polysilicon which is mutually insulated by an insulating film 24A. The adjacent MOS transistors are separated by an element isolation film 30 made of silicon dioxide.
【００２４】また、光電変換基板２０には、素子分離膜
３０を貫通し光電変換基板２０の裏面に達するトレンチ
（深溝）が設けられている。なお、このようなトレンチ
は誘導結合型プラズマエッチング等により形成すること
ができる。このトレンチの内表面に絶縁膜３２が形成さ
れ、トレンチ内に導電材料が充填されて埋め込み配線３
４が形成されている。埋め込み配線３４を形成する導電
材料としては、例えば不純物をドープした低抵抗多結晶
シリコンやタングステン等の低抵抗の金属が使用され
る。The photoelectric conversion substrate 20 is provided with a trench (deep groove) that penetrates the element isolation film 30 and reaches the back surface of the photoelectric conversion substrate 20. Such a trench can be formed by inductively coupled plasma etching or the like. An insulating film 32 is formed on the inner surface of the trench, and the trench is filled with a conductive material to form a buried wiring 3.
4 are formed. As a conductive material for forming the buried wiring 34, for example, a low-resistance metal such as low-resistance polycrystalline silicon or tungsten doped with impurities is used.
【００２５】ＭＯＳトランジスタのソースとなるｎ型不
純物層２２は、例えばアルミニウムからなるソース電極
２８に接続されおり、ドレインとなるｎ型不純物層２２
は、絶縁膜２４Ｂによりソース電極２８と絶縁された例
えばアルミニウムからなるドレイン電極２９に接続され
ている。このドレイン電極２９は埋め込み配線３４に接
続されており、ゲート電極２６に所定電圧を印加するこ
とによりｎ型チャネル２２及びｐ型不純物層１８からな
るフォトダイオードに蓄積された電荷はこの埋め込み配
線３４を介して後述する増幅器へと転送される。The n-type impurity layer 22 serving as a source of the MOS transistor is connected to a source electrode 28 made of, for example, aluminum, and the n-type impurity layer 22 serving as a drain is provided.
Is connected to a drain electrode 29 made of, for example, aluminum and insulated from the source electrode 28 by the insulating film 24B. The drain electrode 29 is connected to the buried wiring 34, and when a predetermined voltage is applied to the gate electrode 26, the charges accumulated in the photodiode composed of the n-type channel 22 and the p-type impurity layer 18 cause the buried wiring 34 to be charged. The data is transferred to an amplifier described later.
【００２６】次に、図２に示すように、透明基板１０に
接着された光電変換基板２０を、化学的機械研磨により
裏面側から研磨して薄膜化する。ｎ型シリコン結晶基板
１６に挿入された絶縁層３６を構成するニ酸化ケイ素は
シリコンよりも研磨耐性が大きいため、研磨は絶縁層３
６の手前で止まり、埋め込み配線３４が絶縁層３６から
露出される。このとき透明基板１０が支持基板の役割を
果たすが、当初からマイクロレンズ１２を一体化して形
成した石英ガラス製の透明基板を用いているので後で取
り外す必要はない。Next, as shown in FIG. 2, the photoelectric conversion substrate 20 adhered to the transparent substrate 10 is polished from the back side by chemical mechanical polishing to make a thin film. Since silicon dioxide constituting the insulating layer 36 inserted into the n-type silicon crystal substrate 16 has higher polishing resistance than silicon, polishing is performed on the insulating layer 3.
6, the embedded wiring 34 is exposed from the insulating layer 36. At this time, the transparent substrate 10 plays a role of a support substrate, but it is not necessary to remove it later since a quartz glass transparent substrate formed by integrating the microlenses 12 is used from the beginning.
【００２７】以上の工程により、光を集光するレンズを
備えた透明基板１０、及び光電変換基板２０を備えたイ
メージセンサ部が完成する。Through the above steps, the transparent substrate 10 provided with a lens for condensing light and the image sensor unit provided with the photoelectric conversion substrate 20 are completed.
【００２８】次に、図３に示すように、光電変換基板２
０の裏面に、光電変換基板２０からの信号を増幅すると
共に増幅されたアナログ信号をデジタル信号に変換する
増幅変換基板４０を接着する。この増幅変換基板４０
は、内部にニ酸化ケイ素からなる絶縁層３６Ａが挿入さ
れたシリコン基板３８Ａ上に、絶縁膜４２Ａにより絶縁
されたゲート４４Ａ、ソース４６Ａ、及びドレイン４８
Ａからなる複数のＭＯＳＦＥＴ５０Ａ（本実施の形態で
は２つのＭＯＳＦＥＴを図示する）を形成したものであ
る。これら隣接するＭＯＳＦＥＴ５０Ａは、ニ酸化ケイ
素からなる素子分離膜５２Ａにより分離されている。Next, as shown in FIG.
An amplifying conversion substrate 40 that amplifies the signal from the photoelectric conversion substrate 20 and converts the amplified analog signal into a digital signal is adhered to the back surface of the “0”. This amplification conversion board 40
A gate 44A, a source 46A, and a drain 48, which are insulated by an insulating film 42A, on a silicon substrate 38A in which an insulating layer 36A made of silicon dioxide is inserted.
A plurality of MOSFETs 50A (two MOSFETs are shown in the present embodiment) are formed. These adjacent MOSFETs 50A are separated by an element isolation film 52A made of silicon dioxide.
【００２９】また、増幅変換基板４０には、この素子分
離膜５２Ａを貫通し増幅変換基板４０の裏面側表面から
回路面に達するトレンチが設けられている。このトレン
チの内表面に絶縁膜５４Ａが形成され、トレンチ内に導
電材料が充填されて埋め込み配線５６Ａが形成されてい
る。埋め込み配線５６Ａを形成する導電材料としては、
例えば不純物をドープした低抵抗多結晶シリコンやタン
グステン等の低抵抗の金属が使用される。この埋め込み
配線５６Ａの回路面側の端部にはアルミニウム配線５８
Ａが直接接続されている。これにより増幅器（アンプ）
及びアナログ／デジタル変換器（ＡＤＣ）を含む集積回
路が構成されている。形成された集積回路はニ酸化ケイ
素からなる絶縁膜６０Ａにより被覆され、増幅変換基板
４０の集積回路側の表面が平坦化されている。また、こ
の絶縁膜６０Ａに設けられた開口からアルミニウム配線
５８Ａが引き出され、絶縁膜６０Ａの表面に露出されて
いる。The amplification conversion substrate 40 is provided with a trench penetrating the element isolation film 52A and reaching the circuit surface from the back surface of the amplification conversion substrate 40. An insulating film 54A is formed on the inner surface of the trench, and the trench is filled with a conductive material to form a buried interconnect 56A. As a conductive material for forming the embedded wiring 56A,
For example, low-resistance metal such as low-resistance polycrystalline silicon or tungsten doped with impurities is used. An aluminum wiring 58 is provided at the end of the buried wiring 56A on the circuit surface side.
A is directly connected. This makes the amplifier (amplifier)
And an integrated circuit including an analog / digital converter (ADC). The formed integrated circuit is covered with an insulating film 60A made of silicon dioxide, and the surface of the amplification conversion substrate 40 on the integrated circuit side is planarized. The aluminum wiring 58A is drawn out from the opening provided in the insulating film 60A and is exposed on the surface of the insulating film 60A.
【００３０】上記光電変換基板２０の裏面側の表面に、
絶縁層３６の表面から露出した埋め込み配線３４の端部
に接触するようにマイクロバンプ６２を形成する。一
方、増幅変換基板４０の集積回路側の表面にも、絶縁膜
６０Ａの表面に露出したアルミニウム配線５８Ａの端部
に接触するようにマイクロバンプ６４を形成する。マイ
クロバンプは、レジストマスクを用いたリフトオフ等に
より形成することができ、マイクロバンプの材料として
は例えば金とインジウムとの合金またはインジウムを用
いることができる。On the surface on the back side of the photoelectric conversion substrate 20,
The micro bumps 62 are formed so as to be in contact with the ends of the embedded wiring 34 exposed from the surface of the insulating layer 36. On the other hand, the micro-bump 64 is also formed on the surface of the amplification conversion substrate 40 on the integrated circuit side so as to be in contact with the end of the aluminum wiring 58A exposed on the surface of the insulating film 60A. The microbump can be formed by lift-off using a resist mask or the like. As a material of the microbump, for example, an alloy of gold and indium or indium can be used.
【００３１】光電変換基板２０の裏面側の表面に設けら
れたマイクロバンプ６２と、増幅変換基板４０の集積回
路面側の表面に設けられたマイクロバンプ６４とが電気
的に接続されるように、増幅変換基板４０上に光電変換
基板２０を重ね合わせて仮接着する。なお、光電変換基
板２０と増幅変換基板４０との位置合わせは、例えばシ
リコンウエハを透過する赤外線を用いた位置合わせ装置
により行うことができる。The micro-bumps 62 provided on the back surface of the photoelectric conversion substrate 20 and the micro-bumps 64 provided on the integrated circuit surface of the amplification conversion substrate 40 are electrically connected to each other. The photoelectric conversion substrate 20 is overlaid on the amplification conversion substrate 40 and temporarily bonded. The alignment between the photoelectric conversion substrate 20 and the amplification conversion substrate 40 can be performed by, for example, an alignment device using infrared light transmitted through a silicon wafer.
【００３２】仮接着した光電変換基板２０と増幅変換基
板４０とを、液状のエポキシ樹脂を保持した容器と共に
気圧調整が可能なチャンバーに入れてチャンバー内を真
空にし、仮接着した光電変換基板２０と増幅変換基板４
０とを液状のエポキシ樹脂にディップして常圧に戻し基
板間の隙間にエポキシ樹脂６６を注入する。その後基板
を引き上げエポキシ樹脂６６を硬化させて、増幅変換基
板４０と光電変換基板２０との接着が完了する。The temporarily bonded photoelectric conversion substrate 20 and the amplification conversion substrate 40 are put together with a container holding a liquid epoxy resin into a chamber capable of adjusting the pressure, and the chamber is evacuated. Amplification conversion board 4
0 is dipped in a liquid epoxy resin to return to normal pressure, and the epoxy resin 66 is injected into the gap between the substrates. Thereafter, the substrate is pulled up and the epoxy resin 66 is cured, and the adhesion between the amplification conversion substrate 40 and the photoelectric conversion substrate 20 is completed.
【００３３】次に、図４に示すように、増幅変換基板４
０を裏面側から化学的機械研磨により均一な厚さに研磨
して薄膜化する。絶縁層３６Ａを構成するニ酸化ケイ素
はシリコンよりも研磨耐性が大きいため、研磨は絶縁層
３６Ａの手前で止まり、絶縁層３６Ａよりも深い位置ま
で形成されている埋め込み配線５６Ａが絶縁層３６Ａか
ら露出される。Next, as shown in FIG.
0 is polished from the back side to a uniform thickness by chemical mechanical polishing to make a thin film. Since the silicon dioxide constituting the insulating layer 36A has higher polishing resistance than silicon, polishing stops before the insulating layer 36A, and the embedded wiring 56A formed to a position deeper than the insulating layer 36A is exposed from the insulating layer 36A. Is done.
【００３４】次に、図５に示すように、光電変換基板２
０に接着された増幅変換基板４０の裏面に、一時的にデ
ータを記憶するデータ記憶装置（レジスタアレイ）を備
えたデータ記憶基板７０を接着する。ここで用いるデー
タ記憶基板７０は、増幅変換基板４０と同様に、内部に
ニ酸化ケイ素からなる絶縁層３６Ｂが挿入されたシリコ
ン基板３８Ｂ上に、絶縁膜４２Ｂにより絶縁されたゲー
ト４４Ｂ、ソース４６Ｂ、及びドレイン４８Ｂからなる
複数のＭＯＳＦＥＴ５０Ｂ（本実施の形態では２つのＭ
ＯＳＦＥＴを図示する）を形成したものであり、隣接す
るＭＯＳＦＥＴ５０Ｂは、ニ酸化ケイ素からなる素子分
離膜５２Ｂにより分離されている。Next, as shown in FIG.
A data storage substrate 70 provided with a data storage device (register array) for temporarily storing data is bonded to the back surface of the amplification conversion substrate 40 bonded to “0”. The data storage substrate 70 used here, like the amplification conversion substrate 40, has a gate 44B and a source 46B insulated by an insulating film 42B on a silicon substrate 38B in which an insulating layer 36B made of silicon dioxide is inserted. And a plurality of MOSFETs 50B (in this embodiment, two M
An OSFET is shown), and adjacent MOSFETs 50B are separated by an element isolation film 52B made of silicon dioxide.
【００３５】また、データ記憶基板７０には、この素子
分離膜５２Ｂを貫通しデータ記憶基板７０の裏面側表面
から回路面に達するトレンチが設けられている。このト
レンチの内表面に絶縁膜５４Ｂが形成され、トレンチ内
に導電材料が充填されて埋め込み配線５６Ｂが形成され
ている。埋め込み配線５６Ｂを形成する導電材料として
は、例えば不純物をドープした低抵抗多結晶シリコンや
タングステン等の低抵抗の金属が使用される。埋め込み
配線５６Ｂの回路面側の端部にはアルミニウム配線５８
Ｂが直接接続されている。これによりデータ記憶装置を
含む集積回路が構成されている。形成された集積回路
は、ニ酸化ケイ素からなる絶縁膜６０Ｂにより被覆さ
れ、データ記憶基板７０の集積回路側の表面が平坦化さ
れている。この絶縁膜６０Ｂに設けられた開口からアル
ミニウム配線５８Ｂが引き出されて、絶縁膜６０Ｂの表
面に露出されている。The data storage substrate 70 has a trench penetrating the element isolation film 52B and reaching the circuit surface from the back surface of the data storage substrate 70. An insulating film 54B is formed on the inner surface of the trench, and the trench is filled with a conductive material to form a buried interconnect 56B. As the conductive material for forming the buried wiring 56B, for example, a low-resistance metal such as low-resistance polycrystalline silicon or tungsten doped with impurities is used. An aluminum wiring 58 is provided at the end of the buried wiring 56B on the circuit surface side.
B is directly connected. Thus, an integrated circuit including the data storage device is configured. The formed integrated circuit is covered with an insulating film 60B made of silicon dioxide, and the surface of the data storage substrate 70 on the integrated circuit side is planarized. Aluminum wiring 58B is drawn out from the opening provided in insulating film 60B and is exposed on the surface of insulating film 60B.
【００３６】上記増幅変換基板４０の裏面側の表面に、
絶縁層３６Ａの表面から露出した埋め込み配線５６Ａの
端部に接触するようにマイクロバンプ７１を形成する。
一方、データ記憶基板７０の集積回路側の表面にも、絶
縁膜６０Ｂの表面に露出したアルミニウム配線５８Ｂの
端部に接触するようにマイクロバンプ７２を形成する。
そして増幅変換基板４０の裏面側の表面に設けられたマ
イクロバンプ７１と、データ記憶基板７０の集積回路側
の表面に設けられたマイクロバンプ７２とが電気的に接
続されるようにデータ記憶基板７０上に増幅変換基板４
０を重ね合わせて仮接着し、光電変換基板２０及び増幅
変換基板４０を接着する場合と同様にして、増幅変換基
板４０とデータ記憶基板７０とをエポキシ樹脂７４によ
り接着する。On the surface on the back side of the amplification conversion board 40,
The micro-bump 71 is formed so as to contact the end of the embedded wiring 56A exposed from the surface of the insulating layer 36A.
On the other hand, a microbump 72 is also formed on the surface of the data storage substrate 70 on the integrated circuit side so as to contact the end of the aluminum wiring 58B exposed on the surface of the insulating film 60B.
The micro-bump 71 provided on the back surface of the amplification conversion substrate 40 and the micro-bump 72 provided on the integrated circuit side surface of the data storage substrate 70 are electrically connected to each other. Amplification conversion board 4 on top
The amplification conversion substrate 40 and the data storage substrate 70 are bonded with the epoxy resin 74 in the same manner as in the case where the photoelectric conversion substrate 20 and the amplification conversion substrate 40 are bonded together.
【００３７】次に、図６に示すように、データ記憶基板
７０の裏面に、データ処理基板８０、出力回路基板９
０、及び出力端子部１００を順に形成する。上記増幅変
換基板４０やデータ記憶基板７０の形成工程と同様にし
て、増幅変換基板４０に接着されたデータ記憶基板７０
を裏面側から研磨し、データ記憶基板７０の裏面に、デ
ータ処理装置（プロセッサアレイ）を備え埋め込み配線
８２の形成されたデータ処理基板８０を、両基板に設け
られた集積回路が埋め込み配線８２により電気的に接続
されるように接着する。さらに、このデータ処理基板８
０を裏面側から研磨した後に、データ処理基板８０の裏
面に埋め込み配線９２の形成された出力回路基板９０
を、両基板に設けられた集積回路が埋め込み配線９２に
より電気的に接続されるように接着する。そして出力回
路基板９０を裏面側から研磨して、出力回路基板９０裏
面の絶縁膜から埋め込み配線９２の端部を露出させ、露
出した埋め込み配線９２の端部に接触するようにマイク
ロバンプ９３を形成する。Next, as shown in FIG. 6, the data processing board 80 and the output circuit board 9
0 and the output terminal unit 100 are formed in order. Similarly to the process of forming the amplification conversion board 40 and the data storage board 70, the data storage board 70 adhered to the amplification conversion board 40
Is polished from the back side, and the data processing board 80 provided with a data processing device (processor array) and having the embedded wiring 82 formed on the back side of the data storage board 70 is integrated with the integrated circuit provided on both substrates by the embedded wiring 82. Adhere so that they are electrically connected. Further, the data processing board 8
0 is polished from the back side, and then the output circuit board 90 with the embedded wiring 92 formed on the back side of the data processing board 80.
Are bonded so that the integrated circuits provided on both substrates are electrically connected by the embedded wiring 92. Then, the output circuit board 90 is polished from the back surface side to expose the end of the buried wiring 92 from the insulating film on the back surface of the output circuit board 90, and the microbump 93 is formed so as to contact the exposed end of the buried wiring 92. I do.
【００３８】そして最後に出力回路基板９０の裏面に出
力端子部１００を形成する。出力端子部１００はシリコ
ン基板１０２にこのシリコン基板１０２を貫通し基板両
面側に露出した埋め込み配線１０４が形成されたもので
ある。埋め込み配線１０４を形成する導電材料として
は、例えば銅、タングステン、金等の低抵抗の金属が使
用される。この出力端子部１００の入力側の表面に、出
力端子部１００の絶縁層の表面から露出した埋め込み配
線１０４の一方の端部に接触するようにマイクロバンプ
９４を形成する。そして出力回路基板９０の裏面側の表
面に設けられたマイクロバンプ９３と出力端子部１００
の入力側の表面に設けられたマイクロバンプ９４とが接
触し、出力回路基板９０に設けられた集積回路が出力端
子部１００の出力端子に電気的に接続されるように両基
板を接着する。そして上記出力端子部１００の出力側の
表面には、埋め込み配線１０４の他方の端部に接触する
ようにマイクロバンプ１０６を形成する。マイクロバン
プ１０６は、例えば金やインジウムまたはそれらの合金
から形成することができる。また、はんだバンプとして
もよい。Finally, the output terminal section 100 is formed on the back surface of the output circuit board 90. The output terminal portion 100 is formed by forming a buried wiring 104 penetrating the silicon substrate 102 and exposed on both sides of the substrate. As a conductive material for forming the embedded wiring 104, a low-resistance metal such as copper, tungsten, or gold is used, for example. Micro bumps 94 are formed on the input side surface of the output terminal unit 100 so as to contact one end of the embedded wiring 104 exposed from the surface of the insulating layer of the output terminal unit 100. The micro-bumps 93 provided on the back surface of the output circuit board 90 and the output terminals 100
The two substrates are bonded so that the micro-bumps 94 provided on the input side surface of the output circuit board are in contact with each other, and the integrated circuit provided on the output circuit board 90 is electrically connected to the output terminal of the output terminal section 100. On the output-side surface of the output terminal section 100, a micro-bump 106 is formed so as to contact the other end of the embedded wiring 104. The micro bumps 106 can be formed from, for example, gold, indium, or an alloy thereof. Further, it may be a solder bump.
【００３９】以上の工程により、光を集光するレンズを
備えた透明基板１０及び光電変換基板２０からなるイメ
ージセンサ部と、そのイメージセンサ部からの信号を処
理するための処理部（増幅変換基板４０、データ記憶基
板７０、データ処理基板８０及び出力回路基板９０）と
を一体化した図６に示す３次元画像処理装置を得ること
ができる。Through the above steps, an image sensor unit including the transparent substrate 10 having the lens for condensing light and the photoelectric conversion substrate 20 and a processing unit (an amplification conversion substrate) for processing signals from the image sensor unit 6, the data storage board 70, the data processing board 80, and the output circuit board 90) can be obtained.
【００４０】本実施の形態では、多数のマイクロレンズ
が２次元状に形成された石英ガラス製の透明基板に光電
変換基板を直接接着するので、支持基板を別途用意する
必要がなく支持基板の着脱工程が不要となる。これによ
り製造工程を大幅に簡略化することができ、簡素かつ容
易な工程により３次元画像処理装置を製造することがで
きる。また、各集積回路基板の埋め込み配線は貼り合わ
せ前に形成されるので、信頼性の高い絶縁膜で囲まれた
埋め込み配線を形成することができる。In this embodiment, since the photoelectric conversion substrate is directly bonded to a quartz glass transparent substrate in which a large number of microlenses are formed two-dimensionally, there is no need to separately prepare a support substrate, and the support substrate can be attached and detached. No process is required. Thus, the manufacturing process can be greatly simplified, and the three-dimensional image processing apparatus can be manufactured by simple and easy processes. In addition, since the embedded wiring of each integrated circuit substrate is formed before bonding, the embedded wiring surrounded by a highly reliable insulating film can be formed.
【００４１】上記実施の形態では、集積回路を形成する
ための各半導体基板にニ酸化ケイ素からなる絶縁層が内
部に形成されたシリコン基板を使用したが、ニ酸化ケイ
素からなる絶縁層を含まないシリコン基板を使用しても
よい。In the above embodiment, the silicon substrate in which the insulating layer made of silicon dioxide is formed for each semiconductor substrate for forming the integrated circuit is used, but the insulating layer made of silicon dioxide is not included. A silicon substrate may be used.
【００４２】上記実施の形態では、埋め込み配線の両端
部にマイクロバンプを形成し、マイクロバンプ同士を接
触させて隣接する基板を電気的に接続する例について説
明したが、埋め込み配線の一方の端部にのみマイクロバ
ンプを形成して隣接する基板を電気的に接続するように
しても良い。In the above embodiment, an example has been described in which micro-bumps are formed at both ends of an embedded wiring, and the micro-bumps are brought into contact with each other to electrically connect adjacent substrates. Alternatively, a microbump may be formed only on the substrate to electrically connect the adjacent substrates.
【００４３】上記実施の形態では、集光レンズを備えた
透明基板及び光電変換基板からなるイメージセンサ部
に、そのイメージセンサ部からの信号を処理するための
増幅変換基板、データ記憶基板、データ処理基板、及び
出力回路基板の各処理部を研磨及び貼合せを繰り返すこ
とにより形成する例について説明したが、イメージセン
サ部を構成する光電変換基板を裏面側から研磨して埋め
込み配線を露出させた後、配線により光電変換基板を増
幅変換基板と電気的に接続することもできる。In the above-described embodiment, an amplification conversion board for processing a signal from the image sensor section, a data storage board, and a data processing section are provided on an image sensor section including a transparent substrate having a condenser lens and a photoelectric conversion board. Although the example in which the substrate and each processing section of the output circuit board are formed by repeating polishing and lamination has been described, after exposing the embedded wiring by polishing the photoelectric conversion substrate constituting the image sensor section from the back side, Alternatively, the photoelectric conversion substrate can be electrically connected to the amplification conversion substrate by wiring.
【００４４】また、上記実施の形態と同様にしてイメー
ジセンサ部に研磨及び貼合せにより増幅変換基板を形成
し、増幅変換基板を裏面側から研磨して埋め込み配線を
露出させた後、配線により増幅変換基板をデータ記憶基
板と電気的に接続することもできる。また、上記実施の
形態と同様にしてイメージセンサ部に研磨及び貼合せに
より増幅変換基板及びデータ記憶基板を形成し、データ
記憶基板を裏面側から研磨して埋め込み配線を露出させ
た後、配線によりデータ記憶基板をデータ処理基板と電
気的に接続することもできる。また、上記実施の形態と
同様にしてイメージセンサ部に研磨及び貼合せにより増
幅変換基板、データ記憶基板、及びデータ処理基板を形
成し、データ処理基板を裏面側から研磨して埋め込み配
線を露出させた後、配線によりデータ処理基板を出力回
路基板と電気的に接続することもできる。In the same manner as in the above embodiment, an amplification conversion substrate is formed on the image sensor portion by polishing and bonding, and the amplification conversion substrate is polished from the back side to expose the embedded wiring, and then amplified by the wiring. The conversion board can also be electrically connected to the data storage board. Further, an amplification conversion substrate and a data storage substrate are formed on the image sensor unit by polishing and bonding in the same manner as in the above-described embodiment, and the data storage substrate is polished from the back side to expose the embedded wiring. The data storage board can also be electrically connected to the data processing board. Further, an amplification conversion substrate, a data storage substrate, and a data processing substrate are formed by polishing and bonding the image sensor unit in the same manner as in the above-described embodiment, and the data processing substrate is polished from the back side to expose the embedded wiring. After that, the data processing board can be electrically connected to the output circuit board by wiring.
【００４５】なお、上記実施の形態において使用するシ
リコン基板は、ウエハスケールでもチップスケールでも
よい。The silicon substrate used in the above embodiment may be a wafer scale or a chip scale.
【００４６】[0046]
【発明の効果】本発明の３次元画像処理装置の製造方法
は、支持基板の着脱工程が不要で、製造工程を大幅に簡
略化することができ、簡素かつ容易な工程により３次元
画像処理装置を製造することができる、という効果を奏
する。また、本発明の３次元画像処理装置の製造方法
は、信頼性の高い絶縁膜で囲まれた埋め込み配線を形成
することができる、という効果を奏する。According to the method of manufacturing a three-dimensional image processing apparatus of the present invention, the step of attaching and detaching the support substrate is not required, and the manufacturing process can be greatly simplified. Can be produced. Further, the method for manufacturing a three-dimensional image processing apparatus according to the present invention has an effect that a buried wiring surrounded by a highly reliable insulating film can be formed.
【図１】本実施の形態の３次元画像形成装置の製造工程
を示す概略断面図である。FIG. 1 is a schematic cross-sectional view illustrating a manufacturing process of a three-dimensional image forming apparatus according to an embodiment.
【図２】本実施の形態の３次元画像形成装置の製造工程
を示す概略断面図である。FIG. 2 is a schematic cross-sectional view illustrating a manufacturing process of the three-dimensional image forming apparatus of the present embodiment.
【図３】本実施の形態の３次元画像形成装置の製造工程
を示す概略断面図である。FIG. 3 is a schematic cross-sectional view illustrating a manufacturing process of the three-dimensional image forming apparatus of the present embodiment.
【図４】本実施の形態の３次元画像形成装置の製造工程
を示す概略断面図である。FIG. 4 is a schematic cross-sectional view illustrating a manufacturing process of the three-dimensional image forming apparatus of the present embodiment.
【図５】本実施の形態の３次元画像形成装置の製造工程
を示す概略断面図である。FIG. 5 is a schematic cross-sectional view showing a manufacturing process of the three-dimensional image forming apparatus of the present embodiment.
【図６】本実施の形態の３次元画像形成装置の構造を示
す概略断面図である。FIG. 6 is a schematic sectional view showing the structure of the three-dimensional image forming apparatus of the present embodiment.
１０ 透明基板 １２ マイクロレンズ １６ ｎ型シリコン結晶基板 １８ ｐ型不純物層 ２０ 光電変換基板 ２２ ｎ型不純物層 ２６ ゲート電極 ２８ 電極 ３４ 埋め込み配線 ４０ 増幅変換基板 ７０ データ記憶基板 ８０ データ処理基板 ９０ 出力回路基板 １００ 出力端子部 Reference Signs List 10 transparent substrate 12 microlens 16 n-type silicon crystal substrate 18 p-type impurity layer 20 photoelectric conversion substrate 22 n-type impurity layer 26 gate electrode 28 electrode 34 embedded wiring 40 amplification conversion substrate 70 data storage substrate 80 data processing substrate 90 output circuit substrate 100 output terminal
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 ＦＩ テーマコート゛(参考） Ｈ０１Ｌ 21/8238 Ｈ０１Ｌ 21/90 Ａ ５Ｆ１１０ 27/092 27/08 ３２１Ｇ 27/14 27/14 Ｄ 29/786 29/78 ６１３Ｚ Ｈ０４Ｎ 5/335 (72)発明者 宮川 宣明 神奈川県海老名市本郷2274番地 富士ゼロ ックス株式会社海老名事業所内 Ｆターム(参考） 4M118 AA10 AB01 BA04 BA14 CA03 EA04 EA20 FA33 GD01 GD04 GD07 HA21 HA33 5B047 BB04 BC01 BC05 DB01 5C024 CY47 EX43 GX03 GY31 HX01 HX17 HX40 HX41 5F033 HH04 HH08 HH11 HH13 HH19 JJ01 JJ08 KK01 MM30 QQ08 QQ09 QQ12 QQ37 QQ49 RR04 SS25 UU05 VV00 VV07 XX10 5F048 AA09 AB03 AB10 AC03 AC10 BA09 BB05 BC12 BF01 BF02 BF03 BF07 BF15 BG12 BG14 CB02 CB03 CB04 5F110 AA16 BB10 BB11 CC02 DD03 DD05 DD21 DD30 EE09 HL03 NN62 NN71 QQ16 QQ30 ──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. 7 Identification code FI Theme coat ゛ (Reference) H01L 21/8238 H01L 21/90 A 5F110 27/092 27/08 321G 27/14 27/14 D 29/786 29/78 613Z H04N 5/335 (72) Inventor Nobuaki Miyagawa 2274 Hongo, Ebina-shi, Kanagawa Prefecture Fuji Xerox Co., Ltd. Ebina Works F-term (reference) 4M118 AA10 AB01 BA04 BA14 CA03 EA04 EA20 FA33 GD01 GD04 GD07 HA21 HA33 5B047 BB04 BC01 BC05 DB01 5C024 CY47 EX43 GX03 GY31 HX01 HX17 HX40 HX41 5F033 HH04 HH08 HH11 HH13 HH19 JJ01 JJ08 KK01 MM30 QQ08 QQ09 QQ12 QQ37 QQ49 RR04 SS25 UU05 VV03 A13 CB04 CB04 CB02 CB03 CB04 5F110 AA16 BB10 BB11 CC02 DD03 DD05 DD21 DD30 EE09 HL03 NN62 NN71 QQ16 QQ30
Claims (5)
主面に光電変換素子が形成されると共に該光電変換素子
に電気的に接続された埋め込み配線が形成された光電変
換基板とを、透明基板の裏面と光電変換基板の主面とが
対向するように接着して、３次元画像処理装置を製造す
る３次元画像処理装置の製造方法。1. A transparent substrate having a lens for condensing light,
The photoelectric conversion element is formed on the main surface and the photoelectric conversion substrate on which the embedded wiring electrically connected to the photoelectric conversion element is formed. The back surface of the transparent substrate and the main surface of the photoelectric conversion substrate face each other. A method of manufacturing a three-dimensional image processing apparatus for manufacturing a three-dimensional image processing apparatus by adhering to a substrate.
埋め込み配線を露出させ、 該光電変換基板の裏面に、主面に増幅器及びアナログ／
デジタル変換器が形成されると共に該増幅器及びアナロ
グ／デジタル変換器に電気的に接続された埋め込み配線
が形成された増幅変換基板を、該増幅器及びアナログ／
デジタル変換器が前記埋め込み配線の露出部に電気的に
接続されるように接着して、３次元画像処理装置を製造
する請求項１に記載の３次元画像処理装置の製造方法。2. A back surface side of the photoelectric conversion substrate is polished to expose the embedded wiring, and an amplifier and an analog / digital converter are provided on a main surface of the back surface of the photoelectric conversion substrate.
An amplification conversion board, on which a digital converter is formed and on which an embedded wiring electrically connected to the amplifier and the analog / digital converter is formed, is connected to the amplifier and the analog / digital converter.
The method for manufacturing a three-dimensional image processing apparatus according to claim 1, wherein the three-dimensional image processing apparatus is manufactured by bonding a digital converter so as to be electrically connected to an exposed portion of the embedded wiring.
埋め込み配線を露出させ、 該増幅変換基板の裏面に、主面にデータ記憶装置が形成
されると共に該データ記憶装置に電気的に接続された埋
め込み配線が形成されたデータ記憶基板を、該データ記
憶装置が前記埋め込み配線の露出部に電気的に接続され
るように接着して、３次元画像処理装置を製造する請求
項２に記載の３次元画像処理装置の製造方法。3. A data storage device is formed on a main surface of the amplification conversion substrate by polishing the back surface of the amplification conversion substrate to expose the buried wiring, and the data storage device is electrically connected to the back surface of the amplification conversion substrate. 3. The three-dimensional image processing device according to claim 2, wherein the data storage substrate having the connected embedded wiring formed thereon is bonded so that the data storage device is electrically connected to the exposed portion of the embedded wiring. A manufacturing method of the three-dimensional image processing device according to the above.
記埋め込み配線を露出させ、 該データ記憶基板の裏面に、主面にデータ処理装置が形
成されると共に該データ処理装置に電気的に接続された
埋め込み配線が形成されたデータ処理基板を、該データ
処理装置が前記埋め込み配線の露出部に電気的に接続さ
れるように接着して、３次元画像処理装置を製造する請
求項３に記載の３次元画像処理装置の製造方法。4. A data processing device is formed on a main surface of the back surface of the data storage substrate by polishing the back surface of the data storage substrate to expose the buried wiring, and electrically connected to the data processing device. 4. The three-dimensional image processing apparatus according to claim 3, wherein the data processing substrate having the connected embedded wiring formed thereon is bonded so that the data processing device is electrically connected to the exposed portion of the embedded wiring. A manufacturing method of the three-dimensional image processing device according to the above.
記埋め込み配線を露出させ、 該データ処理基板の裏面に、主面に出力回路が形成され
ると共に該出力回路に電気的に接続された埋め込み配線
が形成された出力回路基板を、該出力回路が前記埋め込
み配線の露出部に電気的に接続されるように接着して、
３次元画像処理装置を製造する請求項４に記載の３次元
画像処理装置の製造方法。5. The data processing board is polished on the back side to expose the embedded wiring, and on the back side of the data processing board, an output circuit is formed on a main surface and is electrically connected to the output circuit. Bonding the output circuit board on which the embedded wiring is formed so that the output circuit is electrically connected to the exposed portion of the embedded wiring,
The method for manufacturing a three-dimensional image processing apparatus according to claim 4, wherein the three-dimensional image processing apparatus is manufactured.
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| JP2000160330A JP3713418B2 (en) | 2000-05-30 | 2000-05-30 | Manufacturing method of three-dimensional image processing apparatus |
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| JP3713418B2 JP3713418B2 (en) | 2005-11-09 |
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