WO2016035184A1 - Solid-state image pickup device - Google Patents

Solid-state image pickup device Download PDF

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Publication number
WO2016035184A1
WO2016035184A1 PCT/JP2014/073333 JP2014073333W WO2016035184A1 WO 2016035184 A1 WO2016035184 A1 WO 2016035184A1 JP 2014073333 W JP2014073333 W JP 2014073333W WO 2016035184 A1 WO2016035184 A1 WO 2016035184A1
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WO
WIPO (PCT)
Prior art keywords
semiconductor substrate
solid
imaging device
state imaging
semiconductor
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PCT/JP2014/073333
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French (fr)
Japanese (ja)
Inventor
良章 竹本
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オリンパス株式会社
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Priority to PCT/JP2014/073333 priority Critical patent/WO2016035184A1/en
Publication of WO2016035184A1 publication Critical patent/WO2016035184A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures

Definitions

  • the present invention relates to a solid-state imaging device.
  • imaging devices such as video cameras and electronic still cameras have been widely used.
  • CCD Charge Coupled Device
  • amplification type solid-state imaging devices introduces an electric signal generated and accumulated by a photoelectric conversion unit such as a photodiode provided in a pixel to which light enters to the amplification unit provided in the pixel, and the amplification unit amplifies the signal.
  • a signal is output from the pixel.
  • the amplification type solid-state imaging device a plurality of such pixels are arranged in a two-dimensional matrix to form a pixel array unit.
  • Examples of the amplification type solid-state imaging device include a CMOS type solid-state imaging device using a CMOS (Complementary Metal Oxide Semiconductor: complementary metal oxide semiconductor) transistor.
  • CMOS type solid-state imaging device having a general monolithic structure (a structure manufactured from a single semiconductor substrate), when viewed from the light incident surface, a plurality of pixels that convert incident light into electrical signals are provided.
  • a peripheral circuit is disposed around the formed pixel array portion. This peripheral circuit is a logic circuit such as a vertical scanning circuit, a horizontal scanning circuit, a column processing circuit, and an output circuit. A wiring for transmitting an electrical signal is provided for each column or row between the pixel array portion and these peripheral circuits.
  • CMOS type solid-state imaging devices are required to improve the data rate, improve the in-plane imaging performance, and increase the functionality.
  • recent CMOS type solid-state imaging devices are required to be reduced in size, but it is difficult to reduce the area of the substrate plane because peripheral circuits are arranged around the pixel array portion.
  • CMOS type solid-state imaging device configured as one semiconductor device has been proposed.
  • the performance and function of the CMOS solid-state imaging device are improved and the size is reduced.
  • Patent Document 1 discloses a stacked CMOS solid-state imaging device having a configuration in which a first semiconductor chip in which a pixel array portion is formed and a second semiconductor chip in which a logic circuit is formed are bonded together.
  • the CMOS type solid-state imaging device disclosed in Patent Document 1 is a backside illumination (BSI) type solid-state imaging device that receives light incident from the back side of a first semiconductor chip.
  • BSI backside illumination
  • a semiconductor removal region in which a part of the semiconductor portion of the first semiconductor chip is removed is provided in the semiconductor removal region. In the semiconductor removal region, a plurality of connection wirings for connecting the first semiconductor chip and the second semiconductor chip are formed so as to penetrate the first semiconductor chip.
  • a plurality of pixels including a photoelectric conversion unit are arranged in a two-dimensional matrix to form a pixel array unit.
  • a semiconductor removal region in a region other than the region where the pixel array portion is formed in the first semiconductor chip.
  • the first semiconductor chip and the second semiconductor chip are connected by the connection wiring formed in the semiconductor removal region provided in the peripheral portion of the pixel array portion. Signal lines that are exchanged between the two are connected.
  • the first semiconductor chip and the second semiconductor chip are connected by connection wiring formed in a semiconductor removal region provided in the peripheral portion of the pixel array portion. Are electrically connected. For this reason, the arrangement of the respective signal lines exchanged between the first semiconductor chip and the second semiconductor chip is limited. That is, in the technique disclosed in Patent Document 1, the degree of freedom is small in the arrangement of the connection wiring that connects the first semiconductor chip and the second semiconductor chip.
  • the present invention has been made based on the above problems, and in a solid-state imaging device having a configuration in which a plurality of semiconductor substrates are stacked, the performance and functions are improved, and the degree of freedom of wiring for connecting each semiconductor substrate is improved.
  • An object of the present invention is to provide a solid-state imaging device that can be reduced in size.
  • the solid-state imaging device includes a circuit element of a pixel unit in which a plurality of pixels each having a photoelectric conversion unit that converts incident light into an electrical signal and outputs the electrical signal is arranged in a two-dimensional matrix.
  • a first semiconductor substrate having a formed first semiconductor layer, and a second semiconductor layer having a second semiconductor layer on which circuit elements of a processing unit for processing the electrical signal output from the photoelectric conversion unit are formed.
  • connection electrode overlaps a region of the pixel unit on a side opposite to a side on which the light ray enters the pixel unit. It may be arranged as follows.
  • the solid-state imaging device further includes a support substrate that supports a state in which the first semiconductor substrate and the second semiconductor substrate are stacked.
  • the support substrate may be made of the same material as the first semiconductor substrate and the second semiconductor substrate.
  • the solid-state imaging device further includes a support substrate that supports a state in which the first semiconductor substrate and the second semiconductor substrate are stacked.
  • the support substrate may be made of a material different from that of the first semiconductor substrate and the second semiconductor substrate.
  • connection electrode is a signal line between circuit elements formed in the first semiconductor substrate, or the second You may form with the material different from the metal wiring formed in order to connect the signal wire
  • connection electrode is a signal line between circuit elements formed in the first semiconductor substrate, or the second You may form with the same material as the metal wiring formed in order to connect the signal wire
  • connection electrode is a signal line between circuit elements formed in the first semiconductor substrate, or the second You may form with the same material as the metal wiring formed in order to connect the signal wire
  • a solid-state imaging device having a configuration in which a plurality of semiconductor substrates are stacked, performance and functions can be improved, and the degree of freedom of wiring for connecting each semiconductor substrate can be improved to achieve miniaturization. it can.
  • FIG. 1 is an overview diagram illustrating a schematic configuration of a solid-state imaging device according to a first embodiment of the present invention. It is the top view which showed schematic structure when the solid-state imaging device of the 1st Embodiment of this invention is seen from the light incident side. It is the figure which showed the structure of the 1st semiconductor substrate and 2nd semiconductor substrate in the solid-state imaging device of the 1st Embodiment of this invention. It is sectional drawing which showed the structure of the solid-state imaging device of the 1st Embodiment of this invention. It is sectional drawing which showed the structure of the solid-state imaging device of the 2nd Embodiment of this invention.
  • FIG. 1 is an overview showing a schematic configuration of a solid-state imaging device according to the first embodiment of the present invention.
  • the solid-state imaging device 10 according to the first embodiment is configured by stacking a plurality of substrates.
  • a first semiconductor substrate 11 and a second semiconductor substrate 12 are bonded.
  • a support substrate 13 is bonded to the second semiconductor substrate 12.
  • a circuit for realizing the function of the solid-state imaging device 10 is formed on one of the first semiconductor substrate 11 and the second semiconductor substrate 12.
  • a circuit for realizing the function of the solid-state imaging device 10 is a pixel array in which a plurality of pixels including photoelectric conversion units such as photodiodes that convert incident light (light rays) into electric signals are arranged in a two-dimensional matrix. Unit, a column processing circuit that processes the electrical signal photoelectrically converted by the photoelectric conversion unit, a drive circuit for driving the pixels in the pixel array unit, and a signal processing circuit that processes the electrical signal processed by the column processing circuit, etc. It is.
  • the pixel array unit is formed on the first semiconductor substrate 11.
  • the solid-state imaging device 10 has a so-called backside illumination in which the first semiconductor substrate 11 is bonded to the second semiconductor substrate 12 so that the surface on which light is incident is a silicon layer. : BSI) type solid-state imaging device.
  • an adhesive layer may be provided, or the first semiconductor substrate 11 and the second semiconductor substrate 12 are directly bonded. May be.
  • the adhesive layer may include a connection electrode portion for electrically connecting signals between the first semiconductor substrate 11 and the second semiconductor substrate 12.
  • a method of directly bonding the first semiconductor substrate 11 and the second semiconductor substrate 12 for example, pretreatment is performed on oxide films or metal portions of the respective semiconductor substrates, and plasma bonding by surface activation is performed.
  • a method of directly bonding (stacking) semiconductor substrates to each other can be considered.
  • a connection film such as a silicon oxide film or a silicon nitride film may be provided and used as an adhesive layer.
  • a method of directly bonding the first semiconductor substrate 11 and the second semiconductor substrate 12 is desirable.
  • the method of bonding the second semiconductor substrate 12 and the support substrate 13 can be considered in the same manner as the method of bonding the first semiconductor substrate 11 and the second semiconductor substrate 12. However, since the second semiconductor substrate 12 and the support substrate 13 are not electrically connected, they may be joined by an insulating member such as a resin adhesive.
  • the function of the solid-state imaging device 10 is realized by a configuration in which two semiconductor substrates of the first semiconductor substrate 11 and the second semiconductor substrate 12 are stacked is shown.
  • the number of semiconductor substrates to be stacked in order to realize the function of the solid-state imaging device is not limited to two, and a configuration in which a larger number of semiconductor substrates are stacked may be employed.
  • the third substrate is provided on the surface of the second semiconductor substrate 12 shown in FIG. The semiconductor substrate is bonded, and the support substrate 13 is further bonded. That is, the third and subsequent semiconductor substrates are sandwiched between the second semiconductor substrate 12 and the support substrate 13.
  • FIG. 2 is a plan view showing a schematic configuration when the solid-state imaging device 10 according to the first embodiment of the present invention is viewed from the light incident side.
  • a pixel array unit 111 in which a plurality of pixels including a photoelectric conversion unit are arranged in a two-dimensional matrix, and an electric signal photoelectrically converted by each pixel in the pixel array unit 111 are read out.
  • a horizontal drive circuit 112 for the above and a bonding pad 113 for connecting wiring for the solid-state imaging device 10 to input and output signals to and from the outside are arranged.
  • the bonding pad 113 is used to input and output electrical signals between a circuit outside the package and the solid-state imaging device 10.
  • the bonding pad 113 and the package are electrically connected by a wiring part formed by using a wire bonding method or the like.
  • the electrical signal output from the solid-state imaging device 10 is output to an external circuit via the corresponding bonding pad 113 and wiring portion.
  • an electrical signal input from an external circuit is input to each component in the solid-state imaging device 10 via the corresponding wiring portion and the bonding pad 113.
  • the bonding pad 113 is electrically connected to each component in the first semiconductor substrate 11, but connected to each component in the second semiconductor substrate 12. It may be configured. Further, the bonding pad 113 may be disposed not only on the first semiconductor substrate 11 but also on the second semiconductor substrate 12.
  • the horizontal drive circuit 112 is arranged on the first semiconductor substrate 11. However, the horizontal drive circuit 112 is arranged on the second semiconductor substrate 12. Also good. Further, the horizontal drive circuit 112 may be arranged separately on both the first semiconductor substrate 11 and the second semiconductor substrate 12.
  • the first semiconductor substrate 11 is a semiconductor substrate that converts incident light into an electrical signal and outputs it to the second semiconductor substrate 12.
  • a pixel array unit 111 and a horizontal drive circuit 112 are arranged.
  • the second semiconductor substrate 12 is a semiconductor substrate that processes the electrical signal output from the first semiconductor substrate 11 and outputs the processed electrical signal to the first semiconductor substrate 11.
  • a vertical drive circuit 121, a column processing circuit 122, a signal processing circuit 123, a first connection electrode array 124, and a second connection electrode array 125 are arranged.
  • the pixel array unit 111 is a pixel unit in which a plurality of pixels each including a photoelectric conversion unit that converts incident light into an electrical signal and a plurality of transistors are arranged in a two-dimensional matrix.
  • the pixel array unit 111 outputs an electric signal obtained by converting incident light to the column processing circuit 122 in accordance with the drive signal input from the vertical drive circuit 121 via the first connection electrode array 124.
  • the vertical drive circuit 121 drives each pixel in the pixel array unit 111 and causes the horizontal drive circuit 112 to output an electric signal (hereinafter referred to as “pixel signal”) obtained by photoelectrically converting light incident on each pixel.
  • the vertical drive circuit 121 generates a drive signal for driving each pixel in the pixel array unit 111. Then, the vertical drive circuit 121 sequentially outputs the generated drive signal for each row of pixels arranged in the pixel array unit 111 via the first connection electrode array 124, so that each pixel in the pixel array unit 111 is output. Is driven row by row.
  • the horizontal drive circuit 112 reads out pixel signals output from the pixels driven by the vertical drive circuit 121 for each row, and outputs electrical signals corresponding to the read pixel signals from the respective pixels output by the solid-state imaging device 10.
  • a signal is sequentially output for each column of pixels arranged in the pixel array unit 111.
  • the horizontal drive circuit 112 outputs the electrical signal after the predetermined processing is performed by the column processing circuit 122 and the signal processing circuit 123 as the electrical signal of each pixel output from the solid-state imaging device 10. More specifically, the horizontal driving circuit 112 outputs the read pixel signal to the column processing circuit 122 via the second connection electrode array 125, and from the signal processing circuit 123 via the second connection electrode array 125.
  • the input electric signal is output as an electric signal of each pixel output from the solid-state imaging device 10.
  • the column processing circuit 122 is arranged in the pixel array unit 111 with respect to the pixel signal read out for each row by the vertical driving circuit 121 and input from the horizontal driving circuit 112 via the second connection electrode array 125.
  • a predetermined process (hereinafter referred to as “column processing”) is performed for each column of pixels. Then, the column processing circuit 122 outputs the pixel signal after the column processing to the signal processing circuit 123. Examples of the column processing performed by the column processing circuit 122 on the pixel signal include, for example, CDS (Correlated Double Sampling) processing that performs amplification processing for amplifying the pixel signal and processing for removing noise from the pixel signal.
  • CDS Correlated Double Sampling
  • There is a process for an analog signal such as an analog-to-digital conversion process for converting a pixel signal (analog signal) from analog to digital.
  • the signal processing circuit 123 performs predetermined signal processing on the pixel signal after column processing input from the column processing circuit 122. Then, the signal processing circuit 123 outputs the electric signal after the signal processing to the horizontal drive circuit 112 via the second connection electrode array 125. As a result, the horizontal drive circuit 112 sequentially outputs, for each column, the electrical signal that has been subjected to predetermined processing by the column processing circuit 122 and the signal processing circuit 123 as the electrical signal of each pixel output from the solid-state imaging device 10. can do.
  • the signal processing performed by the signal processing circuit 123 on the pixel signal after column processing is, for example, noise removal processing or distortion correction processing for outputting the pixel signal after column processing to a circuit outside the solid-state imaging device 10. , YC (luminance color) conversion processing, resizing processing, and the like.
  • the first connection electrode array 124 and the second connection electrode array 125 have connection electrodes for electrically connecting the components in the first semiconductor substrate 11 and the components in the second semiconductor substrate 12. A plurality of arrays are arranged. More specifically, in the solid-state imaging device 10, the first connection electrode array 124 electrically connects the components in the vertical drive circuit 121 and the components in the pixel array unit 111. The second connection electrode array 125 electrically connects the components in the horizontal drive circuit 112 and the components in the column processing circuit 122 or the signal processing circuit 123, respectively.
  • connection electrode part for example, a structure of a micro bump manufactured by a vapor deposition method or a plating method or a structure connected by a metal wiring layer is used.
  • structure of the connection electrode portion for example, a structure of a through silicon via (TSV: Through-Silicon-Via) may be used.
  • the first connection electrode array 124 is arranged in parallel with the vertical drive circuit 121, and the second connection electrode array 125 is in parallel with the column processing circuit 122.
  • a configuration arranged side by side is shown.
  • the positions at which the first connection electrode array 124 and the second connection electrode array 125 are arranged are not limited to the positions shown in FIG.
  • the first connection electrode array 124 may be arranged at a position opposite to the signal processing circuit 123 parallel to the vertical drive circuit 121, and the second connection electrode array 125 is parallel to the column processing circuit 122. You may arrange
  • each of the first connection electrode array 124 and the second connection electrode array 125 may be distributed in a plurality of positions, or may be disposed in at least a part of the positions described above.
  • the horizontal drive circuit 112 is arranged on the first semiconductor substrate 11 and the vertical drive circuit 121 is arranged on the second semiconductor substrate 12 is shown.
  • the vertical drive circuit 121 may be arranged on the first semiconductor substrate 11 and the horizontal drive circuit 112 may be arranged on the second semiconductor substrate 12.
  • the horizontal drive circuit 112 and the vertical drive circuit 121 may be arranged separately on both the first semiconductor substrate 11 and the second semiconductor substrate 12.
  • FIG. 4 is a cross-sectional view showing the structure of the solid-state imaging device 10 according to the first embodiment of the present invention.
  • FIG. 4 shows a part of the structure of the region where the pixels in the pixel array unit 111 are formed in the configuration of the solid-state imaging device 10 shown in FIG.
  • the first semiconductor substrate 11 and the second semiconductor substrate 12 are bonded, and the support substrate 13 is bonded to the second semiconductor substrate 12.
  • FIG. 4 an example in which each substrate is bonded by an adhesive layer is illustrated.
  • the second semiconductor substrate 12 bonded to the first semiconductor substrate 11 by the adhesive layer 1130 is constituted by the second wiring layer 1201 and the second semiconductor layer 1203.
  • the second semiconductor substrate 12 is formed with circuit elements that are components (circuits) that mainly process digital signals.
  • the support substrate 13 is a thinned semiconductor in the manufacturing process of the solid-state imaging device 10 in which the first semiconductor substrate 11 and the second semiconductor substrate 12 are stacked and then the respective semiconductor substrates stacked by etching or the like are thinned. It is a board
  • the micro lens 1111 condenses light (light rays) incident on the solid-state imaging device 10.
  • the micro lens 1111 is formed at a position corresponding to each pixel disposed in the solid-state imaging device 10. Then, the micro lens 1111 condenses the incident light beam on the first semiconductor layer 1116, for example.
  • the color filter 1112 changes the spectral transmission characteristics of light (light rays) incident on the solid-state imaging device 10 so that light beams of different colors are incident on each pixel formed immediately below.
  • the color filter 1112 is formed at a position corresponding to each of the microlens 1111 and the pixel. Note that the color filter 1112 is provided as necessary. For example, when the solid-state imaging device 10 is a solid-state imaging device that forms a monochrome image, the color filter 1112 need not be provided.
  • the transparent resin layer 1113 is a layer that flattens the surface on which light (light rays) is incident on the first semiconductor substrate 11.
  • the light shielding film 1114 shields light between adjacent pixels.
  • the light shielding film 1114 is made of a metal material, and is formed of a plurality of layers using, for example, tungsten or aluminum as a main material and titanium or a nitride thereof as an adhesion layer.
  • the antireflection film 1115 is a film that reduces reflection of light (light rays) incident on the solid-state imaging device 10.
  • the antireflection film 1115 is formed of a high dielectric material, for example, a single layer or a plurality of layers using tantalum oxide, hafnium oxide, or silicon nitride, and is formed on a surface in contact with the first semiconductor layer 1116. . At this time, the antireflection film 1115 is formed so that incident light rays are incident on the first semiconductor layer 1116 with a predetermined spectral transmission characteristic.
  • the first semiconductor layer 1116 is a semiconductor layer that forms a circuit element of a pixel.
  • photoelectric conversion is performed in which a pixel is formed in the first semiconductor layer 1116 and light (light rays) incident from a surface in contact with the antireflection film 1115 is converted into an electrical signal.
  • the case where the part 1117 is formed is shown.
  • the incident light beam is converted into an electric signal (pixel signal) by the photoelectric conversion unit 1117 formed in the first semiconductor layer 1116.
  • the first wiring layer 1118 is a layer in which metal wiring for connecting pixel circuit elements or respective components arranged in the first semiconductor substrate 11 is formed.
  • the metal wiring 1119 is formed in the first wiring layer 1118.
  • the respective circuit elements constituting the respective constituent elements arranged on the first semiconductor substrate 11 are connected by the respective metal wirings 1119 formed in the first wiring layer 1118.
  • the adhesive layer 1130 is a layer for bonding the first semiconductor substrate 11 and the second semiconductor substrate 12.
  • the adhesive layer 1130 is made of, for example, a silicon oxide film or a silicon nitride film.
  • the second wiring layer 1201 is a layer in which metal wiring for connecting the respective constituent elements arranged in the second semiconductor substrate 12 is formed.
  • the metal wiring 1202 is formed in the second wiring layer 1201 in the configuration of the solid-state imaging device 10 illustrated in FIG. 4, a case where the metal wiring 1202 is formed in the second wiring layer 1201 is illustrated.
  • the respective circuit elements constituting the respective constituent elements arranged on the second semiconductor substrate 12 are connected by the respective metal wirings 1202 formed in the second wiring layer 1201.
  • the signal line of the circuit element formed on the first semiconductor substrate 11 and the signal line of the circuit element formed on the second semiconductor substrate 12 are the silicon through electrode 1204 and the back electrode 1205.
  • the connection electrode includes a silicon through electrode 1204 that passes through the second semiconductor layer 1203 and is connected to the metal wiring in the second wiring layer 1201, the second semiconductor layer 1203, the second wiring layer 1201, and an adhesive.
  • the silicon through electrode 1204 penetrating the layer 1130 and connected to the metal wiring in the first wiring layer 1118 forms a set, and the set of the silicon through electrode 1204 is connected by the back electrode 1205. .
  • the material of the through silicon via 1204 and the back electrode 1205 is the circuit elements formed in the first semiconductor substrate 11 in the first wiring layer 1118 or the second wiring layer 1201, or the second semiconductor substrate.
  • the same material as the metal wiring formed for connecting the circuit elements formed in 12 may be used, or a different material may be used.
  • the material of the silicon through electrode 1204 and the back electrode 1205 may be aluminum or copper generally used as metal wiring, or metal wiring (aluminum) such as polysilicon used as a gate terminal of a transistor. Different materials may be used.
  • silicon can be used in the semiconductor manufacturing process. A process of forming the through electrode 1204 and the back electrode 1205 can be easily incorporated.
  • the adhesive layer 1230 is a layer for joining the second semiconductor substrate 12 and the support substrate 13 together.
  • the adhesive layer 1230 joins the second semiconductor substrate 12 and the support substrate 13 directly or by resin.
  • the adhesive layer 1230 is made of, for example, a protective film such as a silicon oxide film or a silicon nitride film, or a resin film such as polyimide resin.
  • the support substrate 13 supports the first semiconductor substrate 11 and the second semiconductor substrate 12 that are bonded together, so that the first semiconductor substrate 11 and the second semiconductor substrate 12 that are stacked and thinned are supported.
  • This is a substrate for maintaining physical strength (mechanical strength).
  • the solid-state imaging device 10 has a final structure by proceeding with the respective steps in the following order.
  • Process 1 Each of the first semiconductor layer 1116 and the first wiring layer 1118 is formed on the first semiconductor substrate 11.
  • the second semiconductor layer 1203 and the second wiring layer 1201 are formed on the second semiconductor substrate 12.
  • the microlens 1111, the color filter 1112, the transparent resin layer 1113, the light shielding film 1114, and the antireflection film 1115 are not formed on the first semiconductor substrate 11.
  • Process 2 The first semiconductor substrate 11 and the second semiconductor substrate 12 formed in step 1 are stacked. At this time, as shown in FIG. 4, the surface of the first semiconductor substrate 11 on the first wiring layer 1118 side and the surface of the second semiconductor substrate 12 on the second wiring layer 1201 side are opposed to each other, Bonding is performed using an adhesive layer 1130.
  • a solid-state imaging device (solid-state imaging device 10) including a through-electrode (silicon through electrode 1204) that penetrates the semiconductor layer 1203 is configured.
  • connection electrodes overlap the region of the pixel array unit 111 on the side opposite to the side where the light beam enters the pixel array unit 111.
  • the solid-state imaging device 10 arranged in the above is configured.
  • the semiconductor device further includes a support substrate (support substrate 13) that supports a state in which the first semiconductor substrate 11 and the second semiconductor substrate 12 are stacked.
  • a solid-state imaging device 10 made of the same material as the first semiconductor substrate 11 and the second semiconductor substrate 12 is configured.
  • connection electrodes are signal lines between circuit elements formed in the first semiconductor substrate 11 or the second semiconductor substrate 12.
  • the solid-state imaging device 10 formed of a material different from a metal wiring (metal wiring 1119 or metal wiring 1202) formed to connect signal lines between circuit elements formed therein is configured.
  • An electrode is formed. That is, in the solid-state imaging device 10 according to the first embodiment, unlike the conventional solid-state imaging device, the light (light ray) is incident instead of forming the through silicon via from the surface on which light (light ray) is incident.
  • a through-silicon electrode 1204 and a back electrode 1205 are formed from the surface opposite to the side to be processed, and signal lines of circuit elements formed on the first semiconductor substrate 11 and circuit elements formed on the second semiconductor substrate 12 Electrically connect to the signal line.
  • the connection electrode can be formed without blocking light (light rays) incident on the pixel.
  • the performance and function of the solid-state imaging device 10 can be improved by stacking the first semiconductor substrate 11 and the second semiconductor substrate 12. At the same time, it is possible to improve the degree of freedom of wiring formed for connecting the respective semiconductor substrates, and to realize miniaturization.
  • the connection electrode can be formed even in the region immediately below the region where the pixel array unit 111 is formed, the first semiconductor substrate 11 and the second semiconductor substrate 11 can be formed. It is possible to reduce the length of the wiring connecting the respective components formed on the semiconductor substrate 12. In other words, in the conventional solid-state imaging device, depending on the position where each component is arranged, it is necessary to provide wiring so as to bypass the region of the pixel array portion. In the solid-state imaging device 10 of the first embodiment, it is possible to form a wiring having a shorter length without bypassing the region of the pixel array unit.
  • the delay of the signal line exchanged between the first semiconductor substrate 11 and the second semiconductor substrate 12 increases according to the length of the wiring. Therefore, the performance and function of the solid-state imaging device 10 can be further improved.
  • the case where the silicon substrate similar to the first semiconductor substrate 11 and the second semiconductor substrate 12 is used as the support substrate 13 has been described, but as described above.
  • a circuit for realizing the function of the solid-state imaging device 10 is not formed on the support substrate 13. That is, any material such as a glass substrate or a resin substrate can be used as long as it supports the first semiconductor substrate 11 and the second semiconductor substrate 12 that are stacked and thinned to maintain the mechanical strength. It may be a substrate.
  • FIG. 5 is a cross-sectional view showing the structure of the solid-state imaging device according to the second embodiment of the present invention.
  • solid-state imaging device 20 the first semiconductor substrate 11 and the second semiconductor substrate 12 that are stacked and thinned are used.
  • a glass substrate is used as the supporting substrate to be supported will be described.
  • the configuration of the first semiconductor substrate 11 and the second semiconductor substrate 12 in the solid-state imaging device 20 of the second embodiment is the same as that of the solid-state imaging device 10 of the first embodiment shown in FIGS. It is the same composition. Therefore, in the following description, each component of the solid-state imaging device 20 of the second embodiment will be described using the same reference numerals as those of the solid-state imaging device 10 of the first embodiment, and the second embodiment will be described. A detailed description of the configuration of the solid-state imaging device 20 and the respective components will be omitted.
  • FIG. 5 shows the pixels in the pixel array unit 111 in the solid-state imaging device 20 having a configuration in which the first semiconductor substrate 11 and the second semiconductor substrate 12 are stacked, like the solid-state imaging device 10 shown in FIG. A part of the structure of the region where is formed is shown.
  • the first semiconductor substrate 11 and the second semiconductor substrate 12 are bonded as in the solid-state imaging device 10.
  • FIG. 5 An example in which each semiconductor substrate is directly bonded is shown.
  • the first semiconductor substrate 11 and the second semiconductor substrate 12 are bonded, and further, the glass substrate 14 is bonded to the first semiconductor substrate 11 as a support substrate.
  • the glass substrate 14 is a substrate that transmits light.
  • the surface of the first semiconductor substrate 11 on the first semiconductor layer 1116 side that is, the light (light beam) on which the microlenses 1111 are formed on the first semiconductor substrate 11. Is bonded to the surface on the side where the light enters.
  • the first semiconductor substrate 11 and the glass substrate 14 are bonded by, for example, a transparent resin adhesive.
  • the mechanical strength of the thinned first semiconductor substrate 11 and second semiconductor substrate 12 is maintained by the glass substrate 14.
  • the surface of the second semiconductor substrate 12 on the second semiconductor layer 1203 side that is, the side opposite to the side on which light (light rays) enters the solid-state imaging device 20.
  • a protective film 1530 and a protruding electrode 1501 are formed on the surface.
  • the protective film 1530 is a film for protecting the connection electrode formed to electrically connect the first semiconductor substrate 11 and the second semiconductor substrate 12. More specifically, the protective film 1530 includes the silicon through electrode 1204 that penetrates the second semiconductor layer 1203 and is connected to the metal wiring 1202 in the second wiring layer 1201, the second semiconductor layer 1203, and the second semiconductor layer 1203. A connection electrode constituted by a silicon through electrode 1204 that penetrates through the two wiring layers 1201 and is connected to the metal wiring 1119 in the first wiring layer 1118 and a back electrode 1205 that connects each silicon through electrode 1204. Protect.
  • the protective film 1530 is, for example, a protective film such as a silicon oxide film or a silicon nitride film. Further, the protective film 1530 may be a resin film such as a polyimide resin, for example.
  • the protective film 1530 is provided with a concave opening at the position of the back electrode 1205 for the solid-state imaging device 20 to input / output an electric signal to / from an external circuit.
  • a protruding electrode 1501 connected to the back electrode 1205 is formed in the opening.
  • the protruding electrode 1501 is a terminal for the solid-state imaging device 20 to input and output signals with the outside. Unlike the solid-state imaging device 10 of the first embodiment, the solid-state imaging device 20 exchanges electric signals with an external circuit via the protruding electrodes 1501.
  • the protruding electrode 1501 is formed of a metal material such as solder, gold, copper, or tin, for example.
  • the solid-state imaging device 20 is configured such that, for example, the chip electrode 1501 can be flip-chip mounted on a mounting substrate on which electronic components are mounted.
  • the electrical signal output from the solid-state imaging device 20 is output to an external circuit via the corresponding back surface electrode 1205 and protruding electrode 1501.
  • an electrical signal input from an external circuit is input to each component in the solid-state imaging device 20 via the corresponding protruding electrode 1501 and back electrode 1205.
  • the solid-state imaging device 20 has a final structure by proceeding with the respective steps in the following order.
  • each of the first semiconductor layer 1116 and the first wiring layer 1118 is formed on the first semiconductor substrate 11.
  • the second semiconductor layer 1203 and the second wiring layer 1201 are formed on the second semiconductor substrate 12.
  • the microlens 1111, the color filter 1112, the transparent resin layer 1113, the light shielding film 1114, and the antireflection film 1115 are: It is not formed on the first semiconductor substrate 11.
  • the first semiconductor substrate 11 and the second semiconductor substrate 12 formed in step 1 are stacked. At this time, as shown in FIG. 5, the surface on the first wiring layer 1118 side of the first semiconductor substrate 11 and the surface on the second wiring layer 1201 side of the second semiconductor substrate 12 are opposed to each other. Join directly.
  • a connection film such as a silicon oxide film or a silicon nitride film is provided on each surface of the first semiconductor substrate 11 and the second semiconductor substrate 12 to be bonded, and this connection film is used as an adhesive layer. It may be used as a joint.
  • An antireflection film 1115, a light shielding film 1114, a transparent resin layer 1113, a color filter 1112, and a microlens 1111 are sequentially formed on the surface of the first semiconductor substrate 11 on the first semiconductor layer 1116 side.
  • a glass substrate 14 is laminated on the surface of the first semiconductor substrate 11 on which the microlenses 1111 are formed.
  • Step 6 In a state where the glass substrate 14 is bonded to the first semiconductor substrate 11 and the second semiconductor substrate 12, the silicon layer on the surface of the second semiconductor substrate 12 on the second semiconductor layer 1203 side is etched, and the second semiconductor substrate 120 is etched. The semiconductor substrate 12 is thinned.
  • Step 7 A silicon through electrode 1204 and a back electrode 1205 are formed from the surface of the second semiconductor substrate 12 on the second semiconductor layer 1203 side.
  • the signal line and the signal line of the circuit element formed on the second semiconductor substrate 12 are electrically connected.
  • a connection electrode composed of a silicon through electrode 1204 and a back electrode 1205 that inputs / outputs an electric signal to / from an external circuit hereinafter referred to as “input / output electrode” when the connection electrode is distinguished).
  • the circuit element formed on the first semiconductor substrate 11 or the circuit element formed on the second semiconductor substrate 12 can exchange electric signals with the outside.
  • a protective film 1530 is formed on the surface of the second semiconductor substrate 12 on which the connection electrode is formed. Then, after removing the protective film 1530 at the position of the input / output electrode, the protruding electrode 1501 is formed in this portion.
  • the semiconductor device further includes a support substrate (glass substrate 14) that supports a state in which the first semiconductor substrate 11 and the second semiconductor substrate 12 are stacked.
  • a solid-state imaging device (solid-state imaging device 20) that is a different material from the semiconductor substrate 11 and the second semiconductor substrate 12 is configured.
  • connection electrodes are signal lines between circuit elements formed in the first semiconductor substrate 11 or the second semiconductor substrate 12.
  • a solid-state imaging device 20 formed of a material different from a metal wiring (metal wiring 1119 or metal wiring 1202) formed to connect signal lines between circuit elements formed therein is configured.
  • connection electrodes are signal lines between circuit elements formed in the first semiconductor substrate 11 or the second semiconductor substrate 12.
  • a solid-state imaging device 20 formed of the same material as a metal wiring (metal wiring 1119 or metal wiring 1202) formed to connect signal lines between circuit elements formed therein is configured.
  • the solid-state imaging device 20 of the second embodiment As described above, in the solid-state imaging device 20 of the second embodiment as well as the solid-state imaging device 10 of the first embodiment, from the surface of the second semiconductor substrate 12 on the second semiconductor layer 1203 side. A connection electrode composed of the through silicon via 1204 and the back electrode 1205 is formed. Thereby, also in the solid-state imaging device 20 of 2nd Embodiment, the effect similar to the solid-state imaging device 10 of 1st Embodiment can be acquired.
  • the protruding electrode 1501 is formed on the surface opposite to the side on which light (light rays) enters the solid-state imaging device 20.
  • the first semiconductor substrate 11 and the second semiconductor substrate 12 that are stacked and thinned are supported on the surface on the light incident side of the solid-state imaging device 20.
  • a configuration is shown in which a glass substrate 14 is bonded as a support substrate, and a protective film 1530 and a protruding electrode 1501 are formed on the surface opposite to the side on which light (light rays) enters the solid-state imaging device 20.
  • the glass substrate 14 may be used as a support substrate in a solid-state imaging device having a configuration in which the protective film 1530 and the protruding electrode 1501 are not formed on the surface opposite to the side on which light (light rays) enters the solid-state imaging device 20. Good.
  • a glass substrate 14 may be bonded to the surface on the light incident side of the solid-state imaging device 10.
  • the input / output electrodes are not formed in step 7 and the protruding electrodes 1501 are not formed in the subsequent step 8. The only difference is.
  • the height (thickness) of the back electrode 1205 at the position where the protruding electrode 1501 is formed is the same as or higher than the protective film 1530 (thicker).
  • the back electrode 1205 at that portion may be used as a terminal for the solid-state imaging device 20 to input / output an electric signal to / from an external circuit.
  • the solid-state imaging device 20 shown in FIG. 5 is shaped like a BGA (Ball grid array), but may be shaped like a LGA (Land grid array). Even a solid-state imaging device having this configuration can be flip-chip mounted on a mounting substrate on which electronic components are mounted.
  • the first semiconductor substrate 11 and the second semiconductor substrate 12 that are stacked and thinned are used.
  • the substrate may be made of any material as long as it supports the substrate and maintains the mechanical strength.
  • the resin used for adjusting the refractive index of light in the microlens 1111 formed on the first semiconductor substrate 11 is used as a material for the support substrate, and plays a role of both maintaining the mechanical strength and adjusting the refractive index. It may be.
  • the role of the support substrate in the solid-state imaging device is only to maintain the mechanical strength of the first semiconductor substrate 11 and the second semiconductor substrate 12 that are stacked and thinned in the manufacturing process of the solid-state imaging device.
  • a material that can be removed after mounting the solid-state imaging device on the mounting substrate on which the electronic component is mounted may be used as the material of the support substrate.
  • a through silicon via electrode is formed from a surface opposite to a side on which light (light rays) is incident.
  • a connection electrode composed of a back electrode is formed, and signal lines of circuit elements formed on the respective semiconductor substrates are electrically connected.
  • the performance and function of the solid-state imaging device is improved by stacking a plurality of semiconductor substrates, and the degree of freedom of wiring formed to connect each semiconductor substrate is increased.
  • the solid-state imaging device can be downsized.
  • the delay of signal lines exchanged between components formed on each semiconductor substrate can be reduced, and the performance and function of the solid-state imaging device can be further improved. .
  • the configuration of the solid-state imaging device in which two semiconductor substrates of the first semiconductor substrate 11 and the second semiconductor substrate 12 are stacked has been described.
  • the number of substrates stacked in the solid-state imaging device is not limited to two, and a configuration in which a larger number of substrates is stacked may be used.
  • the configuration including the configuration for supporting the stacked semiconductor substrates (the support substrate 13 in the first embodiment and the glass substrate 14 in the second embodiment) has been described.
  • the mechanical strength of the stacked semiconductor substrates can be maintained by reducing the amount of thinning of any of the stacked semiconductor substrates, that is, by increasing the thickness
  • the first connection electrode array 124 or the second connection electrode array 125 is joined via the corresponding connection electrode portion disposed in the first connection electrode array 124 or the second connection electrode array 125.
  • the configuration in which the electrical signals are transmitted and received between the components arranged on the first semiconductor substrate 11 and the second semiconductor substrate 12 has been described.
  • the connection electrode formed by the through silicon via 1204 and the back electrode 1205 is not formed only in the region immediately below the pixel described above, but the first connection electrode array 124 and the second connection electrode array 125. You may comprise in the area
  • connection electrode made up of the through silicon via 1204 and the back electrode 1205 is not only applied to the solid-state imaging device, but a plurality of semiconductor substrates are stacked, and signals between circuit elements formed on the respective semiconductor substrates.
  • the idea of the present invention can be applied to any semiconductor device in which wires are electrically connected.
  • Solid-state imaging device 11 First semiconductor substrate 111 Pixel array unit (pixel, pixel unit, first semiconductor substrate) 112 Horizontal drive circuit (processing unit) 113 Bonding pad 1111 Microlens (pixel, pixel portion, first semiconductor substrate) 1112 Color filter (pixel, pixel portion, first semiconductor substrate) 1113 Transparent resin layer (pixel, pixel portion, first semiconductor substrate) 1114 Light-shielding film (pixel, pixel portion, first semiconductor substrate) 1115 Antireflection film (pixel, pixel portion, first semiconductor substrate) 1116 First semiconductor layer (first semiconductor substrate) 1117 Photoelectric conversion unit (pixel) 1118 First wiring layer (first semiconductor substrate) 1119 Metal wiring (first semiconductor substrate) 1130 Adhesive layer 12 Second semiconductor substrate 121 Vertical drive circuit (processing unit) 122 column processing circuit (processing unit) 123 Signal processing circuit (processing unit) 124 first connection electrode array 125 second connection electrode array 1201 second wiring layer (second semiconductor substrate) 1202 Metal wiring (second semiconductor substrate) 1203 Second semiconductor layer (second semiconductor substrate) 1204 Silicon through electrode

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Abstract

The present invention is provided with: a first semiconductor substrate having a first semiconductor layer having formed therein circuit elements of a pixel unit that has disposed therein a plurality of pixels in two-dimensional matrix, each of said pixels being provided with a photoelectric conversion unit, which converts an inputted light beam into electrical signals, and outputs the electrical signals; a second semiconductor substrate having a second semiconductor layer having formed therein circuit elements of a processing unit that performs processing with respect to the electrical signals outputted from the photoelectric conversion unit; and a connecting electrode that electrically connects signal lines of the circuit elements formed in the first semiconductor layer, and signal lines of the circuit elements formed in the second semiconductor layer to each other, in a state wherein the first semiconductor substrate and the second semiconductor substrate are laminated to each other. The connecting electrode is provided with a through electrode that penetrates the second semiconductor layer in the second semiconductor substrate.

Description

固体撮像装置Solid-state imaging device
　本発明は、固体撮像装置に関する。 The present invention relates to a solid-state imaging device.
　近年、ビデオカメラや電子スチルカメラなどの撮像装置が広く一般に普及している。これらの撮像装置（以下、「カメラ」という）には、ＣＣＤ（Ｃｈａｒｇｅ　Ｃｏｕｐｌｅｄ　Ｄｅｖｉｃｅ：電荷結合素子）型の固体撮像装置や、増幅型の固体撮像装置が使用されている。増幅型の固体撮像装置は、光が入射する画素内に設けられたフォトダイオードなどの光電変換部が生成、蓄積した電気信号を、画素内に設けられた増幅部に導き、増幅部が増幅した信号を画素から出力する。増幅型の固体撮像装置では、このような画素が二次元のマトリクス状に複数配置されて、画素アレイ部が形成されている。増幅型の固体撮像装置には、例えば、ＣＭＯＳ（Ｃｏｍｐｌｅｍｅｎｔａｒｙ　Ｍｅｔａｌ　Ｏｘｉｄｅ　Ｓｅｍｉｃｏｎｄｕｃｔｏｒ：相補型金属酸化膜半導体）トランジスタを用いたＣＭＯＳ型固体撮像装置などがある。 In recent years, imaging devices such as video cameras and electronic still cameras have been widely used. For these imaging devices (hereinafter referred to as “cameras”), CCD (Charge Coupled Device) type solid-state imaging devices and amplification type solid-state imaging devices are used. An amplification type solid-state image pickup device introduces an electric signal generated and accumulated by a photoelectric conversion unit such as a photodiode provided in a pixel to which light enters to the amplification unit provided in the pixel, and the amplification unit amplifies the signal. A signal is output from the pixel. In the amplification type solid-state imaging device, a plurality of such pixels are arranged in a two-dimensional matrix to form a pixel array unit. Examples of the amplification type solid-state imaging device include a CMOS type solid-state imaging device using a CMOS (Complementary Metal Oxide Semiconductor: complementary metal oxide semiconductor) transistor.
　従来のＣＭＯＳ型固体撮像装置は、二次元のマトリクス状に配列された各画素内の光電変換部が生成、蓄積した電気信号を、同一の基板上に設けられた回路部によって行毎に順次読み出す方式を採用している。一般的なモノリシック構造（単一の半導体基板で製造された構造）を有したＣＭＯＳ型固体撮像装置では、光が入射する面から見たとき、入射した光を電気信号に変換する複数の画素が形成された画素アレイ部の周囲には、周辺回路が配置されている。この周辺回路は、垂直走査回路、水平走査回路、列処理回路、出力回路などのロジック回路である。そして、画素アレイ部とこれらの周辺回路との間には、電気信号を伝達するための配線が、列毎または行毎に設けられている。 In a conventional CMOS solid-state imaging device, electrical signals generated and accumulated by photoelectric conversion units in each pixel arranged in a two-dimensional matrix are sequentially read out row by row by a circuit unit provided on the same substrate. The method is adopted. In a CMOS type solid-state imaging device having a general monolithic structure (a structure manufactured from a single semiconductor substrate), when viewed from the light incident surface, a plurality of pixels that convert incident light into electrical signals are provided. A peripheral circuit is disposed around the formed pixel array portion. This peripheral circuit is a logic circuit such as a vertical scanning circuit, a horizontal scanning circuit, a column processing circuit, and an output circuit. A wiring for transmitting an electrical signal is provided for each column or row between the pixel array portion and these peripheral circuits.
　ところで、近年のＣＭＯＳ型固体撮像装置には、データレートの向上、面内の撮像性能の同一性の向上、高機能化などの要求がされている。しかしながら、従来のモノリシック構造を有したＣＭＯＳ型固体撮像装置では、平面方向の電気伝導における速度制限や密度制限などによって、性能を向上させることが難しい。また、近年のＣＭＯＳ型固体撮像装置には、サイズの小型化も要求されているが、周辺回路を画素アレイ部の周辺に配置するため、基板平面の面積を小さくすることが難しい。 By the way, recent CMOS type solid-state imaging devices are required to improve the data rate, improve the in-plane imaging performance, and increase the functionality. However, it is difficult to improve the performance of a conventional CMOS solid-state imaging device having a monolithic structure due to speed limitation and density limitation in electrical conduction in a planar direction. Further, recent CMOS type solid-state imaging devices are required to be reduced in size, but it is difficult to reduce the area of the substrate plane because peripheral circuits are arranged around the pixel array portion.
　そこで、複数の画素が配置された画素アレイが形成された半導体基板と、信号処理などを行う周辺のロジック回路が形成された半導体基板とを積層し、それぞれの半導体基板を電気的に接続して１つの半導体デバイスとして構成したＣＭＯＳ型固体撮像装置が提案されている。このように複数の半導体基板を積層することによって、ＣＭＯＳ型固体撮像装置における性能や機能の向上と小型化とを実現している。 Therefore, a semiconductor substrate on which a pixel array in which a plurality of pixels are arranged is formed and a semiconductor substrate on which peripheral logic circuits for performing signal processing and the like are stacked, and the respective semiconductor substrates are electrically connected. A CMOS type solid-state imaging device configured as one semiconductor device has been proposed. Thus, by laminating a plurality of semiconductor substrates, the performance and function of the CMOS solid-state imaging device are improved and the size is reduced.
　例えば、特許文献１には、画素アレイ部が形成された第１の半導体チップと、ロジック回路が形成された第２の半導体チップとが張り合わされた構成の積層型のＣＭＯＳ型固体撮像装置が開示されている。この特許文献１に開示されたＣＭＯＳ型固体撮像装置は、第１の半導体チップの裏面側から入射した光を受光する裏面照射（ＢａｃｋＳｉｄｅ　Ｉｌｌｕｍｉｎａｔｉｏｎ：ＢＳＩ）型の固体撮像装置である。特許文献１に開示されたＣＭＯＳ型固体撮像装置では、第１の半導体チップの一部の半導体部分が除去された半導体除去領域が設けられている。そして、この半導体除去領域内に、第１の半導体チップと第２の半導体チップとの間を接続するための複数の接続配線が、第１の半導体チップを貫通するように形成されている。 For example, Patent Document 1 discloses a stacked CMOS solid-state imaging device having a configuration in which a first semiconductor chip in which a pixel array portion is formed and a second semiconductor chip in which a logic circuit is formed are bonded together. Has been. The CMOS type solid-state imaging device disclosed in Patent Document 1 is a backside illumination (BSI) type solid-state imaging device that receives light incident from the back side of a first semiconductor chip. In the CMOS-type solid-state imaging device disclosed in Patent Document 1, a semiconductor removal region in which a part of the semiconductor portion of the first semiconductor chip is removed is provided. In the semiconductor removal region, a plurality of connection wirings for connecting the first semiconductor chip and the second semiconductor chip are formed so as to penetrate the first semiconductor chip.
日本国特開２０１１－１５１３７５号公報Japanese Unexamined Patent Publication No. 2011-151375
　ところで、固体撮像装置では、光電変換部を含む複数の画素が、二次元のマトリクス状に配置されて画素アレイ部が形成されている。このため、特許文献１に開示されたＣＭＯＳ型固体撮像装置では、第１の半導体チップにおいて画素アレイ部か形成された領域以外の領域に半導体除去領域を設ける必要がある。そして、特許文献１に開示されたＣＭＯＳ型固体撮像装置では、画素アレイ部の周辺部分に設けられた半導体除去領域内に形成された接続配線によって、第１の半導体チップと第２の半導体チップとの間でやり取りされる信号線が接続されている。このため、特許文献１に開示された技術を適用した場合でも、固体撮像装置の小型化の実現に対しては、チップサイズや設計ルールなどに一定の制限が設けられることになる。つまり、特許文献１に開示されたＣＭＯＳ型固体撮像装置は、画素アレイ部の領域と半導体除去領域とを合わせた大きさよりも小型化することが困難である。 By the way, in a solid-state imaging device, a plurality of pixels including a photoelectric conversion unit are arranged in a two-dimensional matrix to form a pixel array unit. For this reason, in the CMOS type solid-state imaging device disclosed in Patent Document 1, it is necessary to provide a semiconductor removal region in a region other than the region where the pixel array portion is formed in the first semiconductor chip. In the CMOS type solid-state imaging device disclosed in Patent Document 1, the first semiconductor chip and the second semiconductor chip are connected by the connection wiring formed in the semiconductor removal region provided in the peripheral portion of the pixel array portion. Signal lines that are exchanged between the two are connected. For this reason, even when the technique disclosed in Patent Document 1 is applied, certain restrictions are imposed on the chip size, the design rules, and the like for realizing the downsizing of the solid-state imaging device. That is, it is difficult to reduce the size of the CMOS solid-state imaging device disclosed in Patent Document 1 beyond the combined size of the pixel array region and the semiconductor removal region.
　また、特許文献１に開示されたＣＭＯＳ型固体撮像装置では、画素アレイ部の周辺部分に設けられた半導体除去領域内に形成された接続配線によって、第１の半導体チップと第２の半導体チップとが電気的に接続される。このため、第１の半導体チップと第２の半導体チップとの間でやり取りされるそれぞれの信号線の配置が制限される。つまり、特許文献１に開示された技術では、第１の半導体チップと第２の半導体チップとの間を接続する接続配線の配置に自由度が少ない。 In the CMOS type solid-state imaging device disclosed in Patent Document 1, the first semiconductor chip and the second semiconductor chip are connected by connection wiring formed in a semiconductor removal region provided in the peripheral portion of the pixel array portion. Are electrically connected. For this reason, the arrangement of the respective signal lines exchanged between the first semiconductor chip and the second semiconductor chip is limited. That is, in the technique disclosed in Patent Document 1, the degree of freedom is small in the arrangement of the connection wiring that connects the first semiconductor chip and the second semiconductor chip.
　本発明は、上記の課題に基づいてなされたものであり、複数の半導体基板を積層した構成の固体撮像装置において、性能や機能の向上と共に、それぞれの半導体基板を接続する配線の自由度を向上させて小型化を実現することができる固体撮像装置を提供することを目的としている。 The present invention has been made based on the above problems, and in a solid-state imaging device having a configuration in which a plurality of semiconductor substrates are stacked, the performance and functions are improved, and the degree of freedom of wiring for connecting each semiconductor substrate is improved. An object of the present invention is to provide a solid-state imaging device that can be reduced in size.
　本発明の第１の態様の固体撮像装置は、入射された光線を電気信号に変換して出力する光電変換部を具備した画素が二次元のマトリクス状に複数配置された画素部の回路要素が形成された第１の半導体層を有する第１の半導体基板と、前記光電変換部が出力した前記電気信号に対して処理を行う処理部の回路要素が形成された第２の半導体層を有する第２の半導体基板と、前記第１の半導体基板と前記第２の半導体基板とを積層した状態で、前記第１の半導体層に形成された回路要素の信号線と、前記第２の半導体層に形成された回路要素の信号線とを電気的に接続する接続電極と、を備え、前記接続電極は、前記第２の半導体基板内の第２の半導体層を貫通する貫通電極、を備える。 The solid-state imaging device according to the first aspect of the present invention includes a circuit element of a pixel unit in which a plurality of pixels each having a photoelectric conversion unit that converts incident light into an electrical signal and outputs the electrical signal is arranged in a two-dimensional matrix. A first semiconductor substrate having a formed first semiconductor layer, and a second semiconductor layer having a second semiconductor layer on which circuit elements of a processing unit for processing the electrical signal output from the photoelectric conversion unit are formed. A signal line of a circuit element formed in the first semiconductor layer in a state in which the second semiconductor substrate, the first semiconductor substrate, and the second semiconductor substrate are stacked; A connection electrode that electrically connects a signal line of the formed circuit element, and the connection electrode includes a through electrode that penetrates the second semiconductor layer in the second semiconductor substrate.
　本発明の第２の態様によれば、上記第１の態様の固体撮像装置において、前記接続電極は、前記画素部に前記光線が入射する側とは反対側で、前記画素部の領域に重なるように配置されていてもよい。 According to the second aspect of the present invention, in the solid-state imaging device according to the first aspect, the connection electrode overlaps a region of the pixel unit on a side opposite to a side on which the light ray enters the pixel unit. It may be arranged as follows.
　本発明の第３の態様によれば、上記第２の態様の固体撮像装置は、前記第１の半導体基板と前記第２の半導体基板とが積層された状態を支持する支持基板、をさらに備え、前記支持基板は、前記第１の半導体基板および前記第２の半導体基板と同じ材料であってもよい。 According to a third aspect of the present invention, the solid-state imaging device according to the second aspect further includes a support substrate that supports a state in which the first semiconductor substrate and the second semiconductor substrate are stacked. The support substrate may be made of the same material as the first semiconductor substrate and the second semiconductor substrate.
　本発明の第４の態様によれば、上記第２の態様の固体撮像装置は、前記第１の半導体基板と前記第２の半導体基板とが積層された状態を支持する支持基板、をさらに備え、前記支持基板は、前記第１の半導体基板および前記第２の半導体基板と異なる材料であってもよい。 According to a fourth aspect of the present invention, the solid-state imaging device according to the second aspect further includes a support substrate that supports a state in which the first semiconductor substrate and the second semiconductor substrate are stacked. The support substrate may be made of a material different from that of the first semiconductor substrate and the second semiconductor substrate.
　本発明の第５の態様によれば、上記第３の態様の固体撮像装置において、前記接続電極は、前記第１の半導体基板内に形成された回路要素同士の信号線、または前記第２の半導体基板内に形成された回路要素同士の信号線を接続するために形成される金属配線と異なる材料によって形成されていてもよい。 According to a fifth aspect of the present invention, in the solid-state imaging device according to the third aspect, the connection electrode is a signal line between circuit elements formed in the first semiconductor substrate, or the second You may form with the material different from the metal wiring formed in order to connect the signal wire | line of the circuit elements formed in the semiconductor substrate.
　本発明の第６の態様によれば、上記第４の態様の固体撮像装置において、前記接続電極は、前記第１の半導体基板内に形成された回路要素同士の信号線、または前記第２の半導体基板内に形成された回路要素同士の信号線を接続するために形成される金属配線と異なる材料によって形成されていてもよい。 According to a sixth aspect of the present invention, in the solid-state imaging device according to the fourth aspect, the connection electrode is a signal line between circuit elements formed in the first semiconductor substrate, or the second You may form with the material different from the metal wiring formed in order to connect the signal wire | line of the circuit elements formed in the semiconductor substrate.
　本発明の第７の態様によれば、上記第３の態様の固体撮像装置において、前記接続電極は、前記第１の半導体基板内に形成された回路要素同士の信号線、または前記第２の半導体基板内に形成された回路要素同士の信号線を接続するために形成される金属配線と同じ材料によって形成されていてもよい。 According to a seventh aspect of the present invention, in the solid-state imaging device according to the third aspect, the connection electrode is a signal line between circuit elements formed in the first semiconductor substrate, or the second You may form with the same material as the metal wiring formed in order to connect the signal wire | line of the circuit elements formed in the semiconductor substrate.
　本発明の第８の態様によれば、上記第４の態様の固体撮像装置において、前記接続電極は、前記第１の半導体基板内に形成された回路要素同士の信号線、または前記第２の半導体基板内に形成された回路要素同士の信号線を接続するために形成される金属配線と同じ材料によって形成されていてもよい。 According to an eighth aspect of the present invention, in the solid-state imaging device according to the fourth aspect, the connection electrode is a signal line between circuit elements formed in the first semiconductor substrate, or the second You may form with the same material as the metal wiring formed in order to connect the signal wire | line of the circuit elements formed in the semiconductor substrate.
　上記各態様によれば、複数の半導体基板を積層した構成の固体撮像装置において、性能や機能の向上と共に、それぞれの半導体基板を接続する配線の自由度を向上させて小型化を実現することができる。 According to each of the above aspects, in a solid-state imaging device having a configuration in which a plurality of semiconductor substrates are stacked, performance and functions can be improved, and the degree of freedom of wiring for connecting each semiconductor substrate can be improved to achieve miniaturization. it can.
本発明の第１の実施形態の固体撮像装置の概略構成を示した概観図である。1 is an overview diagram illustrating a schematic configuration of a solid-state imaging device according to a first embodiment of the present invention. 本発明の第１の実施形態の固体撮像装置を光が入射する側から見たときの概略構成を示した平面図である。It is the top view which showed schematic structure when the solid-state imaging device of the 1st Embodiment of this invention is seen from the light incident side. 本発明の第１の実施形態の固体撮像装置における第１の半導体基板および第２の半導体基板の構成を示した図である。It is the figure which showed the structure of the 1st semiconductor substrate and 2nd semiconductor substrate in the solid-state imaging device of the 1st Embodiment of this invention. 本発明の第１の実施形態の固体撮像装置の構造を示した断面図である。It is sectional drawing which showed the structure of the solid-state imaging device of the 1st Embodiment of this invention. 本発明の第２の実施形態の固体撮像装置の構造を示した断面図である。It is sectional drawing which showed the structure of the solid-state imaging device of the 2nd Embodiment of this invention.
（第１の実施形態）
　以下、本発明の実施形態について、図面を参照して説明する。図１は、本発明の第１の実施形態の固体撮像装置の概略構成を示した概観図である。第１の実施形態の固体撮像装置１０は、複数の基板を積層することによって構成されている。図１において、固体撮像装置１０は、第１の半導体基板１１と第２の半導体基板１２とが接合されている。さらに、固体撮像装置１０は、第２の半導体基板１２に支持基板１３が接合されている。 (First embodiment)
Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is an overview showing a schematic configuration of a solid-state imaging device according to the first embodiment of the present invention. The solid-state imaging device 10 according to the first embodiment is configured by stacking a plurality of substrates. In FIG. 1, in a solid-state imaging device 10, a first semiconductor substrate 11 and a second semiconductor substrate 12 are bonded. Further, in the solid-state imaging device 10, a support substrate 13 is bonded to the second semiconductor substrate 12.
　固体撮像装置１０は、固体撮像装置１０の機能を実現するための回路が、第１の半導体基板１１または第２の半導体基板１２のいずれか一方の半導体基板上に形成されている。固体撮像装置１０の機能を実現するための回路は、入射してきた光（光線）を電気信号に変換するフォトダイオードなどの光電変換部を含む画素が二次元のマトリクス状に複数配置された画素アレイ部、光電変換部によって光電変換された電気信号を処理する列処理回路、画素アレイ部内の画素を駆動するための駆動回路、および列処理回路によって処理された電気信号を信号処理する信号処理回路などである。固体撮像装置１０では、画素アレイ部が第１の半導体基板１１に形成されている。そして、固体撮像装置１０は、第１の半導体基板１１が、光が入射してくる側の面がシリコン層となるように第２の半導体基板１２と接合された、いわゆる、裏面照射（ＢａｃｋＳｉｄｅ　Ｉｌｌｕｍｉｎａｔｉｏｎ：ＢＳＩ）型の固体撮像装置と同様の構成である。 In the solid-state imaging device 10, a circuit for realizing the function of the solid-state imaging device 10 is formed on one of the first semiconductor substrate 11 and the second semiconductor substrate 12. A circuit for realizing the function of the solid-state imaging device 10 is a pixel array in which a plurality of pixels including photoelectric conversion units such as photodiodes that convert incident light (light rays) into electric signals are arranged in a two-dimensional matrix. Unit, a column processing circuit that processes the electrical signal photoelectrically converted by the photoelectric conversion unit, a drive circuit for driving the pixels in the pixel array unit, and a signal processing circuit that processes the electrical signal processed by the column processing circuit, etc. It is. In the solid-state imaging device 10, the pixel array unit is formed on the first semiconductor substrate 11. The solid-state imaging device 10 has a so-called backside illumination in which the first semiconductor substrate 11 is bonded to the second semiconductor substrate 12 so that the surface on which light is incident is a silicon layer. : BSI) type solid-state imaging device.
　なお、第１の半導体基板１１と第２の半導体基板１２とを接合する方法としては、接着層を設けてもよいし、第１の半導体基板１１と第２の半導体基板１２とを直接接合してもよい。接着層を設けて第１の半導体基板１１と第２の半導体基板１２とを接合する方法としては、例えば、樹脂接着剤などの樹脂膜を接着層として用いて半導体基板同士を接合（積層）する方法が考えられる。このとき、接着層には、第１の半導体基板１１と第２の半導体基板１２との信号を電気的に接続するための接続電極部を含んでいてもよい。また、第１の半導体基板１１と第２の半導体基板１２とを直接接合する方法としては、例えば、それぞれの半導体基板の酸化膜同士や金属部分同士に前処理を施し、表面活性化によるプラズマ接合によって半導体基板同士を直接的に接合（積層）する方法が考えられる。このとき、第１の半導体基板１１と第２の半導体基板１２とを直接接合する場合においても、例えば、シリコン酸化膜やシリコン窒化膜などの接続用の膜を設けて接着層として用いてもよい。なお、第１の実施形態の固体撮像装置１０の構成においては、第１の半導体基板１１と第２の半導体基板１２とを直接接合する方法が望ましい。 Note that as a method of bonding the first semiconductor substrate 11 and the second semiconductor substrate 12, an adhesive layer may be provided, or the first semiconductor substrate 11 and the second semiconductor substrate 12 are directly bonded. May be. As a method for bonding the first semiconductor substrate 11 and the second semiconductor substrate 12 by providing an adhesive layer, for example, the semiconductor substrates are bonded (laminated) using a resin film such as a resin adhesive as the adhesive layer. A method is conceivable. At this time, the adhesive layer may include a connection electrode portion for electrically connecting signals between the first semiconductor substrate 11 and the second semiconductor substrate 12. In addition, as a method of directly bonding the first semiconductor substrate 11 and the second semiconductor substrate 12, for example, pretreatment is performed on oxide films or metal portions of the respective semiconductor substrates, and plasma bonding by surface activation is performed. A method of directly bonding (stacking) semiconductor substrates to each other can be considered. At this time, even when the first semiconductor substrate 11 and the second semiconductor substrate 12 are directly bonded, for example, a connection film such as a silicon oxide film or a silicon nitride film may be provided and used as an adhesive layer. . Note that in the configuration of the solid-state imaging device 10 of the first embodiment, a method of directly bonding the first semiconductor substrate 11 and the second semiconductor substrate 12 is desirable.
　なお、第２の半導体基板１２と支持基板１３とを接合する方法も第１の半導体基板１１と第２の半導体基板１２とを接合する方法と同様に考えられる。ただし、第２の半導体基板１２と支持基板１３とは電気的に接続しないため、樹脂接着剤などの絶縁部材で接合してもよい。 It should be noted that the method of bonding the second semiconductor substrate 12 and the support substrate 13 can be considered in the same manner as the method of bonding the first semiconductor substrate 11 and the second semiconductor substrate 12. However, since the second semiconductor substrate 12 and the support substrate 13 are not electrically connected, they may be joined by an insulating member such as a resin adhesive.
　なお、第１の実施形態では、第１の半導体基板１１と第２の半導体基板１２との２枚の半導体基板を積層した構成によって固体撮像装置１０の機能を実現する例を示しているが、固体撮像装置の機能を実現するために積層する半導体基板の枚数は２枚に限らず、さらに多くの枚数の半導体基板を積層する構成であってもよい。例えば、３枚の半導体基板を積層することによって固体撮像装置の機能を実現する構成である場合には、図１に示した第２の半導体基板１２における支持基板１３側の面に３枚目の半導体基板が接合され、さらに支持基板１３が接合される構成になる。つまり、第２の半導体基板１２と支持基板１３との間に３枚目以降の半導体基板が挟まれる構成になる。 In the first embodiment, an example in which the function of the solid-state imaging device 10 is realized by a configuration in which two semiconductor substrates of the first semiconductor substrate 11 and the second semiconductor substrate 12 are stacked is shown. The number of semiconductor substrates to be stacked in order to realize the function of the solid-state imaging device is not limited to two, and a configuration in which a larger number of semiconductor substrates are stacked may be employed. For example, when the structure of the solid-state imaging device is realized by stacking three semiconductor substrates, the third substrate is provided on the surface of the second semiconductor substrate 12 shown in FIG. The semiconductor substrate is bonded, and the support substrate 13 is further bonded. That is, the third and subsequent semiconductor substrates are sandwiched between the second semiconductor substrate 12 and the support substrate 13.
　次に、第１の実施形態の固体撮像装置１０を光が入射する側から見たときの構成について説明する。図２は、本発明の第１の実施形態の固体撮像装置１０を光が入射する側から見たときの概略構成を示した平面図である。 Next, a configuration when the solid-state imaging device 10 of the first embodiment is viewed from the light incident side will be described. FIG. 2 is a plan view showing a schematic configuration when the solid-state imaging device 10 according to the first embodiment of the present invention is viewed from the light incident side.
　第１の半導体基板１１の上面には、光電変換部を含む画素を二次元のマトリクス状に複数配置した画素アレイ部１１１と、画素アレイ部１１１内のそれぞれの画素が光電変換した電気信号を読み出すための水平駆動回路１１２と、固体撮像装置１０が外部との間で信号を入出力するための配線を接続するボンディングパッド１１３とが配置されている。 On the upper surface of the first semiconductor substrate 11, a pixel array unit 111 in which a plurality of pixels including a photoelectric conversion unit are arranged in a two-dimensional matrix, and an electric signal photoelectrically converted by each pixel in the pixel array unit 111 are read out. A horizontal drive circuit 112 for the above and a bonding pad 113 for connecting wiring for the solid-state imaging device 10 to input and output signals to and from the outside are arranged.
　ボンディングパッド１１３は、例えば、セラミックパッケージなどに固体撮像装置１０が組み付けられた（パッケージされた）場合に、パッケージの外部の回路と固体撮像装置１０との間で電気信号の入出力を行うための配線が接続される端子である。ボンディングパッド１１３とパッケージとは、ワイヤーボンディング法などを用いて形成した配線部によって電気的に接続される。固体撮像装置１０から出力する電気信号は、対応するボンディングパッド１１３および配線部を介して外部の回路に出力される。また、外部の回路から入力された電気信号は、対応する配線部およびボンディングパッド１１３を介して固体撮像装置１０内のそれぞれの構成要素に入力される。 For example, when the solid-state imaging device 10 is assembled (packaged) in a ceramic package or the like, the bonding pad 113 is used to input and output electrical signals between a circuit outside the package and the solid-state imaging device 10. A terminal to which wiring is connected. The bonding pad 113 and the package are electrically connected by a wiring part formed by using a wire bonding method or the like. The electrical signal output from the solid-state imaging device 10 is output to an external circuit via the corresponding bonding pad 113 and wiring portion. In addition, an electrical signal input from an external circuit is input to each component in the solid-state imaging device 10 via the corresponding wiring portion and the bonding pad 113.
　なお、図２に示した構成では、ボンディングパッド１１３は、第１の半導体基板１１内のそれぞれの構成要素と電気的に接続されるが、第２の半導体基板１２内のそれぞれの構成要素に接続される構成であってもよい。また、ボンディングパッド１１３は、第１の半導体基板１１に配置されるのみではなく、第２の半導体基板１２に配置されてもよい。 In the configuration shown in FIG. 2, the bonding pad 113 is electrically connected to each component in the first semiconductor substrate 11, but connected to each component in the second semiconductor substrate 12. It may be configured. Further, the bonding pad 113 may be disposed not only on the first semiconductor substrate 11 but also on the second semiconductor substrate 12.
　また、図２に示した構成では、水平駆動回路１１２が第１の半導体基板１１に配置されている場合を示しているが、水平駆動回路１１２を第２の半導体基板１２に配置する構成にしてもよい。また、水平駆動回路１１２を第１の半導体基板１１と第２の半導体基板１２の両方に分けて配置する構成にしてもよい。 In the configuration shown in FIG. 2, the horizontal drive circuit 112 is arranged on the first semiconductor substrate 11. However, the horizontal drive circuit 112 is arranged on the second semiconductor substrate 12. Also good. Further, the horizontal drive circuit 112 may be arranged separately on both the first semiconductor substrate 11 and the second semiconductor substrate 12.
　次に、第１の実施形態の固体撮像装置１０の構成についてより詳しく説明する。図３は、本発明の第１の実施形態の固体撮像装置１０における第１の半導体基板１１および第２の半導体基板１２の構成を示した図である。図３には、固体撮像装置１０を構成する第１の半導体基板１１内の構成要素と、第２の半導体基板１２内の構成要素との一例を示している。なお、図３においては、図２に示した第１の半導体基板１１に配置されるボンディングパッド１１３を省略している。 Next, the configuration of the solid-state imaging device 10 of the first embodiment will be described in more detail. FIG. 3 is a diagram illustrating the configuration of the first semiconductor substrate 11 and the second semiconductor substrate 12 in the solid-state imaging device 10 according to the first embodiment of the present invention. FIG. 3 shows an example of the components in the first semiconductor substrate 11 and the components in the second semiconductor substrate 12 constituting the solid-state imaging device 10. In FIG. 3, the bonding pads 113 arranged on the first semiconductor substrate 11 shown in FIG. 2 are omitted.
　第１の半導体基板１１は、入射された光を電気信号に変換して第２の半導体基板１２に出力する半導体基板である。第１の半導体基板１１には、画素アレイ部１１１と、水平駆動回路１１２とが配置されている。また、第２の半導体基板１２は、第１の半導体基板１１から出力された電気信号を処理して第１の半導体基板１１に出力する半導体基板である。第２の半導体基板１２には、垂直駆動回路１２１と、列処理回路１２２と、信号処理回路１２３と、第１の接続電極アレイ１２４と、第２の接続電極アレイ１２５とが配置されている。 The first semiconductor substrate 11 is a semiconductor substrate that converts incident light into an electrical signal and outputs it to the second semiconductor substrate 12. On the first semiconductor substrate 11, a pixel array unit 111 and a horizontal drive circuit 112 are arranged. The second semiconductor substrate 12 is a semiconductor substrate that processes the electrical signal output from the first semiconductor substrate 11 and outputs the processed electrical signal to the first semiconductor substrate 11. On the second semiconductor substrate 12, a vertical drive circuit 121, a column processing circuit 122, a signal processing circuit 123, a first connection electrode array 124, and a second connection electrode array 125 are arranged.
　画素アレイ部１１１は、入射された光を電気信号に変換する光電変換部と複数のトランジスタとから構成される画素が、二次元のマトリクス状に複数配置されている画素部である。画素アレイ部１１１は、第１の接続電極アレイ１２４を介して垂直駆動回路１２１から入力された駆動信号に応じて、入射してきた光を変換した電気信号を列処理回路１２２に出力する。 The pixel array unit 111 is a pixel unit in which a plurality of pixels each including a photoelectric conversion unit that converts incident light into an electrical signal and a plurality of transistors are arranged in a two-dimensional matrix. The pixel array unit 111 outputs an electric signal obtained by converting incident light to the column processing circuit 122 in accordance with the drive signal input from the vertical drive circuit 121 via the first connection electrode array 124.
　垂直駆動回路１２１は、画素アレイ部１１１内のそれぞれの画素を駆動し、各画素が入射した光を光電変換した電気信号（以下、「画素信号」という）を水平駆動回路１１２に出力させる。垂直駆動回路１２１は、画素アレイ部１１１内のそれぞれの画素を駆動するための駆動信号を生成する。そして、垂直駆動回路１２１は、生成した駆動信号を第１の接続電極アレイ１２４を介して画素アレイ部１１１に配置された画素の行毎に順次出力して、画素アレイ部１１１内のそれぞれの画素を行毎に駆動する。 The vertical drive circuit 121 drives each pixel in the pixel array unit 111 and causes the horizontal drive circuit 112 to output an electric signal (hereinafter referred to as “pixel signal”) obtained by photoelectrically converting light incident on each pixel. The vertical drive circuit 121 generates a drive signal for driving each pixel in the pixel array unit 111. Then, the vertical drive circuit 121 sequentially outputs the generated drive signal for each row of pixels arranged in the pixel array unit 111 via the first connection electrode array 124, so that each pixel in the pixel array unit 111 is output. Is driven row by row.
　水平駆動回路１１２は、垂直駆動回路１２１によって駆動された画素から出力された画素信号を行毎に読み出し、読み出した画素信号に応じた電気信号を、固体撮像装置１０が出力するそれぞれの画素の電気信号として、画素アレイ部１１１に配置された画素の列毎に順次出力する。このとき、水平駆動回路１１２は、列処理回路１２２および信号処理回路１２３によって予め定めた処理を施した後の電気信号を、固体撮像装置１０が出力するそれぞれの画素の電気信号として出力する。より具体的には、水平駆動回路１１２は、読み出した画素信号を第２の接続電極アレイ１２５を介して列処理回路１２２に出力し、第２の接続電極アレイ１２５を介して信号処理回路１２３から入力された電気信号を、固体撮像装置１０が出力するそれぞれの画素の電気信号として出力する。 The horizontal drive circuit 112 reads out pixel signals output from the pixels driven by the vertical drive circuit 121 for each row, and outputs electrical signals corresponding to the read pixel signals from the respective pixels output by the solid-state imaging device 10. A signal is sequentially output for each column of pixels arranged in the pixel array unit 111. At this time, the horizontal drive circuit 112 outputs the electrical signal after the predetermined processing is performed by the column processing circuit 122 and the signal processing circuit 123 as the electrical signal of each pixel output from the solid-state imaging device 10. More specifically, the horizontal driving circuit 112 outputs the read pixel signal to the column processing circuit 122 via the second connection electrode array 125, and from the signal processing circuit 123 via the second connection electrode array 125. The input electric signal is output as an electric signal of each pixel output from the solid-state imaging device 10.
　列処理回路１２２は、垂直駆動回路１２１によって行毎に読み出され、第２の接続電極アレイ１２５を介して水平駆動回路１１２から入力された画素信号に対して、画素アレイ部１１１に配置された画素の列毎に予め定めた処理（以下、「列処理」という）を施す。そして、列処理回路１２２は、列処理後の画素信号を、信号処理回路１２３に出力する。列処理回路１２２が画素信号に対して施す列処理としては、例えば、画素信号を増幅する増幅処理、画素信号に対してノイズ除去などの処理を行うＣＤＳ（Ｃｏｒｒｅｌａｔｅｄ　Ｄｏｕｂｌｅ　Ｓａｍｐｌｉｎｇ：相関二重サンプリング）処理、画素信号（アナログ信号）をアナログデジタル変換するアナログデジタル変換処理などのアナログ信号に対する処理がある。 The column processing circuit 122 is arranged in the pixel array unit 111 with respect to the pixel signal read out for each row by the vertical driving circuit 121 and input from the horizontal driving circuit 112 via the second connection electrode array 125. A predetermined process (hereinafter referred to as “column processing”) is performed for each column of pixels. Then, the column processing circuit 122 outputs the pixel signal after the column processing to the signal processing circuit 123. Examples of the column processing performed by the column processing circuit 122 on the pixel signal include, for example, CDS (Correlated Double Sampling) processing that performs amplification processing for amplifying the pixel signal and processing for removing noise from the pixel signal. There is a process for an analog signal such as an analog-to-digital conversion process for converting a pixel signal (analog signal) from analog to digital.
　信号処理回路１２３は、列処理回路１２２から入力された列処理後の画素信号に対して予め定めた信号処理を施す。そして、信号処理回路１２３は、信号処理を施した後の電気信号を、第２の接続電極アレイ１２５を介して水平駆動回路１１２に出力する。これにより、水平駆動回路１１２は、列処理回路１２２および信号処理回路１２３によって予め定めた処理が施された電気信号を、固体撮像装置１０が出力するそれぞれの画素の電気信号として列毎に順次出力することができる。信号処理回路１２３が列処理後の画素信号に対して施す信号処理としては、列処理後の画素信号を固体撮像装置１０の外部の回路に出力するための、例えば、ノイズ除去処理、歪補正処理、ＹＣ（輝度色）変換処理、リサイズ処理などのデジタル信号に対する処理がある。 The signal processing circuit 123 performs predetermined signal processing on the pixel signal after column processing input from the column processing circuit 122. Then, the signal processing circuit 123 outputs the electric signal after the signal processing to the horizontal drive circuit 112 via the second connection electrode array 125. As a result, the horizontal drive circuit 112 sequentially outputs, for each column, the electrical signal that has been subjected to predetermined processing by the column processing circuit 122 and the signal processing circuit 123 as the electrical signal of each pixel output from the solid-state imaging device 10. can do. The signal processing performed by the signal processing circuit 123 on the pixel signal after column processing is, for example, noise removal processing or distortion correction processing for outputting the pixel signal after column processing to a circuit outside the solid-state imaging device 10. , YC (luminance color) conversion processing, resizing processing, and the like.
　第１の接続電極アレイ１２４および第２の接続電極アレイ１２５は、第１の半導体基板１１内の構成要素と第２の半導体基板１２内の構成要素とを電気的に接続するための接続電極が、アレイ状に複数配置されている。より具体的には、固体撮像装置１０では、第１の接続電極アレイ１２４が、垂直駆動回路１２１内の構成要素と画素アレイ部１１１内の構成要素とをそれぞれ電気的に接続している。また、第２の接続電極アレイ１２５は、水平駆動回路１１２内の構成要素と、列処理回路１２２または信号処理回路１２３内の構成要素とをそれぞれ電気的に接続している。 The first connection electrode array 124 and the second connection electrode array 125 have connection electrodes for electrically connecting the components in the first semiconductor substrate 11 and the components in the second semiconductor substrate 12. A plurality of arrays are arranged. More specifically, in the solid-state imaging device 10, the first connection electrode array 124 electrically connects the components in the vertical drive circuit 121 and the components in the pixel array unit 111. The second connection electrode array 125 electrically connects the components in the horizontal drive circuit 112 and the components in the column processing circuit 122 or the signal processing circuit 123, respectively.
　接合した第１の半導体基板１１および第２の半導体基板１２に配置された構成要素同士は、第１の接続電極アレイ１２４または第２の接続電極アレイ１２５に配置された対応するそれぞれの接続電極部を介して、それぞれの電気信号の送受信を行う。接続電極部としては、例えば、蒸着法、めっき法で作製されるマイクロバンプの構造や、金属配線層によって接続する構造が用いられる。なお、接続電極部の構造として、例えば、シリコン貫通電極（ＴＳＶ：Ｔｈｒｏｕｇｈ－Ｓｉｌｉｃｏｎ－Ｖｉａ）の構造を用いてもよい。 The components disposed on the first semiconductor substrate 11 and the second semiconductor substrate 12 that are joined together are the corresponding connection electrode portions disposed on the first connection electrode array 124 or the second connection electrode array 125. Each electrical signal is transmitted and received via the. As the connection electrode part, for example, a structure of a micro bump manufactured by a vapor deposition method or a plating method or a structure connected by a metal wiring layer is used. As the structure of the connection electrode portion, for example, a structure of a through silicon via (TSV: Through-Silicon-Via) may be used.
　なお、図３に示した固体撮像装置１０の構成では、第１の接続電極アレイ１２４が垂直駆動回路１２１と並行に並んで配置され、第２の接続電極アレイ１２５が列処理回路１２２と並行に並んで配置されている構成を示している。しかし、第１の接続電極アレイ１２４および第２の接続電極アレイ１２５が配置される位置は、図３に示した位置に限定されることはない。例えば、第１の接続電極アレイ１２４が、垂直駆動回路１２１と並行な信号処理回路１２３の反対側の位置に配置されてもよく、第２の接続電極アレイ１２５が、列処理回路１２２と並行な信号処理回路１２３の反対側の位置に配置されてもよい。また、例えば、第１の接続電極アレイ１２４と第２の接続電極アレイ１２５とのそれぞれが複数の位置に分散して配置されてもよく、前述した位置の少なくとも一部に配置されてもよい。 In the configuration of the solid-state imaging device 10 shown in FIG. 3, the first connection electrode array 124 is arranged in parallel with the vertical drive circuit 121, and the second connection electrode array 125 is in parallel with the column processing circuit 122. A configuration arranged side by side is shown. However, the positions at which the first connection electrode array 124 and the second connection electrode array 125 are arranged are not limited to the positions shown in FIG. For example, the first connection electrode array 124 may be arranged at a position opposite to the signal processing circuit 123 parallel to the vertical drive circuit 121, and the second connection electrode array 125 is parallel to the column processing circuit 122. You may arrange | position in the position on the opposite side of the signal processing circuit 123. FIG. In addition, for example, each of the first connection electrode array 124 and the second connection electrode array 125 may be distributed in a plurality of positions, or may be disposed in at least a part of the positions described above.
　また、図３に示した固体撮像装置１０の構成では、水平駆動回路１１２が第１の半導体基板１１に配置され、垂直駆動回路１２１が第２の半導体基板１２に配置されている場合を示しているが、垂直駆動回路１２１を第１の半導体基板１１に配置し、水平駆動回路１１２を第２の半導体基板１２に配置する構成にしてもよい。また、水平駆動回路１１２および垂直駆動回路１２１を、第１の半導体基板１１と第２の半導体基板１２の両方に分けて配置する構成にしてもよい。 Further, in the configuration of the solid-state imaging device 10 shown in FIG. 3, a case where the horizontal drive circuit 112 is arranged on the first semiconductor substrate 11 and the vertical drive circuit 121 is arranged on the second semiconductor substrate 12 is shown. However, the vertical drive circuit 121 may be arranged on the first semiconductor substrate 11 and the horizontal drive circuit 112 may be arranged on the second semiconductor substrate 12. Further, the horizontal drive circuit 112 and the vertical drive circuit 121 may be arranged separately on both the first semiconductor substrate 11 and the second semiconductor substrate 12.
　次に、第１の実施形態の固体撮像装置１０の構造について説明する。図４は、本発明の第１の実施形態の固体撮像装置１０の構造を示した断面図である。図４には、図３に示した固体撮像装置１０の構成において、画素アレイ部１１１内の画素が形成された領域の構造の一部を示している。なお、上述したように、固体撮像装置１０は、第１の半導体基板１１と第２の半導体基板１２とが接合され、さらに、第２の半導体基板１２に支持基板１３が接合されているが、図４に示した固体撮像装置１０の構造では、それぞれの基板が接着層によって接合されている場合の一例を示している。 Next, the structure of the solid-state imaging device 10 of the first embodiment will be described. FIG. 4 is a cross-sectional view showing the structure of the solid-state imaging device 10 according to the first embodiment of the present invention. FIG. 4 shows a part of the structure of the region where the pixels in the pixel array unit 111 are formed in the configuration of the solid-state imaging device 10 shown in FIG. As described above, in the solid-state imaging device 10, the first semiconductor substrate 11 and the second semiconductor substrate 12 are bonded, and the support substrate 13 is bonded to the second semiconductor substrate 12. In the structure of the solid-state imaging device 10 illustrated in FIG. 4, an example in which each substrate is bonded by an adhesive layer is illustrated.
　第１の半導体基板１１は、マイクロレンズ１１１１と、カラーフィルター（色フィルター）１１１２と、透明樹脂層１１１３と、遮光膜１１１４と、反射防止膜１１１５と、第１の半導体層１１１６と、第１の配線層１１１８とで構成される。第１の半導体基板１１は、固体撮像装置１０において、主に入射された光線を電気信号に変換するための画素の回路要素が形成された、裏面照射型の固体撮像装置と同様の構成である。 The first semiconductor substrate 11 includes a micro lens 1111, a color filter 1112, a transparent resin layer 1113, a light shielding film 1114, an antireflection film 1115, a first semiconductor layer 1116, And a wiring layer 1118. The first semiconductor substrate 11 has the same configuration as that of the back-illuminated solid-state imaging device in which pixel circuit elements for mainly converting incident light rays into electrical signals are formed in the solid-state imaging device 10. .
　また、接着層１１３０によって第１の半導体基板１１と接合される第２の半導体基板１２は、第２の配線層１２０１と第２の半導体層１２０３とによって構成される。第２の半導体基板１２は、固体撮像装置１０において、主にデジタル信号に対する処理を行う構成要素（回路）の回路要素が形成される。 Further, the second semiconductor substrate 12 bonded to the first semiconductor substrate 11 by the adhesive layer 1130 is constituted by the second wiring layer 1201 and the second semiconductor layer 1203. In the solid-state imaging device 10, the second semiconductor substrate 12 is formed with circuit elements that are components (circuits) that mainly process digital signals.
　また、第２の半導体基板１２と支持基板１３とは、接着層１２３０によって接合される。支持基板１３は、第１の半導体基板１１と第２の半導体基板１２とを積層した後、エッチングなどによって積層したそれぞれの半導体基板を薄化する固体撮像装置１０の製造工程において、薄化した半導体基板が破壊されてしまわないように支持するための基板である。従って、支持基板１３には、固体撮像装置１０の機能を実現するための回路は形成されない。 Further, the second semiconductor substrate 12 and the support substrate 13 are bonded together by an adhesive layer 1230. The support substrate 13 is a thinned semiconductor in the manufacturing process of the solid-state imaging device 10 in which the first semiconductor substrate 11 and the second semiconductor substrate 12 are stacked and then the respective semiconductor substrates stacked by etching or the like are thinned. It is a board | substrate for supporting so that a board | substrate may not be destroyed. Therefore, a circuit for realizing the function of the solid-state imaging device 10 is not formed on the support substrate 13.
　マイクロレンズ１１１１は、固体撮像装置１０に入射された光（光線）を集光する。マイクロレンズ１１１１は、固体撮像装置１０に配置されたそれぞれの画素に対応する位置に形成される。そして、マイクロレンズ１１１１は、入射された光線を、例えば、第１の半導体層１１１６に集光する。 The micro lens 1111 condenses light (light rays) incident on the solid-state imaging device 10. The micro lens 1111 is formed at a position corresponding to each pixel disposed in the solid-state imaging device 10. Then, the micro lens 1111 condenses the incident light beam on the first semiconductor layer 1116, for example.
　カラーフィルター１１１２は、固体撮像装置１０に入射する光（光線）の分光透過特性を変えることによって、直下に形成されたそれぞれの画素毎に、異なる色の光線を入射させる。カラーフィルター１１１２は、マイクロレンズ１１１１および画素のそれぞれに対応する位置に形成される。なお、カラーフィルター１１１２は、必要に応じて設ける。例えば、固体撮像装置１０が、モノクロの画像を結像する固体撮像装置である場合には、カラーフィルター１１１２を設ける必要はない。 The color filter 1112 changes the spectral transmission characteristics of light (light rays) incident on the solid-state imaging device 10 so that light beams of different colors are incident on each pixel formed immediately below. The color filter 1112 is formed at a position corresponding to each of the microlens 1111 and the pixel. Note that the color filter 1112 is provided as necessary. For example, when the solid-state imaging device 10 is a solid-state imaging device that forms a monochrome image, the color filter 1112 need not be provided.
　透明樹脂層１１１３は、第１の半導体基板１１に光（光線）が入射する面を平坦化する層である。
　遮光膜１１１４は、隣接する画素同士の間を遮光する。遮光膜１１１４は、金属材料で構成され、例えば、タングステンまたはアルミを主材料とし、密着層としてチタンやその窒化物を用いた複数の層で形成される。 The transparent resin layer 1113 is a layer that flattens the surface on which light (light rays) is incident on the first semiconductor substrate 11.
The light shielding film 1114 shields light between adjacent pixels. The light shielding film 1114 is made of a metal material, and is formed of a plurality of layers using, for example, tungsten or aluminum as a main material and titanium or a nitride thereof as an adhesion layer.
　反射防止膜１１１５は、固体撮像装置１０に入射された光（光線）の反射を低減する膜である。反射防止膜１１１５は、高誘電体材料によって形成され、例えば、酸化タンタル、酸化ハフニウム、窒化ケイ素を用いた単一の層または複数の層で、第１の半導体層１１１６に接する面に形成される。このとき、反射防止膜１１１５は、入射された光線が予め定めた分光透過特性で第１の半導体層１１１６に入射されるように形成される。 The antireflection film 1115 is a film that reduces reflection of light (light rays) incident on the solid-state imaging device 10. The antireflection film 1115 is formed of a high dielectric material, for example, a single layer or a plurality of layers using tantalum oxide, hafnium oxide, or silicon nitride, and is formed on a surface in contact with the first semiconductor layer 1116. . At this time, the antireflection film 1115 is formed so that incident light rays are incident on the first semiconductor layer 1116 with a predetermined spectral transmission characteristic.
　第１の半導体層１１１６は、画素の回路要素を形成する半導体層である。図４に示した固体撮像装置１０の構成では、第１の半導体層１１１６内に、画素を構成し、反射防止膜１１１５に接する面から入射された光（光線）を電気信号に変換する光電変換部１１１７が形成されている場合を示している。この第１の半導体層１１１６内に形成された光電変換部１１１７によって、入射された光線が電気信号（画素信号）に変換される。 The first semiconductor layer 1116 is a semiconductor layer that forms a circuit element of a pixel. In the configuration of the solid-state imaging device 10 illustrated in FIG. 4, photoelectric conversion is performed in which a pixel is formed in the first semiconductor layer 1116 and light (light rays) incident from a surface in contact with the antireflection film 1115 is converted into an electrical signal. The case where the part 1117 is formed is shown. The incident light beam is converted into an electric signal (pixel signal) by the photoelectric conversion unit 1117 formed in the first semiconductor layer 1116.
　第１の配線層１１１８は、画素の回路要素同士、または第１の半導体基板１１内に配置されるそれぞれの構成要素同士を接続する金属配線が形成される層である。図４に示した固体撮像装置１０の構成では、第１の配線層１１１８内に、金属配線１１１９が形成されている場合を示している。この第１の配線層１１１８内に形成されたそれぞれの金属配線１１１９によって、第１の半導体基板１１に配置されたそれぞれの構成要素を構成するそれぞれの回路要素同士が接続される。 The first wiring layer 1118 is a layer in which metal wiring for connecting pixel circuit elements or respective components arranged in the first semiconductor substrate 11 is formed. In the configuration of the solid-state imaging device 10 illustrated in FIG. 4, a case where the metal wiring 1119 is formed in the first wiring layer 1118 is illustrated. The respective circuit elements constituting the respective constituent elements arranged on the first semiconductor substrate 11 are connected by the respective metal wirings 1119 formed in the first wiring layer 1118.
　接着層１１３０は、第１の半導体基板１１と第２の半導体基板１２とを接合するための層である。接着層１１３０は、例えば、シリコン酸化膜やシリコン窒化膜などによって構成される。 The adhesive layer 1130 is a layer for bonding the first semiconductor substrate 11 and the second semiconductor substrate 12. The adhesive layer 1130 is made of, for example, a silicon oxide film or a silicon nitride film.
　第２の配線層１２０１は、第２の半導体基板１２内に配置されるそれぞれの構成要素同士を接続する金属配線が形成される層である。図４に示した固体撮像装置１０の構成では、第２の配線層１２０１内に、金属配線１２０２が形成されている場合を示している。この第２の配線層１２０１内に形成されたそれぞれの金属配線１２０２によって、第２の半導体基板１２に配置されたそれぞれの構成要素を構成するそれぞれの回路要素同士が接続される。 The second wiring layer 1201 is a layer in which metal wiring for connecting the respective constituent elements arranged in the second semiconductor substrate 12 is formed. In the configuration of the solid-state imaging device 10 illustrated in FIG. 4, a case where the metal wiring 1202 is formed in the second wiring layer 1201 is illustrated. The respective circuit elements constituting the respective constituent elements arranged on the second semiconductor substrate 12 are connected by the respective metal wirings 1202 formed in the second wiring layer 1201.
　第２の半導体層１２０３は、第２の半導体基板１２内に配置されるそれぞれの構成要素を構成するそれぞれの回路要素を形成する半導体層である。第２の半導体層１２０３には、固体撮像装置１０においてデジタル信号に対する処理を行う回路を構成するための複数のトランジスタが形成される。 The second semiconductor layer 1203 is a semiconductor layer forming each circuit element constituting each component arranged in the second semiconductor substrate 12. In the second semiconductor layer 1203, a plurality of transistors for forming a circuit for processing digital signals in the solid-state imaging device 10 are formed.
　固体撮像装置１０においては、第１の半導体基板１１に形成された回路要素の信号線と、第２の半導体基板１２に形成された回路要素の信号線とが、シリコン貫通電極１２０４と裏面電極１２０５とによって構成された接続電極によって電気的に接続される。接続電極は、第２の半導体層１２０３を貫通して第２の配線層１２０１内の金属配線と接続されたシリコン貫通電極１２０４と、第２の半導体層１２０３、第２の配線層１２０１、および接着層１１３０を貫通して第１の配線層１１１８内の金属配線と接続されたシリコン貫通電極１２０４とが組になり、このシリコン貫通電極１２０４の組が裏面電極１２０５によって接続されることによって構成される。図４に示した固体撮像装置１０の構成では、第２の半導体層１２０３を貫通して第２の配線層１２０１内の金属配線１２０２と接続されたシリコン貫通電極１２０４と、第２の半導体層１２０３、第２の配線層１２０１、および接着層１１３０を貫通して第１の配線層１１１８内の金属配線１１１９と接続されたシリコン貫通電極１２０４との組が、裏面電極１２０５によって接続されて接続電極を構成している場合を示している。この接続電極によって、第１の半導体基板１１と第２の半導体基板１２とが電気的に接続される。 In the solid-state imaging device 10, the signal line of the circuit element formed on the first semiconductor substrate 11 and the signal line of the circuit element formed on the second semiconductor substrate 12 are the silicon through electrode 1204 and the back electrode 1205. Are electrically connected by a connection electrode constituted by The connection electrode includes a silicon through electrode 1204 that passes through the second semiconductor layer 1203 and is connected to the metal wiring in the second wiring layer 1201, the second semiconductor layer 1203, the second wiring layer 1201, and an adhesive. The silicon through electrode 1204 penetrating the layer 1130 and connected to the metal wiring in the first wiring layer 1118 forms a set, and the set of the silicon through electrode 1204 is connected by the back electrode 1205. . In the configuration of the solid-state imaging device 10 illustrated in FIG. 4, the silicon through electrode 1204 that penetrates through the second semiconductor layer 1203 and is connected to the metal wiring 1202 in the second wiring layer 1201, and the second semiconductor layer 1203. A pair of the silicon through electrode 1204 connected to the metal wiring 1119 in the first wiring layer 1118 through the second wiring layer 1201 and the adhesive layer 1130 is connected by the back electrode 1205 to connect the connection electrode. The case where it comprises is shown. By this connection electrode, the first semiconductor substrate 11 and the second semiconductor substrate 12 are electrically connected.
　なお、シリコン貫通電極１２０４および裏面電極１２０５の材料は、第１の配線層１１１８または第２の配線層１２０１において、第１の半導体基板１１内に形成された回路要素同士、または第２の半導体基板１２内に形成された回路要素同士を接続するために形成される金属配線と同じ材料を用いてもよいし、異なる材料を用いてもよい。例えば、シリコン貫通電極１２０４および裏面電極１２０５の材料として、金属配線として一般的に使用されるアルミや銅であってもよいし、トランジスタのゲート端子として使用されるポリシリコンなどの金属配線（アルミ）と異なる材料であってもよい。このように、第１の半導体基板１１および第２の半導体基板１２を製造する際に使用する材料を、シリコン貫通電極１２０４および裏面電極１２０５の材料として使用することにより、半導体の製造プロセスに、シリコン貫通電極１２０４および裏面電極１２０５を形成する工程を容易に組み込むことができる。 Note that the material of the through silicon via 1204 and the back electrode 1205 is the circuit elements formed in the first semiconductor substrate 11 in the first wiring layer 1118 or the second wiring layer 1201, or the second semiconductor substrate. The same material as the metal wiring formed for connecting the circuit elements formed in 12 may be used, or a different material may be used. For example, the material of the silicon through electrode 1204 and the back electrode 1205 may be aluminum or copper generally used as metal wiring, or metal wiring (aluminum) such as polysilicon used as a gate terminal of a transistor. Different materials may be used. Thus, by using the material used when manufacturing the first semiconductor substrate 11 and the second semiconductor substrate 12 as the material of the silicon through electrode 1204 and the back electrode 1205, silicon can be used in the semiconductor manufacturing process. A process of forming the through electrode 1204 and the back electrode 1205 can be easily incorporated.
　接着層１２３０は、第２の半導体基板１２と支持基板１３とを接合するための層である。接着層１２３０は、第２の半導体基板１２と支持基板１３とを、直接または樹脂によって接合する。接着層１２３０は、例えば、シリコン酸化膜やシリコン窒化膜などの保護膜、ポリィミド樹脂などの樹脂膜によって構成される。 The adhesive layer 1230 is a layer for joining the second semiconductor substrate 12 and the support substrate 13 together. The adhesive layer 1230 joins the second semiconductor substrate 12 and the support substrate 13 directly or by resin. The adhesive layer 1230 is made of, for example, a protective film such as a silicon oxide film or a silicon nitride film, or a resin film such as polyimide resin.
　支持基板１３は、接合された第１の半導体基板１１と第２の半導体基板１２とを支持することによって、積層されて薄化された第１の半導体基板１１と第２の半導体基板１２との物理的強度（機械的強度）を維持するための基板である。支持基板１３としては、例えば、第１の半導体基板１１および第２の半導体基板１２と同じ材料のシリコン基板が用いられる。なお、上述したように、支持基板１３には、固体撮像装置１０の機能を実現するための回路は形成されない。このため、支持基板１３は、シリコン基板と異なる材料であってもよい。 The support substrate 13 supports the first semiconductor substrate 11 and the second semiconductor substrate 12 that are bonded together, so that the first semiconductor substrate 11 and the second semiconductor substrate 12 that are stacked and thinned are supported. This is a substrate for maintaining physical strength (mechanical strength). As the support substrate 13, for example, a silicon substrate made of the same material as the first semiconductor substrate 11 and the second semiconductor substrate 12 is used. Note that, as described above, a circuit for realizing the function of the solid-state imaging device 10 is not formed on the support substrate 13. For this reason, the support substrate 13 may be made of a material different from that of the silicon substrate.
　ここで、固体撮像装置１０を製造する製造工程の概略について説明する。固体撮像装置１０は、以下のような順番でそれぞれの工程を進めることによって、最終的な構造とする。 Here, an outline of a manufacturing process for manufacturing the solid-state imaging device 10 will be described. The solid-state imaging device 10 has a final structure by proceeding with the respective steps in the following order.
　（工程１）
　第１の半導体基板１１に第１の半導体層１１１６と第１の配線層１１１８とのそれぞれを形成する。また、第２の半導体基板１２に第２の半導体層１２０３と第２の配線層１２０１とのそれぞれを形成する。なお、この工程１においては、第１の半導体基板１１に、マイクロレンズ１１１１と、カラーフィルター１１１２と、透明樹脂層１１１３と、遮光膜１１１４と、反射防止膜１１１５とは形成しない。 (Process 1)
Each of the first semiconductor layer 1116 and the first wiring layer 1118 is formed on the first semiconductor substrate 11. In addition, the second semiconductor layer 1203 and the second wiring layer 1201 are formed on the second semiconductor substrate 12. In this step 1, the microlens 1111, the color filter 1112, the transparent resin layer 1113, the light shielding film 1114, and the antireflection film 1115 are not formed on the first semiconductor substrate 11.
　（工程２）
　工程１において形成した第１の半導体基板１１と第２の半導体基板１２とを積層する。このとき、図４に示したように、第１の半導体基板１１の第１の配線層１１１８側の面と、第２の半導体基板１２の第２の配線層１２０１側の面とを対向させ、接着層１１３０によって接合する。 (Process 2)
The first semiconductor substrate 11 and the second semiconductor substrate 12 formed in step 1 are stacked. At this time, as shown in FIG. 4, the surface of the first semiconductor substrate 11 on the first wiring layer 1118 side and the surface of the second semiconductor substrate 12 on the second wiring layer 1201 side are opposed to each other, Bonding is performed using an adhesive layer 1130.
　（工程３）
　第１の半導体基板１１と第２の半導体基板１２とを接合した状態で、第２の半導体基板１２の第２の半導体層１２０３側の面のシリコン層をエッチングし、第２の半導体基板１２を薄化する。このとき、第１の半導体基板１１は、薄化した第２の半導体基板１２を支持する支持基板の役目を担っている。 (Process 3)
In a state where the first semiconductor substrate 11 and the second semiconductor substrate 12 are bonded, the silicon layer on the surface of the second semiconductor substrate 12 on the second semiconductor layer 1203 side is etched, and the second semiconductor substrate 12 is removed. Thin out. At this time, the first semiconductor substrate 11 serves as a support substrate that supports the thinned second semiconductor substrate 12.
　（工程４）
　第２の半導体基板１２の第２の半導体層１２０３側の面からシリコン貫通電極１２０４と裏面電極１２０５とによって構成される接続電極を形成する。これにより、第１の半導体基板１１に形成された回路要素の信号線と、第２の半導体基板１２に形成された回路要素の信号線とが電気的に接続される。 (Process 4)
A connection electrode constituted by the through silicon via 1204 and the back electrode 1205 is formed from the surface of the second semiconductor substrate 12 on the second semiconductor layer 1203 side. As a result, the signal line of the circuit element formed on the first semiconductor substrate 11 and the signal line of the circuit element formed on the second semiconductor substrate 12 are electrically connected.
　（工程５）
　第２の半導体基板１２の接続電極が形成された側の面に、支持基板１３を積層する。 (Process 5)
A support substrate 13 is laminated on the surface of the second semiconductor substrate 12 on which the connection electrodes are formed.
　（工程６）
　第１の半導体基板１１および第２の半導体基板１２と、支持基板１３とを接合した状態で、第１の半導体基板１１の第１の半導体層１１１６側の面のシリコン層、すなわち、光（光線）が入射する側のシリコン層をエッチングし、第１の半導体基板１１を薄化する。 (Step 6)
In a state where the first semiconductor substrate 11 and the second semiconductor substrate 12 are bonded to the support substrate 13, the silicon layer on the surface of the first semiconductor substrate 11 on the first semiconductor layer 1116 side, that is, light (light beam). The first semiconductor substrate 11 is thinned by etching the silicon layer on the side where the first semiconductor substrate 11 is incident.
　（工程７）
　第１の半導体基板１１の第１の半導体層１１１６側の面に、反射防止膜１１１５、遮光膜１１１４、透明樹脂層１１１３、カラーフィルター１１１２、およびマイクロレンズ１１１１を順次形成する。 (Step 7)
An antireflection film 1115, a light shielding film 1114, a transparent resin layer 1113, a color filter 1112, and a microlens 1111 are sequentially formed on the surface of the first semiconductor substrate 11 on the first semiconductor layer 1116 side.
　第１の実施形態によれば、入射された光線を電気信号（画素信号）に変換して出力する光電変換部（光電変換部１１１７）を具備した画素が二次元のマトリクス状に複数配置された画素部（画素アレイ部１１１）の回路要素が形成された第１の半導体層（第１の半導体層１１１６）を有する第１の半導体基板（第１の半導体基板１１）と、光電変換部１１１７が出力した電気信号に対して処理を行う処理部（垂直駆動回路１２１、列処理回路１２２、信号処理回路１２３など）の回路要素が形成された第２の半導体層（第２の半導体層１２０３）を有する第２の半導体基板（第２の半導体基板１２）と、第１の半導体基板１１と第２の半導体基板１２とを積層した状態で、第１の半導体層１１１６に形成された回路要素の信号線と、第２の半導体基板１２に形成された回路要素の信号線とを電気的に接続する接続電極（シリコン貫通電極１２０４および裏面電極１２０５）と、を備え、接続電極は、第２の半導体基板１２内の第２の半導体層１２０３を貫通する貫通電極（シリコン貫通電極１２０４）、を備える固体撮像装置（固体撮像装置１０）が構成される。 According to the first embodiment, a plurality of pixels each having a photoelectric conversion unit (photoelectric conversion unit 1117) that converts incident light into an electric signal (pixel signal) and outputs the electric signal (pixel signal) are arranged in a two-dimensional matrix. A first semiconductor substrate (first semiconductor substrate 11) having a first semiconductor layer (first semiconductor layer 1116) on which circuit elements of the pixel portion (pixel array portion 111) are formed, and a photoelectric conversion portion 1117; A second semiconductor layer (second semiconductor layer 1203) on which circuit elements of a processing unit (such as a vertical drive circuit 121, a column processing circuit 122, and a signal processing circuit 123) that processes the output electric signal is formed. A signal of a circuit element formed in the first semiconductor layer 1116 in a state where the second semiconductor substrate (second semiconductor substrate 12), the first semiconductor substrate 11, and the second semiconductor substrate 12 are stacked. The line and the second A connection electrode (through silicon electrode 1204 and back electrode 1205) for electrically connecting signal lines of circuit elements formed on the conductor substrate 12, and the connection electrode is a second electrode in the second semiconductor substrate 12. A solid-state imaging device (solid-state imaging device 10) including a through-electrode (silicon through electrode 1204) that penetrates the semiconductor layer 1203 is configured.
　また、第１の実施形態によれば、接続電極（シリコン貫通電極１２０４および裏面電極１２０５）は、画素アレイ部１１１に光線が入射する側とは反対側で、画素アレイ部１１１の領域に重なるように配置される固体撮像装置１０が構成される。 In addition, according to the first embodiment, the connection electrodes (the silicon through electrode 1204 and the back electrode 1205) overlap the region of the pixel array unit 111 on the side opposite to the side where the light beam enters the pixel array unit 111. The solid-state imaging device 10 arranged in the above is configured.
　また、第１の実施形態によれば、第１の半導体基板１１と第２の半導体基板１２とが積層された状態を支持する支持基板（支持基板１３）、をさらに備え、支持基板１３は、第１の半導体基板１１および第２の半導体基板１２と同じ材料である固体撮像装置１０が構成される。 In addition, according to the first embodiment, the semiconductor device further includes a support substrate (support substrate 13) that supports a state in which the first semiconductor substrate 11 and the second semiconductor substrate 12 are stacked. A solid-state imaging device 10 made of the same material as the first semiconductor substrate 11 and the second semiconductor substrate 12 is configured.
　また、第１の実施形態によれば、接続電極（シリコン貫通電極１２０４および裏面電極１２０５）は、第１の半導体基板１１内に形成された回路要素同士の信号線、または第２の半導体基板１２内に形成された回路要素同士の信号線を接続するために形成される金属配線（金属配線１１１９または金属配線１２０２）と異なる材料によって形成される固体撮像装置１０が構成される。 In addition, according to the first embodiment, the connection electrodes (the silicon through electrode 1204 and the back electrode 1205) are signal lines between circuit elements formed in the first semiconductor substrate 11 or the second semiconductor substrate 12. The solid-state imaging device 10 formed of a material different from a metal wiring (metal wiring 1119 or metal wiring 1202) formed to connect signal lines between circuit elements formed therein is configured.
　また、第１の実施形態によれば、接続電極（シリコン貫通電極１２０４および裏面電極１２０５）は、第１の半導体基板１１内に形成された回路要素同士の信号線、または第２の半導体基板１２内に形成された回路要素同士の信号線を接続するために形成される金属配線（金属配線１１１９または金属配線１２０２）と同じ材料によって形成される固体撮像装置１０が構成される。 In addition, according to the first embodiment, the connection electrodes (the silicon through electrode 1204 and the back electrode 1205) are signal lines between circuit elements formed in the first semiconductor substrate 11 or the second semiconductor substrate 12. The solid-state imaging device 10 formed of the same material as the metal wiring (metal wiring 1119 or metal wiring 1202) formed to connect the signal lines of the circuit elements formed inside is configured.
　上記に述べたように、第１の実施形態の固体撮像装置１０では、第２の半導体基板１２の第２の半導体層１２０３側の面からシリコン貫通電極１２０４と裏面電極１２０５とによって構成される接続電極を形成する。つまり、第１の実施形態の固体撮像装置１０では、従来の固体撮像装置のように、光（光線）が入射する側の面からシリコン貫通電極を形成するのではなく、光（光線）が入射する側と反対側の面からシリコン貫通電極１２０４および裏面電極１２０５を形成して第１の半導体基板１１に形成された回路要素の信号線と、第２の半導体基板１２に形成された回路要素の信号線とを電気的に接続する。これにより、第１の実施形態の固体撮像装置１０では、形成された画素に光（光線）が入射する側と反対側で画素に重なる領域、すなわち、画素の領域の直下の領域でも、第１の半導体基板１１と第２の半導体基板１２とに形成されたそれぞれの構成要素同士を接続することができる。つまり、従来の固体撮像装置では、画素アレイ部を避けた周辺部分の領域に設けられた半導体除去領域内に接続配線を設ける必要があったが、第１の実施形態の固体撮像装置１０では、画素アレイ部１１１が形成された領域の直下の領域において、画素に入射する光（光線）を遮ることなく、接続電極を形成することができる。このことにより、第１の実施形態の固体撮像装置１０では、第１の半導体基板１１と第２の半導体基板１２とを積層することによって、固体撮像装置１０の性能や機能を向上させることができると共に、それぞれの半導体基板を接続するために形成する配線の自由度を向上させ、小型化を実現することができる。 As described above, in the solid-state imaging device 10 of the first embodiment, the connection constituted by the through silicon via 1204 and the back electrode 1205 from the surface of the second semiconductor substrate 12 on the second semiconductor layer 1203 side. An electrode is formed. That is, in the solid-state imaging device 10 according to the first embodiment, unlike the conventional solid-state imaging device, the light (light ray) is incident instead of forming the through silicon via from the surface on which light (light ray) is incident. A through-silicon electrode 1204 and a back electrode 1205 are formed from the surface opposite to the side to be processed, and signal lines of circuit elements formed on the first semiconductor substrate 11 and circuit elements formed on the second semiconductor substrate 12 Electrically connect to the signal line. Thereby, in the solid-state imaging device 10 according to the first embodiment, even in the region overlapping the pixel on the side opposite to the side on which the light (light ray) is incident on the formed pixel, that is, the region immediately below the pixel region, The respective components formed on the semiconductor substrate 11 and the second semiconductor substrate 12 can be connected to each other. That is, in the conventional solid-state imaging device, it is necessary to provide the connection wiring in the semiconductor removal region provided in the peripheral portion area avoiding the pixel array portion, but in the solid-state imaging device 10 of the first embodiment, In the region immediately below the region where the pixel array unit 111 is formed, the connection electrode can be formed without blocking light (light rays) incident on the pixel. Thus, in the solid-state imaging device 10 of the first embodiment, the performance and function of the solid-state imaging device 10 can be improved by stacking the first semiconductor substrate 11 and the second semiconductor substrate 12. At the same time, it is possible to improve the degree of freedom of wiring formed for connecting the respective semiconductor substrates, and to realize miniaturization.
　また、第１の実施形態の固体撮像装置１０では、画素アレイ部１１１が形成された領域の直下の領域であっても接続電極を形成することができるため、第１の半導体基板１１と第２の半導体基板１２とに形成されたそれぞれの構成要素同士を接続する配線の長さを短くすることができる。つまり、従来の固体撮像装置においては、それぞれの構成要素が配置された位置によっては、画素アレイ部の領域を迂回するように配線を設ける必要があるため配線の長さが長くなることもあるが、第１の実施形態の固体撮像装置１０では、画素アレイ部の領域を迂回せずにより短い長さの配線を形成することができる。これにより、第１の実施形態の固体撮像装置１０では、配線の長さに応じて大きくなる、第１の半導体基板１１と第２の半導体基板１２との間でやり取りされる信号線の遅延を少なくすることができ、固体撮像装置１０の性能や機能をさらに向上することができる。 In the solid-state imaging device 10 according to the first embodiment, since the connection electrode can be formed even in the region immediately below the region where the pixel array unit 111 is formed, the first semiconductor substrate 11 and the second semiconductor substrate 11 can be formed. It is possible to reduce the length of the wiring connecting the respective components formed on the semiconductor substrate 12. In other words, in the conventional solid-state imaging device, depending on the position where each component is arranged, it is necessary to provide wiring so as to bypass the region of the pixel array portion. In the solid-state imaging device 10 of the first embodiment, it is possible to form a wiring having a shorter length without bypassing the region of the pixel array unit. Thereby, in the solid-state imaging device 10 according to the first embodiment, the delay of the signal line exchanged between the first semiconductor substrate 11 and the second semiconductor substrate 12 increases according to the length of the wiring. Therefore, the performance and function of the solid-state imaging device 10 can be further improved.
　なお、第１の実施形態の固体撮像装置１０では、支持基板１３として、第１の半導体基板１１および第２の半導体基板１２と同様のシリコン基板を用いた場合を示したが、上述したように、支持基板１３には、固体撮像装置１０の機能を実現するための回路は形成されない。つまり、積層されて薄化された第１の半導体基板１１と第２の半導体基板１２とを支持して機械的強度を維持する基板であれば、例えば、ガラス基板や樹脂基板など、いかなる材料の基板であってもよい。 In the solid-state imaging device 10 according to the first embodiment, the case where the silicon substrate similar to the first semiconductor substrate 11 and the second semiconductor substrate 12 is used as the support substrate 13 has been described, but as described above. A circuit for realizing the function of the solid-state imaging device 10 is not formed on the support substrate 13. That is, any material such as a glass substrate or a resin substrate can be used as long as it supports the first semiconductor substrate 11 and the second semiconductor substrate 12 that are stacked and thinned to maintain the mechanical strength. It may be a substrate.
（第２の実施形態）
　次に、固体撮像装置において第１の半導体基板１１と第２の半導体基板１２とを支持する支持基板が、第１の半導体基板１１および第２の半導体基板１２と異なる材料である場合の構成の一例について説明する。図５は、本発明の第２の実施形態の固体撮像装置の構造を示した断面図である。以下の説明においては、第２の実施形態の固体撮像装置（以下、「固体撮像装置２０」という）において、積層されて薄化された第１の半導体基板１１と第２の半導体基板１２とを支持する支持基板として、ガラス基板を用いた場合について説明する。なお、第２の実施形態の固体撮像装置２０における第１の半導体基板１１と第２の半導体基板１２との構成は、図１～図４に示した第１の実施形態の固体撮像装置１０と同様の構成である。従って、以下の説明においては、第２の実施形態の固体撮像装置２０のそれぞれの構成要素について、第１の実施形態の固体撮像装置１０と同一の符号を用いて説明し、第２の実施形態の固体撮像装置２０の構成やそれぞれの構成要素に関する詳細な説明は省略する。 (Second Embodiment)
Next, the configuration in the case where the support substrate that supports the first semiconductor substrate 11 and the second semiconductor substrate 12 in the solid-state imaging device is made of a material different from that of the first semiconductor substrate 11 and the second semiconductor substrate 12 is described. An example will be described. FIG. 5 is a cross-sectional view showing the structure of the solid-state imaging device according to the second embodiment of the present invention. In the following description, in the solid-state imaging device of the second embodiment (hereinafter referred to as “solid-state imaging device 20”), the first semiconductor substrate 11 and the second semiconductor substrate 12 that are stacked and thinned are used. The case where a glass substrate is used as the supporting substrate to be supported will be described. Note that the configuration of the first semiconductor substrate 11 and the second semiconductor substrate 12 in the solid-state imaging device 20 of the second embodiment is the same as that of the solid-state imaging device 10 of the first embodiment shown in FIGS. It is the same composition. Therefore, in the following description, each component of the solid-state imaging device 20 of the second embodiment will be described using the same reference numerals as those of the solid-state imaging device 10 of the first embodiment, and the second embodiment will be described. A detailed description of the configuration of the solid-state imaging device 20 and the respective components will be omitted.
　図５には、図３に示した固体撮像装置１０同様に、第１の半導体基板１１と第２の半導体基板１２とが積層された構成の固体撮像装置２０において、画素アレイ部１１１内の画素が形成された領域の構造の一部を示している。なお、固体撮像装置２０においても、固体撮像装置１０と同様に、第１の半導体基板１１と第２の半導体基板１２とが接合されるが、図５に示した固体撮像装置２０の構造では、それぞれの半導体基板が直接接合されている場合の一例を示している。 FIG. 5 shows the pixels in the pixel array unit 111 in the solid-state imaging device 20 having a configuration in which the first semiconductor substrate 11 and the second semiconductor substrate 12 are stacked, like the solid-state imaging device 10 shown in FIG. A part of the structure of the region where is formed is shown. In the solid-state imaging device 20 as well, the first semiconductor substrate 11 and the second semiconductor substrate 12 are bonded as in the solid-state imaging device 10. However, in the structure of the solid-state imaging device 20 shown in FIG. An example in which each semiconductor substrate is directly bonded is shown.
　固体撮像装置２０においては、第１の半導体基板１１と第２の半導体基板１２とが接合され、さらに、支持基板として、第１の半導体基板１１にガラス基板１４が接合されている。ガラス基板１４は、光を透過する基板であり、第１の半導体基板１１の第１の半導体層１１１６側の面、すなわち、第１の半導体基板１１にマイクロレンズ１１１１が形成された光（光線）が入射する側の面に接合される。第１の半導体基板１１とガラス基板１４とは、例えば、透明な樹脂接着剤などによって接合される。固体撮像装置２０では、ガラス基板１４によって、薄化された第１の半導体基板１１と第２の半導体基板１２との機械的強度を維持している。 In the solid-state imaging device 20, the first semiconductor substrate 11 and the second semiconductor substrate 12 are bonded, and further, the glass substrate 14 is bonded to the first semiconductor substrate 11 as a support substrate. The glass substrate 14 is a substrate that transmits light. The surface of the first semiconductor substrate 11 on the first semiconductor layer 1116 side, that is, the light (light beam) on which the microlenses 1111 are formed on the first semiconductor substrate 11. Is bonded to the surface on the side where the light enters. The first semiconductor substrate 11 and the glass substrate 14 are bonded by, for example, a transparent resin adhesive. In the solid-state imaging device 20, the mechanical strength of the thinned first semiconductor substrate 11 and second semiconductor substrate 12 is maintained by the glass substrate 14.
　また、図５に示した固体撮像装置２０の構造では、第２の半導体基板１２の第２の半導体層１２０３側の面、すなわち、固体撮像装置２０に光（光線）が入射する側と反対側の面に、保護膜１５３０と突起電極１５０１とが形成されている。 In the structure of the solid-state imaging device 20 shown in FIG. 5, the surface of the second semiconductor substrate 12 on the second semiconductor layer 1203 side, that is, the side opposite to the side on which light (light rays) enters the solid-state imaging device 20. A protective film 1530 and a protruding electrode 1501 are formed on the surface.
　保護膜１５３０は、第１の半導体基板１１と第２の半導体基板１２とを電気的に接続するために形成された接続電極を保護するための膜である。より具体的には、保護膜１５３０は、第２の半導体層１２０３を貫通して第２の配線層１２０１内の金属配線１２０２と接続されたシリコン貫通電極１２０４と、第２の半導体層１２０３および第２の配線層１２０１を貫通して第１の配線層１１１８内の金属配線１１１９と接続されたシリコン貫通電極１２０４と、それぞれのシリコン貫通電極１２０４を接続する裏面電極１２０５とによって構成された接続電極を保護する。保護膜１５３０は、例えば、シリコン酸化膜、シリコン窒化膜などの保護膜である。また、保護膜１５３０は、例えば、ポリィミド樹脂などの樹脂膜であってもよい。 The protective film 1530 is a film for protecting the connection electrode formed to electrically connect the first semiconductor substrate 11 and the second semiconductor substrate 12. More specifically, the protective film 1530 includes the silicon through electrode 1204 that penetrates the second semiconductor layer 1203 and is connected to the metal wiring 1202 in the second wiring layer 1201, the second semiconductor layer 1203, and the second semiconductor layer 1203. A connection electrode constituted by a silicon through electrode 1204 that penetrates through the two wiring layers 1201 and is connected to the metal wiring 1119 in the first wiring layer 1118 and a back electrode 1205 that connects each silicon through electrode 1204. Protect. The protective film 1530 is, for example, a protective film such as a silicon oxide film or a silicon nitride film. Further, the protective film 1530 may be a resin film such as a polyimide resin, for example.
　また、保護膜１５３０には、固体撮像装置２０が外部の回路との間で電気信号の入出力を行うための裏面電極１２０５の位置に凹形状の開口部が設けられている。この開口部には、裏面電極１２０５と接続された突起電極１５０１が形成されている。 Further, the protective film 1530 is provided with a concave opening at the position of the back electrode 1205 for the solid-state imaging device 20 to input / output an electric signal to / from an external circuit. A protruding electrode 1501 connected to the back electrode 1205 is formed in the opening.
　突起電極１５０１は、固体撮像装置２０が外部との間で信号を入出力するための端子である。固体撮像装置２０では、第１の実施形態の固体撮像装置１０と異なり、この突起電極１５０１を介して外部の回路との間で電気信号のやり取りを行う。突起電極１５０１は、例えば、半田、金、銅、錫などの金属材料で形成される。 The protruding electrode 1501 is a terminal for the solid-state imaging device 20 to input and output signals with the outside. Unlike the solid-state imaging device 10 of the first embodiment, the solid-state imaging device 20 exchanges electric signals with an external circuit via the protruding electrodes 1501. The protruding electrode 1501 is formed of a metal material such as solder, gold, copper, or tin, for example.
　固体撮像装置２０は、突起電極１５０１の構成によって、例えば、電子部品を実装する実装基板にフリップチップ実装をすることができる構成である。そして、固体撮像装置２０から出力する電気信号は、対応する裏面電極１２０５および突起電極１５０１を介して外部の回路に出力される。また、外部の回路から入力された電気信号は、対応する突起電極１５０１および裏面電極１２０５を介して固体撮像装置２０内のそれぞれの構成要素に入力される。 The solid-state imaging device 20 is configured such that, for example, the chip electrode 1501 can be flip-chip mounted on a mounting substrate on which electronic components are mounted. The electrical signal output from the solid-state imaging device 20 is output to an external circuit via the corresponding back surface electrode 1205 and protruding electrode 1501. In addition, an electrical signal input from an external circuit is input to each component in the solid-state imaging device 20 via the corresponding protruding electrode 1501 and back electrode 1205.
　ここで、固体撮像装置２０を製造する製造工程の概略について説明する。固体撮像装置２０は、以下のような順番でそれぞれの工程を進めることによって、最終的な構造とする。 Here, an outline of a manufacturing process for manufacturing the solid-state imaging device 20 will be described. The solid-state imaging device 20 has a final structure by proceeding with the respective steps in the following order.
　（工程１）
　第１の半導体基板１１に第１の半導体層１１１６と第１の配線層１１１８とのそれぞれを形成する。また、第２の半導体基板１２に第２の半導体層１２０３と第２の配線層１２０１とのそれぞれを形成する。なお、固体撮像装置２０においても、固体撮像装置１０と同様に、この工程１において、マイクロレンズ１１１１と、カラーフィルター１１１２と、透明樹脂層１１１３と、遮光膜１１１４と、反射防止膜１１１５とは、第１の半導体基板１１に形成しない。 (Process 1)
Each of the first semiconductor layer 1116 and the first wiring layer 1118 is formed on the first semiconductor substrate 11. In addition, the second semiconductor layer 1203 and the second wiring layer 1201 are formed on the second semiconductor substrate 12. In the solid-state imaging device 20 as well as the solid-state imaging device 10, in this step 1, the microlens 1111, the color filter 1112, the transparent resin layer 1113, the light shielding film 1114, and the antireflection film 1115 are: It is not formed on the first semiconductor substrate 11.
　（工程２）
　工程１において形成した第１の半導体基板１１と第２の半導体基板１２とを積層する。このとき、図５に示したように、第１の半導体基板１１の第１の配線層１１１８側の面と、第２の半導体基板１２の第２の配線層１２０１側の面とを対向させて、直接接合する。なお、接合する第１の半導体基板１１と第２の半導体基板１２とのそれぞれの面に、例えば、シリコン酸化膜やシリコン窒化膜などの接続用の膜を設け、この接続用の膜を接着層として用いて接合してもよい。 (Process 2)
The first semiconductor substrate 11 and the second semiconductor substrate 12 formed in step 1 are stacked. At this time, as shown in FIG. 5, the surface on the first wiring layer 1118 side of the first semiconductor substrate 11 and the surface on the second wiring layer 1201 side of the second semiconductor substrate 12 are opposed to each other. Join directly. For example, a connection film such as a silicon oxide film or a silicon nitride film is provided on each surface of the first semiconductor substrate 11 and the second semiconductor substrate 12 to be bonded, and this connection film is used as an adhesive layer. It may be used as a joint.
　（工程３）
　第１の半導体基板１１と第２の半導体基板１２とを接合した状態で、第１の半導体基板１１の第１の半導体層１１１６側の面のシリコン層、すなわち、光（光線）が入射する側のシリコン層をエッチングし、第１の半導体基板１１を薄化する。 (Process 3)
In a state where the first semiconductor substrate 11 and the second semiconductor substrate 12 are joined, the silicon layer on the surface of the first semiconductor substrate 11 on the first semiconductor layer 1116 side, that is, the side on which light (light rays) is incident. The silicon layer is etched to thin the first semiconductor substrate 11.
　（工程４）
　第１の半導体基板１１の第１の半導体層１１１６側の面に、反射防止膜１１１５、遮光膜１１１４、透明樹脂層１１１３、カラーフィルター１１１２、およびマイクロレンズ１１１１を順次形成する。 (Process 4)
An antireflection film 1115, a light shielding film 1114, a transparent resin layer 1113, a color filter 1112, and a microlens 1111 are sequentially formed on the surface of the first semiconductor substrate 11 on the first semiconductor layer 1116 side.
　（工程５）
　第１の半導体基板１１のマイクロレンズ１１１１が形成された側の面に、ガラス基板１４を積層する。 (Process 5)
A glass substrate 14 is laminated on the surface of the first semiconductor substrate 11 on which the microlenses 1111 are formed.
　（工程６）
　ガラス基板１４と、第１の半導体基板１１および第２の半導体基板１２とを接合した状態で、第２の半導体基板１２の第２の半導体層１２０３側の面のシリコン層をエッチングし、第２の半導体基板１２を薄化する。 (Step 6)
In a state where the glass substrate 14 is bonded to the first semiconductor substrate 11 and the second semiconductor substrate 12, the silicon layer on the surface of the second semiconductor substrate 12 on the second semiconductor layer 1203 side is etched, and the second semiconductor substrate 120 is etched. The semiconductor substrate 12 is thinned.
　（工程７）
　第２の半導体基板１２の第２の半導体層１２０３側の面からシリコン貫通電極１２０４と裏面電極１２０５とを形成する。これにより、シリコン貫通電極１２０４と裏面電極１２０５とから構成された、固体撮像装置２０内の構成要素同士で電気信号のやり取りを行う接続電極によって、第１の半導体基板１１に形成された回路要素の信号線と、第２の半導体基板１２に形成された回路要素の信号線とが電気的に接続される。また、シリコン貫通電極１２０４と裏面電極１２０５とから構成された、外部の回路との間で電気信号の入出力を行う接続電極（以下、接続電極を区別する場合には、「入出力電極」という）によって、第１の半導体基板１１に形成された回路要素、または第２の半導体基板１２に形成された回路要素が、外部との間で電気信号をやり取りすることができる状態になる。 (Step 7)
A silicon through electrode 1204 and a back electrode 1205 are formed from the surface of the second semiconductor substrate 12 on the second semiconductor layer 1203 side. As a result, the circuit elements formed on the first semiconductor substrate 11 by the connection electrodes configured to include the silicon through electrode 1204 and the back electrode 1205 and exchange electric signals between the components in the solid-state imaging device 20. The signal line and the signal line of the circuit element formed on the second semiconductor substrate 12 are electrically connected. In addition, a connection electrode composed of a silicon through electrode 1204 and a back electrode 1205 that inputs / outputs an electric signal to / from an external circuit (hereinafter referred to as “input / output electrode” when the connection electrode is distinguished). ), The circuit element formed on the first semiconductor substrate 11 or the circuit element formed on the second semiconductor substrate 12 can exchange electric signals with the outside.
　（工程８）
　第２の半導体基板１２の接続電極が形成された側の面に、保護膜１５３０を形成する。そして、入出力電極の位置の保護膜１５３０を除去した後、この部分に突起電極１５０１を形成する。 (Process 8)
A protective film 1530 is formed on the surface of the second semiconductor substrate 12 on which the connection electrode is formed. Then, after removing the protective film 1530 at the position of the input / output electrode, the protruding electrode 1501 is formed in this portion.
　第２の実施形態によれば、第１の半導体基板１１と第２の半導体基板１２とが積層された状態を支持する支持基板（ガラス基板１４）、をさらに備え、ガラス基板１４は、第１の半導体基板１１および第２の半導体基板１２と異なる材料である固体撮像装置（固体撮像装置２０）が構成される。 According to the second embodiment, the semiconductor device further includes a support substrate (glass substrate 14) that supports a state in which the first semiconductor substrate 11 and the second semiconductor substrate 12 are stacked. A solid-state imaging device (solid-state imaging device 20) that is a different material from the semiconductor substrate 11 and the second semiconductor substrate 12 is configured.
　また、第２の実施形態によれば、接続電極（シリコン貫通電極１２０４および裏面電極１２０５）は、第１の半導体基板１１内に形成された回路要素同士の信号線、または第２の半導体基板１２内に形成された回路要素同士の信号線を接続するために形成される金属配線（金属配線１１１９または金属配線１２０２）と異なる材料によって形成される固体撮像装置２０が構成される。 Further, according to the second embodiment, the connection electrodes (the silicon through electrode 1204 and the back electrode 1205) are signal lines between circuit elements formed in the first semiconductor substrate 11 or the second semiconductor substrate 12. A solid-state imaging device 20 formed of a material different from a metal wiring (metal wiring 1119 or metal wiring 1202) formed to connect signal lines between circuit elements formed therein is configured.
　また、第２の実施形態によれば、接続電極（シリコン貫通電極１２０４および裏面電極１２０５）は、第１の半導体基板１１内に形成された回路要素同士の信号線、または第２の半導体基板１２内に形成された回路要素同士の信号線を接続するために形成される金属配線（金属配線１１１９または金属配線１２０２）と同じ材料によって形成される固体撮像装置２０が構成される。 Further, according to the second embodiment, the connection electrodes (the silicon through electrode 1204 and the back electrode 1205) are signal lines between circuit elements formed in the first semiconductor substrate 11 or the second semiconductor substrate 12. A solid-state imaging device 20 formed of the same material as a metal wiring (metal wiring 1119 or metal wiring 1202) formed to connect signal lines between circuit elements formed therein is configured.
　上記に述べたように、第２の実施形態の固体撮像装置２０でも、第１の実施形態の固体撮像装置１０と同様に、第２の半導体基板１２の第２の半導体層１２０３側の面からシリコン貫通電極１２０４と裏面電極１２０５とによって構成される接続電極を形成する。これにより、第２の実施形態の固体撮像装置２０でも、第１の実施形態の固体撮像装置１０と同様の効果を得ることができる。 As described above, in the solid-state imaging device 20 of the second embodiment as well as the solid-state imaging device 10 of the first embodiment, from the surface of the second semiconductor substrate 12 on the second semiconductor layer 1203 side. A connection electrode composed of the through silicon via 1204 and the back electrode 1205 is formed. Thereby, also in the solid-state imaging device 20 of 2nd Embodiment, the effect similar to the solid-state imaging device 10 of 1st Embodiment can be acquired.
　また、第２の実施形態の固体撮像装置２０では、固体撮像装置２０に光（光線）が入射する側と反対側の面に突起電極１５０１を形成する。これにより、第２の実施形態の固体撮像装置２０では、第１の実施形態の固体撮像装置１０よりもさらに小型化を図ることができる。 Further, in the solid-state imaging device 20 of the second embodiment, the protruding electrode 1501 is formed on the surface opposite to the side on which light (light rays) enters the solid-state imaging device 20. Thereby, in the solid-state imaging device 20 of 2nd Embodiment, size reduction can be achieved further than the solid-state imaging device 10 of 1st Embodiment.
　なお、第２の実施形態では、固体撮像装置２０に光（光線）が入射する側の面に、積層されて薄化された第１の半導体基板１１と第２の半導体基板１２とを支持する支持基板としてガラス基板１４を接合し、固体撮像装置２０に光（光線）が入射する側と反対側の面に、保護膜１５３０と突起電極１５０１とを形成した構成を示した。しかし、ガラス基板１４は、固体撮像装置２０に光（光線）が入射する側と反対側の面に保護膜１５３０と突起電極１５０１とを形成しない構成の固体撮像装置において、支持基板として用いてもよい。例えば、第１の実施形態の固体撮像装置１０において、支持基板１３の代わりに、ガラス基板１４を固体撮像装置１０に光（光線）が入射する側の面に接合した構成にしてもよい。この構成の固体撮像装置を製造する場合の製造工程は、上述した固体撮像装置２０を製造する製造工程において、工程７で入出力電極を形成せず、その後の工程８で突起電極１５０１を形成しないのみの違いである。 In the second embodiment, the first semiconductor substrate 11 and the second semiconductor substrate 12 that are stacked and thinned are supported on the surface on the light incident side of the solid-state imaging device 20. A configuration is shown in which a glass substrate 14 is bonded as a support substrate, and a protective film 1530 and a protruding electrode 1501 are formed on the surface opposite to the side on which light (light rays) enters the solid-state imaging device 20. However, the glass substrate 14 may be used as a support substrate in a solid-state imaging device having a configuration in which the protective film 1530 and the protruding electrode 1501 are not formed on the surface opposite to the side on which light (light rays) enters the solid-state imaging device 20. Good. For example, in the solid-state imaging device 10 of the first embodiment, instead of the support substrate 13, a glass substrate 14 may be bonded to the surface on the light incident side of the solid-state imaging device 10. In the manufacturing process for manufacturing the solid-state imaging device having this configuration, in the manufacturing process for manufacturing the solid-state imaging device 20 described above, the input / output electrodes are not formed in step 7 and the protruding electrodes 1501 are not formed in the subsequent step 8. The only difference is.
　また、第２の実施形態では、固体撮像装置２０が外部の回路との間で電気信号の入出力を行うための構成として、光（光線）が入射する側と反対側の面に、突起電極１５０１を固体撮像装置２０の端子として形成する場合の構成について説明した。しかし、固体撮像装置２０が外部の回路との間で電気信号の入出力を行うための端子の構成は、図５に示したような球状の突起電極１５０１の構成に限定されることはない。例えば、図５に示した固体撮像装置２０において、突起電極１５０１が形成される位置の裏面電極１２０５の高さ（厚さ）を、保護膜１５３０と同様または保護膜１５３０よりも高くする（厚くする）ことによって、その部分の裏面電極１２０５を、固体撮像装置２０が外部の回路との間で電気信号の入出力を行うための端子として使用する構成にしてもよい。つまり、半導体のパッケージで例えると、図５に示した固体撮像装置２０はＢＧＡ（Ｂａｌｌ　ｇｒｉｄ　ａｒｒａｙ）のような形状であるが、ＬＧＡ（Ｌａｎｄ　ｇｒｉｄ　ａｒｒａｙ）のような形状にしてもよい。この構成の固体撮像装置であっても、電子部品を実装する実装基板にフリップチップ実装をすることができる。 Further, in the second embodiment, as a configuration for the solid-state imaging device 20 to input / output an electric signal to / from an external circuit, a protruding electrode is provided on the surface opposite to the side on which light (light rays) is incident. The configuration when 1501 is formed as a terminal of the solid-state imaging device 20 has been described. However, the configuration of the terminal for the solid-state imaging device 20 to input / output an electric signal to / from an external circuit is not limited to the configuration of the spherical protruding electrode 1501 as shown in FIG. For example, in the solid-state imaging device 20 shown in FIG. 5, the height (thickness) of the back electrode 1205 at the position where the protruding electrode 1501 is formed is the same as or higher than the protective film 1530 (thicker). Thus, the back electrode 1205 at that portion may be used as a terminal for the solid-state imaging device 20 to input / output an electric signal to / from an external circuit. In other words, in the case of a semiconductor package, the solid-state imaging device 20 shown in FIG. 5 is shaped like a BGA (Ball grid array), but may be shaped like a LGA (Land grid array). Even a solid-state imaging device having this configuration can be flip-chip mounted on a mounting substrate on which electronic components are mounted.
　また、第２の実施形態では、支持基板としてガラス基板１４を用いた場合について説明したが、上述したように、積層されて薄化された第１の半導体基板１１と第２の半導体基板１２とを支持して機械的強度を維持する基板であれば、いかなる材料の基板であってもよい。例えば、第１の半導体基板１１に形成したマイクロレンズ１１１１における光の屈折率の調整に用いる樹脂を支持基板の材料として、機械的強度の維持と屈折率の調整との両方の役割を担った構成にしてもよい。また、例えば、固体撮像装置における支持基板の役目を、固体撮像装置の製造工程において積層されて薄化される第１の半導体基板１１と第２の半導体基板１２との機械的強度を維持するのみの役目と考え、電子部品を実装する実装基板に固体撮像装置を実装した後に除去することができる材料を、支持基板の材料として用いた構成にしてもよい。 Further, in the second embodiment, the case where the glass substrate 14 is used as the support substrate has been described. However, as described above, the first semiconductor substrate 11 and the second semiconductor substrate 12 that are stacked and thinned are used. The substrate may be made of any material as long as it supports the substrate and maintains the mechanical strength. For example, the resin used for adjusting the refractive index of light in the microlens 1111 formed on the first semiconductor substrate 11 is used as a material for the support substrate, and plays a role of both maintaining the mechanical strength and adjusting the refractive index. It may be. Further, for example, the role of the support substrate in the solid-state imaging device is only to maintain the mechanical strength of the first semiconductor substrate 11 and the second semiconductor substrate 12 that are stacked and thinned in the manufacturing process of the solid-state imaging device. In view of this role, a material that can be removed after mounting the solid-state imaging device on the mounting substrate on which the electronic component is mounted may be used as the material of the support substrate.
　上記に述べたように、本発明の各実施形態によれば、複数の半導体基板を積層した構成の固体撮像装置において、光（光線）が入射する側と反対側の面から、シリコン貫通電極と裏面電極とによって構成される接続電極を形成して、それぞれの半導体基板に形成された回路要素の信号線を電気的に接続する。これにより、本発明の各実施形態では、固体撮像装置に形成された画素に光（光線）が入射する側と反対側で画素に重なる領域、すなわち、画素の領域の直下の領域にも、それぞれの半導体基板に形成された構成要素同士を接続することができる。このことにより、本発明の各実施形態では、複数の半導体基板を積層した構成にすることによる固体撮像装置の性能や機能の向上と共に、それぞれの半導体基板を接続するために形成する配線の自由度を向上させ、固体撮像装置の小型化を実現することができる。また、本発明の各実施形態では、それぞれの半導体基板に形成された構成要素同士でやり取りされる信号線の遅延を少なくすることができ、固体撮像装置の性能や機能をさらに向上することができる。 As described above, according to each embodiment of the present invention, in a solid-state imaging device having a configuration in which a plurality of semiconductor substrates are stacked, a through silicon via electrode is formed from a surface opposite to a side on which light (light rays) is incident. A connection electrode composed of a back electrode is formed, and signal lines of circuit elements formed on the respective semiconductor substrates are electrically connected. Thereby, in each embodiment of the present invention, a region overlapping the pixel on the side opposite to the side on which light (light rays) is incident on the pixel formed in the solid-state imaging device, that is, a region immediately below the pixel region, respectively, The components formed on the semiconductor substrate can be connected to each other. Thus, in each embodiment of the present invention, the performance and function of the solid-state imaging device is improved by stacking a plurality of semiconductor substrates, and the degree of freedom of wiring formed to connect each semiconductor substrate is increased. The solid-state imaging device can be downsized. In each embodiment of the present invention, the delay of signal lines exchanged between components formed on each semiconductor substrate can be reduced, and the performance and function of the solid-state imaging device can be further improved. .
　また、本発明の各実施形態では、固体撮像装置に光（光線）が入射する側の面に形成された画素の直下の領域にも、外部の回路との間で信号を入出力するための端子を配置することができる。このことにより、本発明の各実施形態では、固体撮像装置のさらなる小型化を実現することができる。 In each embodiment of the present invention, a signal for inputting / outputting a signal to / from an external circuit also in an area immediately below a pixel formed on a surface on which light (light rays) enters the solid-state imaging device. Terminals can be arranged. Thereby, in each embodiment of the present invention, further downsizing of the solid-state imaging device can be realized.
　なお、実施形態においては、第１の半導体基板１１と第２の半導体基板１２との２枚の半導体基板を積層した固体撮像装置の構成について説明した。しかし、上述したように、固体撮像装置において積層する基板の枚数は２枚に限らず、さらに多くの枚数の基板を積層する構成であってもよい。また、実施形態においては、積層した半導体基板を支持するための構成（第１の実施形態においては支持基板１３、第２の実施形態においてはガラス基板１４）を備えた構成について説明した。しかし、例えば、積層した半導体基板の内、いずれかの半導体基板を薄化する量を少なくする、つまり、厚くすることによって積層した半導体基板の機械的強度を維持することができる場合には、積層した半導体基板を支持するための構成を備えない構成にすることもできる。 In the embodiment, the configuration of the solid-state imaging device in which two semiconductor substrates of the first semiconductor substrate 11 and the second semiconductor substrate 12 are stacked has been described. However, as described above, the number of substrates stacked in the solid-state imaging device is not limited to two, and a configuration in which a larger number of substrates is stacked may be used. In the embodiment, the configuration including the configuration for supporting the stacked semiconductor substrates (the support substrate 13 in the first embodiment and the glass substrate 14 in the second embodiment) has been described. However, for example, in the case where the mechanical strength of the stacked semiconductor substrates can be maintained by reducing the amount of thinning of any of the stacked semiconductor substrates, that is, by increasing the thickness, It is also possible to adopt a configuration that does not include a configuration for supporting the semiconductor substrate.
　また、実施形態においては、画素の直下の領域以外の領域では、第１の接続電極アレイ１２４または第２の接続電極アレイ１２５に配置された対応するそれぞれの接続電極部を介して、接合した第１の半導体基板１１と第２の半導体基板１２とに配置された構成要素同士で電気信号の送受信を行う構成について説明した。しかし、シリコン貫通電極１２０４と裏面電極１２０５とによって構成される接続電極は、上述した画素の直下の領域のみに形成される構成ではなく、第１の接続電極アレイ１２４や第２の接続電極アレイ１２５の領域に構成してもよい。つまり、シリコン貫通電極１２０４と裏面電極１２０５とによって構成される接続電極は、積層された半導体基板のいずれの領域にも構成することができる。従って、シリコン貫通電極１２０４と裏面電極１２０５とによる接続電極の構成は、固体撮像装置のみ適用されるのみではなく、複数の半導体基板が積層され、それぞれの半導体基板に形成された回路要素同士の信号線を電気的に接続する半導体装置であれば同様に、本発明の考え方を適用することができる。 In the embodiment, in regions other than the region immediately below the pixels, the first connection electrode array 124 or the second connection electrode array 125 is joined via the corresponding connection electrode portion disposed in the first connection electrode array 124 or the second connection electrode array 125. The configuration in which the electrical signals are transmitted and received between the components arranged on the first semiconductor substrate 11 and the second semiconductor substrate 12 has been described. However, the connection electrode formed by the through silicon via 1204 and the back electrode 1205 is not formed only in the region immediately below the pixel described above, but the first connection electrode array 124 and the second connection electrode array 125. You may comprise in the area | region. That is, the connection electrode constituted by the through silicon via 1204 and the back electrode 1205 can be formed in any region of the stacked semiconductor substrates. Therefore, the configuration of the connection electrode made up of the through silicon via 1204 and the back electrode 1205 is not only applied to the solid-state imaging device, but a plurality of semiconductor substrates are stacked, and signals between circuit elements formed on the respective semiconductor substrates. Similarly, the idea of the present invention can be applied to any semiconductor device in which wires are electrically connected.
　以上、本発明の実施形態について、図面を参照して説明してきたが、具体的な構成はこの実施形態に限定されるものではなく、本発明の趣旨を逸脱しない範囲においての種々の変更も含まれる。 The embodiment of the present invention has been described above with reference to the drawings. However, the specific configuration is not limited to this embodiment, and includes various modifications within the scope of the present invention. It is.
　上記各実施形態によれば、複数の半導体基板を積層した構成の固体撮像装置において、性能や機能の向上と共に、それぞれの半導体基板を接続する配線の自由度を向上させて小型化を実現することができる。 According to each of the above embodiments, in a solid-state imaging device having a configuration in which a plurality of semiconductor substrates are stacked, performance and functions are improved, and the degree of freedom of wiring for connecting each semiconductor substrate is improved, thereby realizing miniaturization. Can do.
　１０，２０　固体撮像装置
　１１　第１の半導体基板
　１１１　画素アレイ部（画素，画素部，第１の半導体基板）
　１１２　水平駆動回路（処理部）
　１１３　ボンディングパッド
　１１１１　マイクロレンズ（画素，画素部，第１の半導体基板）
　１１１２　カラーフィルター（画素，画素部，第１の半導体基板）
　１１１３　透明樹脂層（画素，画素部，第１の半導体基板）
　１１１４　遮光膜（画素，画素部，第１の半導体基板）
　１１１５　反射防止膜（画素，画素部，第１の半導体基板）
　１１１６　第１の半導体層（第１の半導体基板）
　１１１７　光電変換部（画素）
　１１１８　第１の配線層（第１の半導体基板）
　１１１９　金属配線（第１の半導体基板）
　１１３０　接着層
　１２　第２の半導体基板
　１２１　垂直駆動回路（処理部）
　１２２　列処理回路（処理部）
　１２３　信号処理回路（処理部）
　１２４　第１の接続電極アレイ
　１２５　第２の接続電極アレイ
　１２０１　第２の配線層（第２の半導体基板）
　１２０２　金属配線（第２の半導体基板）
　１２０３　第２の半導体層（第２の半導体基板）
　１２０４　シリコン貫通電極（貫通電極，接続電極）
　１２０５　裏面電極（接続電極）
　１２３０　接着層
　１３　支持基板
　１４　ガラス基板（支持基板）
　１５３０　保護膜
　１５０１　突起電極 10, 20 Solid-state imaging device 11 First semiconductor substrate 111 Pixel array unit (pixel, pixel unit, first semiconductor substrate)
112 Horizontal drive circuit (processing unit)
113 Bonding pad 1111 Microlens (pixel, pixel portion, first semiconductor substrate)
1112 Color filter (pixel, pixel portion, first semiconductor substrate)
1113 Transparent resin layer (pixel, pixel portion, first semiconductor substrate)
1114 Light-shielding film (pixel, pixel portion, first semiconductor substrate)
1115 Antireflection film (pixel, pixel portion, first semiconductor substrate)
1116 First semiconductor layer (first semiconductor substrate)
1117 Photoelectric conversion unit (pixel)
1118 First wiring layer (first semiconductor substrate)
1119 Metal wiring (first semiconductor substrate)
1130 Adhesive layer 12 Second semiconductor substrate 121 Vertical drive circuit (processing unit)
122 column processing circuit (processing unit)
123 Signal processing circuit (processing unit)
124 first connection electrode array 125 second connection electrode array 1201 second wiring layer (second semiconductor substrate)
1202 Metal wiring (second semiconductor substrate)
1203 Second semiconductor layer (second semiconductor substrate)
1204 Silicon through electrode (through electrode, connection electrode)
1205 Back electrode (connection electrode)
1230 Adhesive layer 13 Support substrate 14 Glass substrate (support substrate)
1530 Protective film 1501 Projection electrode

Claims (8)

  1. 　入射された光線を電気信号に変換して出力する光電変換部を具備した画素が二次元のマトリクス状に複数配置された画素部の回路要素が形成された第１の半導体層を有する第１の半導体基板と、
    　前記光電変換部が出力した前記電気信号に対して処理を行う処理部の回路要素が形成された第２の半導体層を有する第２の半導体基板と、
    　前記第１の半導体基板と前記第２の半導体基板とを積層した状態で、前記第１の半導体層に形成された回路要素の信号線と、前記第２の半導体層に形成された回路要素の信号線とを電気的に接続する接続電極と、
    　を備え、
    　前記接続電極は、
    　前記第２の半導体基板内の第２の半導体層を貫通する貫通電極、
    　を備える固体撮像装置。     A first semiconductor layer having a first semiconductor layer in which circuit elements of a pixel portion in which a plurality of pixels each including a photoelectric conversion portion that converts incident light into an electrical signal and outputs the electrical signal are arranged in a two-dimensional matrix are formed; A semiconductor substrate;
    A second semiconductor substrate having a second semiconductor layer on which circuit elements of a processing unit that processes the electrical signal output from the photoelectric conversion unit are formed;
    In a state where the first semiconductor substrate and the second semiconductor substrate are stacked, the signal lines of the circuit elements formed in the first semiconductor layer and the circuit elements formed in the second semiconductor layer A connection electrode for electrically connecting the signal line;
    With
    The connection electrode is
    A through electrode penetrating a second semiconductor layer in the second semiconductor substrate;
    A solid-state imaging device.
  2. 　前記接続電極は、
    　前記画素部に前記光線が入射する側とは反対側で、前記画素部の領域に重なるように配置される
    　請求項１に記載の固体撮像装置。     The connection electrode is
    The solid-state imaging device according to claim 1, wherein the solid-state imaging device is disposed so as to overlap a region of the pixel unit on a side opposite to a side on which the light ray enters the pixel unit.
  3. 　前記第１の半導体基板と前記第２の半導体基板とが積層された状態を支持する支持基板、
    　をさらに備え、
    　前記支持基板は、
    　前記第１の半導体基板および前記第２の半導体基板と同じ材料である
    　請求項２に記載の固体撮像装置。     A support substrate for supporting a state in which the first semiconductor substrate and the second semiconductor substrate are stacked;
    Further comprising
    The support substrate is
    The solid-state imaging device according to claim 2, wherein the first semiconductor substrate and the second semiconductor substrate are made of the same material.
  4. 　前記第１の半導体基板と前記第２の半導体基板とが積層された状態を支持する支持基板、
    　をさらに備え、
    　前記支持基板は、
    　前記第１の半導体基板および前記第２の半導体基板と異なる材料である
    　請求項２に記載の固体撮像装置。     A support substrate for supporting a state in which the first semiconductor substrate and the second semiconductor substrate are stacked;
    Further comprising
    The support substrate is
    The solid-state imaging device according to claim 2, wherein the material is different from that of the first semiconductor substrate and the second semiconductor substrate.
  5. 　前記接続電極は、
    　前記第１の半導体基板内に形成された回路要素同士の信号線、または前記第２の半導体基板内に形成された回路要素同士の信号線を接続するために形成される金属配線と異なる材料によって形成される
    　請求項３に記載の固体撮像装置。     The connection electrode is
    By a material different from the metal wiring formed to connect the signal lines between the circuit elements formed in the first semiconductor substrate or the signal lines between the circuit elements formed in the second semiconductor substrate. The solid-state imaging device according to claim 3 formed.
  6. 　前記接続電極は、
    　前記第１の半導体基板内に形成された回路要素同士の信号線、または前記第２の半導体基板内に形成された回路要素同士の信号線を接続するために形成される金属配線と異なる材料によって形成される
    　請求項４に記載の固体撮像装置。     The connection electrode is
    By a material different from the metal wiring formed to connect the signal lines between the circuit elements formed in the first semiconductor substrate or the signal lines between the circuit elements formed in the second semiconductor substrate. The solid-state imaging device according to claim 4 formed.
  7. 　前記接続電極は、
    　前記第１の半導体基板内に形成された回路要素同士の信号線、または前記第２の半導体基板内に形成された回路要素同士の信号線を接続するために形成される金属配線と同じ材料によって形成される
    　請求項３に記載の固体撮像装置。     The connection electrode is
    By the same material as the metal wiring formed to connect the signal lines between the circuit elements formed in the first semiconductor substrate or the signal lines between the circuit elements formed in the second semiconductor substrate. The solid-state imaging device according to claim 3 formed.
  8. 　前記接続電極は、
    　前記第１の半導体基板内に形成された回路要素同士の信号線、または前記第２の半導体基板内に形成された回路要素同士の信号線を接続するために形成される金属配線と同じ材料によって形成される
    　請求項４に記載の固体撮像装置。     The connection electrode is
    By the same material as the metal wiring formed to connect the signal lines between the circuit elements formed in the first semiconductor substrate or the signal lines between the circuit elements formed in the second semiconductor substrate. The solid-state imaging device according to claim 4 formed.
PCT/JP2014/073333 2014-09-04 2014-09-04 Solid-state image pickup device WO2016035184A1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110546765A (en) * 2017-04-25 2019-12-06 松下知识产权经营株式会社 solid-state imaging device and imaging device

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001339057A (en) * 2000-05-30 2001-12-07 Mitsumasa Koyanagi Method of manufacturing three-dimensional image processor
US20070018075A1 (en) * 2005-07-21 2007-01-25 Stmicroelectronics S.A. Image sensor
JP2007228460A (en) * 2006-02-27 2007-09-06 Mitsumasa Koyanagi Stacked semiconductor device with integrated sensor mounted thereon
JP2008211220A (en) * 2007-02-26 2008-09-11 Samsung Electronics Co Ltd Image sensor having backside illumination structure, and method of manufacturing the image sensor
JP2011044489A (en) * 2009-08-19 2011-03-03 Toshiba Corp Solid-state imaging device and method of manufacturing the same
JP2011049445A (en) * 2009-08-28 2011-03-10 Sony Corp Solid-state imaging device, manufacturing method therefor, and electronic device
WO2011077580A1 (en) * 2009-12-26 2011-06-30 キヤノン株式会社 Solid-state imaging device and imaging system
JP2014041867A (en) * 2012-08-21 2014-03-06 Toshiba Corp Solid-state image pickup device, and manufacturing method thereof

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001339057A (en) * 2000-05-30 2001-12-07 Mitsumasa Koyanagi Method of manufacturing three-dimensional image processor
US20070018075A1 (en) * 2005-07-21 2007-01-25 Stmicroelectronics S.A. Image sensor
JP2007228460A (en) * 2006-02-27 2007-09-06 Mitsumasa Koyanagi Stacked semiconductor device with integrated sensor mounted thereon
JP2008211220A (en) * 2007-02-26 2008-09-11 Samsung Electronics Co Ltd Image sensor having backside illumination structure, and method of manufacturing the image sensor
JP2011044489A (en) * 2009-08-19 2011-03-03 Toshiba Corp Solid-state imaging device and method of manufacturing the same
JP2011049445A (en) * 2009-08-28 2011-03-10 Sony Corp Solid-state imaging device, manufacturing method therefor, and electronic device
WO2011077580A1 (en) * 2009-12-26 2011-06-30 キヤノン株式会社 Solid-state imaging device and imaging system
JP2014041867A (en) * 2012-08-21 2014-03-06 Toshiba Corp Solid-state image pickup device, and manufacturing method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110546765A (en) * 2017-04-25 2019-12-06 松下知识产权经营株式会社 solid-state imaging device and imaging device
CN110546765B (en) * 2017-04-25 2023-10-13 新唐科技日本株式会社 Solid-state imaging device and imaging device

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