JP2001111232A - Electronic component mounting multilayer board and manufacturing method thereof - Google Patents
Electronic component mounting multilayer board and manufacturing method thereofInfo
- Publication number
- JP2001111232A JP2001111232A JP28578799A JP28578799A JP2001111232A JP 2001111232 A JP2001111232 A JP 2001111232A JP 28578799 A JP28578799 A JP 28578799A JP 28578799 A JP28578799 A JP 28578799A JP 2001111232 A JP2001111232 A JP 2001111232A
- Authority
- JP
- Japan
- Prior art keywords
- mounting
- electronic component
- lsi
- board
- interlayer wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01087—Francium [Fr]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/162—Disposition
- H01L2924/1627—Disposition stacked type assemblies, e.g. stacked multi-cavities
Landscapes
- Physics & Mathematics (AREA)
- Health & Medical Sciences (AREA)
- Electromagnetism (AREA)
- Toxicology (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Combinations Of Printed Boards (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体集積回路装
置や受動素子などの電子部品を高密度実装した携帯端末
装置に適用して好適な電子部品実装多層基板及びその製
造方法に関する。詳しくは、シールド用の導電部材に対
向して電子部品を実装した実装基板間に、中継ぎ用の層
間配線部材を設け、この層間配線部材を挟んで実装基板
を積層すると共に、その層間配線部材により実装基板間
を電気的に接合するようにして、シールド付きの電子部
品の実装面積を積層方向に立体的に増加できるようにし
たものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic component-mounted multilayer board suitable for application to a portable terminal device on which electronic components such as a semiconductor integrated circuit device and a passive element are mounted at a high density, and a method of manufacturing the same. More specifically, an inter-layer wiring member for intermediary is provided between mounting boards on which electronic components are mounted in opposition to the conductive member for shielding, and the mounting boards are laminated with the inter-layer wiring member interposed therebetween. By electrically connecting the mounting substrates, the mounting area of the electronic component with the shield can be three-dimensionally increased in the stacking direction.
【０００２】[0002]
【従来の技術】近年、携帯電話機や、携帯用のパーソナ
ルコンピュータなどの携帯端末装置に、ベアーチップ状
の半導体集積回路装置（以下単にＬＳＩチップという）
を実装したＬＳＩ実装基板が使用されるようになってき
た。この種の実装基板には個々のＬＳＩチップがモール
ド成形されることなく、複数のＬＳＩチップが実装基板
の一方の面に平面的に並べて配置され、他方の面に抵抗
や、コンデンサなどの電子部品が実装されている。ま
た、近接回路間のノイズ対策に関しては、金属の筐体を
個々のＬＳＩチップに覆い被せるようにしてシールドし
ている。2. Description of the Related Art In recent years, a portable terminal device such as a portable telephone or a portable personal computer has been used in a bare chip semiconductor integrated circuit device (hereinafter simply referred to as an LSI chip).
Has come to be used. On this type of mounting board, a plurality of LSI chips are arranged in a plane on one side of the mounting board without molding individual LSI chips, and electronic components such as resistors and capacitors are mounted on the other side. Has been implemented. In addition, with respect to measures against noise between adjacent circuits, the metal casing is shielded so as to cover each LSI chip.
【０００３】[0003]
【発明が解決しようとする課題】ところで、従来方式の
ＬＳＩ実装基板によれば、ＬＳＩチップが平面的に並べ
て配置されるので、電子部品の高密度な実装要求に対し
て、部品搭載面積に限界を生ずるに至っている。従っ
て、近年のプリント配線板の小型化、つまり、電子機器
の小型化の要求に満足できなくなってきた。併せて、電
子機器の小型化により、近接回路間のノイズも問題とな
ってきた。However, according to the conventional LSI mounting board, since the LSI chips are arranged in a plane, the component mounting area is limited in response to a demand for high-density mounting of electronic components. Is caused. Therefore, it has become impossible to satisfy the recent demand for miniaturization of printed wiring boards, that is, miniaturization of electronic devices. At the same time, with the miniaturization of electronic devices, noise between adjacent circuits has also become a problem.
【０００４】この種の問題に対して、技術文献である特
開平２−１６４０９６号公報の「多層電子回路基板とそ
の製造方法」には、電子回路を構成する回路素子をプリ
ント配線基板の層間に内蔵し、電子回路の高密度な実装
を図ることが記載されている。また、特開平５−３４３
８５６号公報の「多層プリント配線基板及びその製造方
法」には、電子回路などを構成するハイブリッドモジュ
ールをプリント配線基板間に挟み込み、電子回路などを
高密度に実装することが記載されている。In order to solve this kind of problem, Japanese Patent Laid-Open Publication No. 2-164096 discloses a "multilayer electronic circuit board and a method for manufacturing the same", in which circuit elements constituting an electronic circuit are placed between layers of a printed wiring board. It describes that the electronic circuit is built-in to achieve high-density mounting of electronic circuits. Also, Japanese Patent Application Laid-Open No. 5-343
Japanese Patent Publication No. 856 discloses "Multilayer Printed Wiring Board and Manufacturing Method Thereof", in which a hybrid module constituting an electronic circuit or the like is sandwiched between printed wiring boards to mount electronic circuits or the like at high density.
【０００５】更に、特開平３−１４２９３号公報の「多
層高密度実装モジュール」には、電子回路などを中間層
に内蔵したプリント配線基板を積層する際に、ハンダバ
ンプと接する面に白金、あるいはパラジウムメッキを施
すことが記載されている。いずれの技術文献も、電子部
品の実装面積を積層方向に立体的に増加することができ
ても、シールド付きの電子部品の実装面積を積層方向に
立体的に増加することがでない。[0005] Further, in the "multilayer high-density mounting module" disclosed in JP-A-3-14293, when a printed wiring board having an electronic circuit or the like embedded in an intermediate layer is laminated, platinum or palladium is applied to a surface in contact with a solder bump. It is described that plating is performed. In any of the technical documents, even though the mounting area of the electronic component can be three-dimensionally increased in the stacking direction, the mounting area of the electronic component with the shield does not increase three-dimensionally in the stacking direction.
【０００６】そこで、この発明はこのような従来の課題
を解決したものであって、シールド付きの電子部品の実
装面積を積層方向に立体的に増加できるようにした電子
部品実装多層基板及びその製造方法を提供することを目
的とする。SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems, and it is an object of the present invention to provide a multi-layer board for mounting electronic components, which is capable of three-dimensionally increasing the mounting area of electronic components with a shield in the stacking direction. The aim is to provide a method.
【０００７】[0007]
【課題を解決するための手段】上述した課題は、一方の
面又は両面に電子部品を実装した実装基板が複数と、実
装基板間に設けられた中継ぎ用の層間配線部材と、この
層間配線部材によって画定される領域内であって、少な
くとも、電子部品に対向する側の実装基板に設けられた
所定の広さのシールド用の導電部材とを備え、実装基板
が層間配線部材を挟んで積層されると共に、該実装基板
間が層間配線部材により電気的に接合された多層構造を
成していることを特徴とする電子部品実装多層基板によ
って解決される。SUMMARY OF THE INVENTION The above-mentioned problems are solved by a plurality of mounting boards having electronic components mounted on one or both surfaces thereof, an intermediate wiring member provided between the mounting boards, and an intermediate wiring member. And a conductive member for shielding having a predetermined size provided on the mounting board on the side facing the electronic component at least, and the mounting board is laminated with the interlayer wiring member interposed therebetween. In addition, the electronic component mounting multilayer substrate is characterized in that the mounting substrate has a multilayer structure electrically connected by an interlayer wiring member.
【０００８】本発明に係る電子部品実装多層基板によれ
ば、シールド用の導電部材と対向した電子部品を実装す
る実装基板間に中継ぎ用の層間配線部材が設けられ、そ
の実装基板が層間配線部材を挟んで積層されると共に、
その実装基板間が層間配線部材により電気的に接合され
た多層構造を成している。According to the electronic component mounting multilayer board according to the present invention, an intermediate wiring member is provided between the mounting substrate for mounting the electronic component facing the conductive member for shielding, and the mounting substrate is connected to the interlayer wiring member. While being laminated with
The mounting boards form a multilayer structure in which they are electrically connected by interlayer wiring members.
【０００９】従って、所定の広さの導電部材によってシ
ールドされた電子部品の実装面積を積層方向に立体的に
増加させることができ、電子部品を平面に並べてシール
ド実装する場合に比べて、シールド付きの電子部品を高
密度に実装することができる。Therefore, the mounting area of the electronic component shielded by the conductive member having a predetermined size can be three-dimensionally increased in the laminating direction, and compared with the case where the electronic components are arranged in a plane and shielded, the electronic component is shielded. Electronic components can be mounted at high density.
【００１０】本発明に係る電子部品実装多層基板の製造
方法は、一方の面又は両面に電子部品を実装して実装基
板を形成すると共に、電子部品に対向する側の他の実装
基板に所定の広さのシールド用の導電部材を形成する工
程と、電子部品を導電部材に対向するようにして実装基
板間に中継ぎ用の層間配線部材を挟んで積層し接合する
工程と、実装基板間を層間配線部材により電気的に接合
する工程とを有することを特徴とするものである。According to a method of manufacturing an electronic component-mounted multilayer substrate according to the present invention, an electronic component is mounted on one or both surfaces to form a mounting substrate, and a predetermined mounting is performed on another mounting substrate facing the electronic component. A step of forming a conductive member for shielding of a size, a step of laminating and joining electronic parts so as to face the conductive member with an interlayer wiring member for a relay between mounting boards, and a step of forming an interlayer between the mounting boards. Electrically connecting with a wiring member.
【００１１】本発明に係る電子部品実装多層基板の製造
方法によれば、シールド付きの電子部品の実装面積を積
層方向に立体的に増加させることができ、電子部品を平
面に並べてシールド実装する場合に比べて、シールド付
きの電子部品を高密度に実装することができる。これに
より、当該電子部品実装多層基板を適用した電子機器の
小型化を図ることができる。According to the method of manufacturing an electronic component-mounted multilayer board according to the present invention, the mounting area of the shielded electronic component can be three-dimensionally increased in the laminating direction. , Electronic components with a shield can be mounted at a higher density. This makes it possible to reduce the size of an electronic device to which the electronic component-mounted multilayer board is applied.
【００１２】[0012]
【発明の実施の形態】続いて、この発明に係る電子部品
実装多層基板及びその製造方法の一実施の形態につい
て、図面を参照しながら説明をする。 （１）第１の実施形態 図１は本発明に係る第１の実施形態としての電子部品実
装多層基板の構成例を示す断面図である。この実施形態
では、シールド用の導電部材に対向して電子部品を実装
した実装基板間に、中継ぎ用の層間配線部材を設け、こ
の層間配線部材を挟んで実装基板を積層すると共に、そ
の層間配線部材により実装基板間を電気的に接合するよ
うにして、シールド付きの電子部品の実装面積を積層方
向に立体的に増加できるようにしたものである。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an embodiment of a multilayer board for mounting electronic components and a method for manufacturing the same according to the present invention will be described with reference to the drawings. (1) First Embodiment FIG. 1 is a cross-sectional view showing a configuration example of an electronic component-mounted multilayer board as a first embodiment according to the present invention. In this embodiment, an interlayer wiring member for a relay is provided between mounting boards on which electronic components are mounted in opposition to a conductive member for shielding, and the mounting boards are laminated with the interlayer wiring member interposed therebetween. The mounting boards are electrically joined by members so that the mounting area of the electronic component with the shield can be three-dimensionally increased in the stacking direction.
【００１３】図１に示す電子部品実装多層基板１００は
半導体集積回路装置（ＬＳＩチップ）などの電子部品を
高密度に実装したものである。ＬＳＩチップは厚みが数
百μｍ程度であり、電子部品実装多層基板１００の厚み
はｔ０であり、電子部品の積層数によるが１ｍｍ前後〜
数ｍｍ程度である。図１に示す例では、一方の面にＬＳ
Ｉチップ３Ａを実装した、厚みｔ１のＬＳＩ実装基板１
Ａが、中継ぎ用の層間配線部材４Ａ，５Ａを挟んで内層
配線基板（第２の実装基板）２の一方の面に積層される
と共に、ＬＳＩ実装基板１Ａ及び内層配線基板２間がそ
の層間配線部材４Ａ，５Ａにより電気的に接合され、し
かも、その内層配線基板２の他方の面に、他の中継ぎ用
の層間配線部材４Ｂ，５Ｂを挟んで他のＬＳＩ実装基板
１Ｂが積層されると共に、ＬＳＩ実装基板１Ｂ及び内層
配線基板２間がその層間配線部材４Ｂ，５Ｂにより電気
的に接合された多層構造を成している。The electronic component mounting multilayer substrate 100 shown in FIG. 1 is a device on which electronic components such as a semiconductor integrated circuit device (LSI chip) are mounted at a high density. The thickness of the LSI chip is about several hundred μm, the thickness of the electronic component-mounted multilayer substrate 100 is t0, and depends on the number of laminated electronic components, but is about 1 mm to
It is about several mm. In the example shown in FIG.
LSI mounting board 1 with thickness t1 on which I chip 3A is mounted
A is laminated on one surface of the inner-layer wiring board (second mounting board) 2 with the intermediate wiring members 4A and 5A interposed therebetween, and the interlayer wiring between the LSI mounting board 1A and the inner-layer wiring board 2 is formed. The other LSI mounting boards 1B are electrically connected to each other by the members 4A and 5A, and the other LSI mounting board 1B is laminated on the other surface of the inner wiring board 2 with the other intermediate wiring members 4B and 5B interposed therebetween. The LSI mounting board 1B and the inner wiring board 2 form a multilayer structure in which they are electrically connected by the interlayer wiring members 4B and 5B.
【００１４】つまり、これらの中継ぎ用の層間配線部材
４Ａ，５ＡはＬＳＩ実装基板１Ａと内層配線基板２との
間に設けられ、その層間配線部材４Ｂ，５ＢはＬＳＩ実
装基板１Ｂと内層配線基板２との間に設けられ、少なく
とも、ＬＳＩ実装基板１Ａ，１Ｂや内層配線基板２を支
える躯体としての性質と、信号などを伝搬する信号線路
と、ＬＳＩチップ３Ａ，３Ｂや信号線などをシールドす
る遮蔽壁としての３つの機能を有している。That is, the intermediate wiring members 4A and 5A for relay are provided between the LSI mounting substrate 1A and the inner wiring substrate 2, and the interlayer wiring members 4B and 5B are provided between the LSI mounting substrate 1B and the inner wiring substrate 2A. And a shield that at least shields the LSI chips 3A and 3B, signal lines, and the like, a signal line for transmitting signals and the like, and a signal line for transmitting signals and the like. It has three functions as a wall.
【００１５】これらの層間配線部材４Ａ，５Ａ，４Ｂ，
５Ｂによって画定される領域内であって、少なくとも、
ＬＳＩチップ３Ａ，３Ｂに対向する側の実装基板、つま
り、内層配線基板２の両面には所定の広さのシールド用
の導電部材６Ａ，６Ｂが設けられる。この導電部材６
Ａ，６Ｂには銅箔などが使用され、このシールド用の銅
箔パターン（以下シールドパターンという）６Ａ，６Ｂ
が接地される。シールドパターン６Ａ，６Ｂは内層配線
基板２の形成時に配線パターンと共に同時に形成される
ので、多層基板構造の簡略化及びその製造工程の短縮化
によるコストダウンにつながる。These interlayer wiring members 4A, 5A, 4B,
Within the area defined by 5B, at least
Conductive members 6A and 6B for shielding having a predetermined size are provided on the mounting substrate facing the LSI chips 3A and 3B, that is, on both surfaces of the inner layer wiring substrate 2. This conductive member 6
Copper foil or the like is used for A and 6B, and a copper foil pattern for shielding (hereinafter referred to as a shield pattern) 6A, 6B
Is grounded. Since the shield patterns 6A and 6B are formed simultaneously with the wiring patterns when the inner wiring substrate 2 is formed, it leads to a cost reduction by simplifying the multilayer substrate structure and shortening the manufacturing process.
【００１６】このシールドパターン６Ａ，６Ｂの大きさ
はＬＳＩチップ３Ａ，３Ｂの上部投影面積よりも広い方
が好ましい。電磁及び静電シールド効果を上げるためで
ある。この例では、ＬＳＩ実装基板１Ａ下のＬＳＩチッ
プ３Ａを内層配線基板２の上面のシールドパターン６Ａ
により電磁シールドすることができ、同様にして、ＬＳ
Ｉ実装基板１Ｂ上のＬＳＩチップ３Ｂを内層配線基板２
の下面のシールドパターン６Ｂにより電磁シールドする
ことができる。The size of the shield patterns 6A, 6B is preferably larger than the upper projected area of the LSI chips 3A, 3B. This is to enhance the electromagnetic and electrostatic shielding effects. In this example, the LSI chip 3A under the LSI mounting board 1A is connected to the shield pattern 6A on the upper surface of the inner wiring board 2.
Can be electromagnetically shielded, and similarly, LS
The LSI chip 3B on the I-mount substrate 1B is
Can be electromagnetically shielded by the shield pattern 6B on the lower surface of the.
【００１７】また、電子部品は実装基板の一方の面に実
装する場合に限られることはなく、これらの実装基板の
両面に電子部品を実装するようにしてもよい。例えば、
一方の面にＬＳＩチップ３Ａ，３Ｂを実装し、他方の面
にチップ状の抵抗や、コンデンサなどの受動素子を実装
する場合や、両面にＬＳＩチップ３Ａ，３Ｂを実装する
場合もある。電子部品を高密度に実装するためである。The electronic components are not limited to being mounted on one surface of the mounting board, but may be mounted on both sides of the mounting board. For example,
The LSI chips 3A and 3B may be mounted on one surface and passive elements such as chip resistors and capacitors may be mounted on the other surface, or the LSI chips 3A and 3B may be mounted on both surfaces. This is for mounting electronic components at high density.
【００１８】このように、第１の実施形態としての電子
部品実装多層基板１００によれば、一方の面にシールド
パターン６Ａと対向したＬＳＩチップ３Ａを実装したＬ
ＳＩ実装基板１Ａが、中継ぎ用の層間配線部材４Ａ，５
Ａを挟んで内層配線基板２の一方の面に積層されると共
に、ＬＳＩ実装基板１Ａ及び内層配線基板２との間がそ
の層間配線部材４Ａ，５Ａにより電気的に接合され、し
かも、その内層配線基板２の他方の面に、他の中継ぎ用
の層間配線部材４Ｂ，５Ｂを挟んでシールドパターン６
Ｂと対向した他のＬＳＩチップ３Ｂを実装したＬＳＩ実
装基板１Ｂが積層されると共に、ＬＳＩ実装基板１Ｂ及
び内層配線基板２との間がその層間配線部材４Ｂ，５Ｂ
により電気的に接合された多層構造を成している。As described above, according to the electronic component mounting multilayer board 100 as the first embodiment, the L on which the LSI chip 3A facing the shield pattern 6A is mounted on one surface.
The SI mounting board 1A is used as an interlayer wiring member 4A, 5
A is laminated on one surface of the inner wiring board 2 with the A interposed therebetween, and the LSI mounting board 1A and the inner wiring board 2 are electrically connected by the interlayer wiring members 4A and 5A. On the other surface of the substrate 2, the shield pattern 6 is sandwiched with the other interlayer wiring members 4 </ b> B and 5 </ b> B
B, an LSI mounting board 1B on which another LSI chip 3B opposed to B is mounted, and the interlayer wiring members 4B, 5B are provided between the LSI mounting board 1B and the inner wiring board 2.
To form a multi-layered structure electrically connected to each other.
【００１９】従って、所定の広さのシールドパターン６
Ａ，６Ｂによって電気的にシールドされたＬＳＩチップ
３Ａ，３Ｂの実装面積を積層方向に立体的に増加させる
ことができ、ＬＳＩチップ３Ａ，３Ｂを平面に並べてシ
ールド実装する場合に比べて、シールド付きのＬＳＩチ
ップ３Ａ，３Ｂを高密度に実装することができる。しか
も、各積層間に設けられたシールドパターン６Ａ，６Ｂ
によって近接回路間のノイズによるクロストークを防止
できる。これにより、当該電子部品実装多層基板１００
を適用した電子機器の小型化及び信頼性の向上を図るこ
とができる。Therefore, the shield pattern 6 having a predetermined size is provided.
The mounting area of the LSI chips 3A and 3B electrically shielded by the A and 6B can be three-dimensionally increased in the stacking direction, and a shielded structure is provided as compared with the case where the LSI chips 3A and 3B are arranged in a plane and shielded. LSI chips 3A and 3B can be mounted at high density. Moreover, the shield patterns 6A, 6B provided between the respective laminations
Thus, crosstalk due to noise between adjacent circuits can be prevented. Thereby, the electronic component mounting multilayer board 100
It is possible to reduce the size and improve the reliability of an electronic device to which the invention is applied.
【００２０】続いて、電子部品実装多層基板１００の製
造方法について説明をする。図２〜図６は電子部品実装
多層基板１００の形成例（その１〜５）を示す工程図で
ある。この例では、内層配線基板２の両面に所定の広さ
のシールド用の導電部材を形成する。この導電部材には
銅箔などを使用する。シールドパターン６Ａ，６Ｂは配
線パターンと共に同時に形成し、各層のシールドパター
ン６Ａ，６Ｂは層間配線部材４Ａ，５Ａ，４Ｂ，５Ｂの
例えば接地線用のスルーホールに共通に接続し当該基板
実装時に一括して接地することを想定する。Next, a method of manufacturing the electronic component mounting multilayer board 100 will be described. 2 to 6 are process diagrams showing examples of forming the electronic component-mounted multilayer substrate 100 (parts 1 to 5). In this example, conductive members for shielding having a predetermined size are formed on both surfaces of the inner wiring board 2. Copper foil or the like is used for this conductive member. The shield patterns 6A and 6B are formed simultaneously with the wiring patterns, and the shield patterns 6A and 6B of each layer are connected in common to, for example, through holes for ground lines of the interlayer wiring members 4A, 5A, 4B and 5B, and are collectively mounted at the time of mounting the board. It is assumed that it is grounded.
【００２１】これを前提として、まず、図２に示す実装
基板１の一方の面にＬＳＩチップ３ＡやＬＳＩチップ３
Ｂを実装してＬＳＩ実装基板１Ａ，１Ｂを形成する。こ
の実装基板１は予め、ガラス布基材エポキシ樹脂銅張積
層板（ＦＲ−４）などの両面銅箔基板を加工して所定の
配線パターンや電極（ラウンド）などを形成したもので
ある。Assuming this, first, the LSI chip 3A or the LSI chip 3A is mounted on one surface of the mounting substrate 1 shown in FIG.
B is mounted to form LSI mounting boards 1A and 1B. The mounting substrate 1 is obtained by previously processing a double-sided copper foil substrate such as a glass cloth base epoxy resin copper-clad laminate (FR-4) to form a predetermined wiring pattern, an electrode (round), and the like.
【００２２】例えば、両面銅箔基板の片面づつにレジス
ト材料を塗布し、その後、配線パターンや電極などの形
を象ったレチクル（例えばネガフィルムや乾板）を使用
してレジスト材料を露光し、その後、このレジスト膜を
マスクにして銅箔をエッチングすることにより配線パタ
ーンや電極などが形成される。両面銅箔基板には、ポリ
イミド系樹脂銅張積層板や、ビスマレイミド−トリアジ
ン（ＢＴレジン）系樹脂銅張積層板を用いてもよい。こ
れら基板は耐熱性や、寸法度安定性に優れている。この
ＬＳＩ実装基板１Ａ，１Ｂは予め形成された複数のパッ
ド電極などにバンプ電極を介在してＬＳＩチップ３Ａ，
３Ｂを接合したものである。バンプ電極はハンダボール
や球状の銀、金などから成る。For example, a resist material is applied to each side of a double-sided copper foil substrate, and then the resist material is exposed using a reticle (for example, a negative film or a dry plate) in the shape of a wiring pattern or an electrode. Thereafter, the copper foil is etched using the resist film as a mask to form a wiring pattern, an electrode, and the like. A polyimide resin copper-clad laminate or a bismaleimide-triazine (BT resin) resin copper-clad laminate may be used for the double-sided copper foil substrate. These substrates are excellent in heat resistance and dimensional stability. The LSI mounting substrates 1A and 1B are provided with a plurality of pad electrodes formed in advance and bump electrodes interposed therebetween to form LSI chips 3A and 1B.
3B joined together. The bump electrodes are made of solder balls, spherical silver, gold, or the like.
【００２３】この例では、ＬＳＩ実装基板１Ａ，１Ｂか
ら動作検査用の電極７，８が引き出される。この動作検
査用の電極７，８は試験電圧を印可したり、テストデー
タを供給したり、その結果データを引き出すために使用
される。この電極７，８としてテスト専用に端子を設け
てもよいが、端子数を極力少なくする観点から、本来の
信号入力線や信号出力線に接続される電極、例えば、層
間配線部材４Ａ，５Ａ，４Ｂ，５Ｂの芯部に設けられる
スルーホールと電気的に接続するためのラウンド電極
７，８が兼用される。In this example, electrodes 7 and 8 for operation inspection are pulled out from the LSI mounting boards 1A and 1B. The electrodes 7 and 8 for operation inspection are used for applying a test voltage, supplying test data, and extracting data as a result. Terminals may be provided exclusively for the test as the electrodes 7 and 8, but from the viewpoint of minimizing the number of terminals, electrodes connected to the original signal input lines and signal output lines, for example, the interlayer wiring members 4A, 5A, Round electrodes 7, 8 for electrically connecting to through holes provided in the cores of 4B, 5B are also used.
【００２４】次に、図３Ａに示す両面基板の両面にシー
ルドパターン６Ａ，６Ｂを有した内層配線基板２を形成
する。もちろん、ＬＳＩ実装基板１Ａ，１Ｂと内層配線
基板２の形成順序はこれに限られることはなく、内層配
線基板２を形成した後に、ＬＳＩ実装基板１Ａ，１Ｂを
形成してもよい。シールドパターン６Ａ，６Ｂは予め両
面銅箔基板をエッチング加工して所定の大きさに形成し
たものである。例えば、両面銅箔基板の片面づつにレジ
スト材料を塗布し、その後、スルーホール用のラウンド
電極９，１１や、配線パターン、シールドパターン６
Ａ，６Ｂなどの形を象ったレチクルを使用してレジスト
材料を露光する。Next, the inner wiring board 2 having the shield patterns 6A and 6B on both sides of the double-sided board shown in FIG. 3A is formed. Of course, the order of forming the LSI mounting boards 1A and 1B and the inner wiring board 2 is not limited to this, and the LSI mounting boards 1A and 1B may be formed after the inner wiring board 2 is formed. The shield patterns 6A and 6B are formed in a predetermined size by etching a double-sided copper foil substrate in advance. For example, a resist material is applied to each side of the double-sided copper foil substrate, and thereafter, round electrodes 9 and 11 for through holes, wiring patterns, and shield patterns 6 are formed.
The resist material is exposed using a reticle in the shape of A, 6B or the like.
【００２５】このシールドパターン６Ａ，６Ｂは接地線
用のスルーホール１２に至るようにパターニングされ
る。その後、このレジスト膜をマスクにして銅箔をエッ
チングする。これにより、スルーホール用のラウンド電
極９，１１や、接地線用のスルーホール１２に至るラウ
ンド電極、プリント配線パターン、シールドパターン６
Ａ，６Ｂなどが形成される。The shield patterns 6A and 6B are patterned so as to reach the ground line through hole 12. Thereafter, the copper foil is etched using the resist film as a mask. As a result, the round electrodes 9 and 11 for the through holes, the round electrodes reaching the through holes 12 for the ground line, the printed wiring pattern, and the shield pattern 6 are formed.
A, 6B, etc. are formed.
【００２６】これらのＬＳＩ実装基板１Ａ，１Ｂや内層
配線基板２が形成できたら、図４に示すＬＳＩテスタ１
０などにより実装基板毎に電気的な検査を行う。この例
では１つのＬＳＩ実装基板１を１個の回路ブロックとし
て取り扱うことができ、当該電子部品実装多層基板１０
０の実装後に、ＬＳＩ実装基板１に故障を生じた際に
は、その故障を起こしたＬＳＩ実装基板１のみの交換が
可能となり、メンテナンス及びその修理が容易となる。When the LSI mounting boards 1A and 1B and the inner wiring board 2 can be formed, the LSI tester 1 shown in FIG.
An electrical test is performed for each mounting board by setting a value of 0 or the like. In this example, one LSI mounting substrate 1 can be handled as one circuit block, and the electronic component mounting multilayer substrate 10
If a failure occurs in the LSI mounting board 1 after the mounting of No. 0, only the failed LSI mounting board 1 can be replaced, and maintenance and repair thereof become easy.
【００２７】この例で動作検査用の電極には、層間配線
部材４Ａ，５Ａや層間配線部材４Ｂ，５Ｂの芯部に設け
られる複数のスルーホールと電気的に接続されるラウン
ド電極７，８が使用される。この複数の電極７，８にＬ
ＳＩテスタ１０のプローブ１３，１４が接触され、回路
ブロック毎にローカルな実装試験が行われる。もちろ
ん、この実装試験に関しては、予めＬＳＩ実装基板１Ａ
やＬＳＩ実装基板１Ｂなどに専用に作成されたテストデ
ータが使用される。In this example, the electrodes for operation inspection include round electrodes 7 and 8 which are electrically connected to a plurality of through holes provided in the cores of the interlayer wiring members 4A and 5A and the interlayer wiring members 4B and 5B. used. L is applied to the plurality of electrodes 7 and 8.
The probes 13 and 14 of the SI tester 10 are brought into contact with each other, and a local mounting test is performed for each circuit block. Of course, regarding this mounting test, the LSI mounting substrate 1A
And test data created exclusively for the LSI mounting board 1B and the like.
【００２８】従って、ＬＳＩ実装基板１Ａ，１Ｂや内層
配線基板２を積層する前に、ＬＳＩ実装基板１Ａ，１Ｂ
の不良を早期に除去することができる。この検査結果で
良品と判定されたＬＳＩ実装基板１Ａ，１Ｂや内層配線
基板２のみを中継ぎ用の層間配線部材４Ａ，５Ａ，４
Ｂ，５Ｂを介在して積層することができる。ＬＳＩ実装
基板１Ａ，１Ｂや内層配線基板２を全部積層した後に電
気的な検査を行う場合に比べて、当該電子部品実装多層
基板１００の生産歩留まりを向上させることができる。Therefore, before stacking the LSI mounting boards 1A and 1B and the inner wiring board 2, the LSI mounting boards 1A and 1B
Can be removed early. Only the LSI mounting boards 1A and 1B and the inner wiring board 2 which are determined to be non-defective in the inspection result are used as interlayer wiring members 4A, 5A and 4 for relaying.
B and 5B can be interposed. The production yield of the electronic component-mounted multilayer substrate 100 can be improved as compared with the case where an electrical inspection is performed after all the LSI mounted substrates 1A and 1B and the inner layer wiring substrate 2 are stacked.
【００２９】次に、図５に示すような中継ぎ用の層間配
線部材４Ａ，５Ａなどを準備する。この層間配線部材４
Ａ，５Ａにはその主要部が絶縁材料４，５から構成され
る、例えば、ガラス布基材エポキシ樹脂銅張積層板（Ｆ
Ｒ−４）などの両面銅箔基板を図５に示す長四角状に切
断したものが使用される。この絶縁材料４，５の芯部に
は他の回路基板への信号出力線や、他の回路基板からの
信号入力線、その他電源線、接地線などを構成するスル
ーホール１５Ａ，１６Ａなどが設けられ、その両面（内
外面）にはシールド用に銅箔（導電部材）１７が形成さ
れ、内層配線基板２のシールドパターン６Ａ，６Ｂと共
に接地される。スルーホール１５Ａ，１６Ａは周知の方
法で形成される。スルーホール１５Ａ，１６Ａは中空管
状に形成される他に銀などの導体により充填される場合
もある。Next, the interlayer wiring members 4A and 5A for the relay as shown in FIG. 5 are prepared. This interlayer wiring member 4
A and 5A are mainly composed of insulating materials 4 and 5, for example, a glass cloth base epoxy resin copper-clad laminate (F).
A substrate obtained by cutting a double-sided copper foil substrate such as R-4) into a rectangular shape shown in FIG. 5 is used. Through holes 15A and 16A forming signal output lines to other circuit boards, signal input lines from other circuit boards, other power lines, ground lines, and the like are provided in the cores of the insulating materials 4 and 5. A copper foil (conductive member) 17 is formed on both sides (inner and outer surfaces) for shielding, and grounded together with the shield patterns 6A and 6B of the inner layer wiring board 2. The through holes 15A and 16A are formed by a known method. The through holes 15A and 16A may be filled with a conductor such as silver in addition to being formed in a hollow tubular shape.
【００３０】この銅箔１７は層間配線部材４Ａ、５Ａの
両面に設けられたもの、又は、これらの片面のみに設け
られたものでもよい。内側面に銅箔を設けた（残した）
場合には、シールドパターン６Ａ，６Ｂと共に、ＬＳＩ
チップ３Ａなどを立体的（三次元的）に効率良く電磁シ
ールドすることができ、両面に銅箔を設けた（残した）
場合には、ＬＳＩチップ３Ａなどの電磁シールド効果と
共に、芯部を通る信号出力線や信号入力線の電磁シール
ド効果とを併せて得ることができる。なお、層間配線部
材４Ｂ，５Ｂについては層間配線部材４Ａ，５Ａと同様
な構成を採るのでその説明を省略する。The copper foil 17 may be provided on both surfaces of the interlayer wiring members 4A, 5A, or may be provided on only one surface thereof. Copper foil was provided on the inner surface (remained)
In this case, the LSI is used together with the shield patterns 6A and 6B.
The chip 3A and the like can be three-dimensionally (three-dimensionally) efficiently electromagnetically shielded, and copper foils are provided on both sides (remaining).
In this case, the electromagnetic shielding effect of the signal output line and the signal input line passing through the core can be obtained together with the electromagnetic shielding effect of the LSI chip 3A and the like. The interlayer wiring members 4B and 5B have the same configuration as that of the interlayer wiring members 4A and 5A, and thus the description thereof is omitted.
【００３１】その後、図６に示すように、ＬＳＩ実装基
板１Ａ、層間配線部材４Ａ，５Ａ、内層配線基板２、層
間配線部材４Ｂ，５Ｂ、ＬＳＩ実装基板１Ｂを位置合わ
せして積層する。この際に、ＬＳＩチップ３Ａがシール
ドパターン６Ａ面に対向し、ＬＳＩチップ３Ｂがシール
ドパターン６Ｂ面に対向するようにＬＳＩ実装基板１
Ａ、内層配線基板２及びＬＳＩ実装基板１Ｂを位置合わ
せする。そして、ＬＳＩ実装基板１Ａと内層配線基板２
との間に中継ぎ用の層間配線部材４Ａ，５Ａを挟み込む
と共に、内層配線基板２とＬＳＩ実装基板１Ｂとの間に
中継ぎ用の層間配線部材４Ｂ，５Ｂを挟み込む。この状
態で、ＬＳＩ実装基板１Ａと内層配線基板２とを層間配
線部材４Ａ，５Ａにより電気的かつ構造的に接合し、内
層配線基板２とＬＳＩ実装基板１Ｂとを層間配線部材４
Ｂ，５Ｂにより接着剤を介在して電気的かつ構造的に接
合する。この接合に関しては各部材間に熱溶融性の接着
剤を介在させ、同一の加圧熱処理工程によって行われ
る。After that, as shown in FIG. 6, the LSI mounting board 1A, the interlayer wiring members 4A and 5A, the inner wiring board 2, the interlayer wiring members 4B and 5B, and the LSI mounting board 1B are aligned and laminated. At this time, the LSI mounting board 1 is placed such that the LSI chip 3A faces the shield pattern 6A surface and the LSI chip 3B faces the shield pattern 6B surface.
A, the inner wiring board 2 and the LSI mounting board 1B are aligned. Then, the LSI mounting board 1A and the inner wiring board 2
And the intermediate wiring members 4A and 5A are interposed between the inner wiring substrate 2 and the LSI mounting substrate 1B. In this state, the LSI mounting board 1A and the inner wiring board 2 are electrically and structurally joined to each other by the interlayer wiring members 4A and 5A, and the inner wiring board 2 and the LSI mounting board 1B are connected to each other.
B and 5B electrically and structurally join via an adhesive. This joining is performed by the same pressure heat treatment step with a hot-melt adhesive interposed between the members.
【００３２】例えば、異方性導電樹脂を各々の部材間に
塗布し、ＬＳＩ実装基板１Ａ、層間配線部材４Ａ，５
Ａ、内層配線基板２、層間配線部材４Ｂ，５Ｂ、ＬＳＩ
実装基板１Ｂから成る積層物を１７０°Ｃ程度で加圧加
熱する。これにより、樹脂内に存在する金属粒子がつぶ
れて電気的に基板間が接続されると共に、各々の部材間
が熱接合され、図１に示した電子部品実装多層基板１０
０を形成することができる。しかも、シールド付きのＬ
ＳＩチップ３Ａ，３Ｂの実装面積を積層方向に立体的に
増加させることができ、ＬＳＩチップ３Ａ，３Ｂを平面
に並べてシールド実装する場合に比べて、シールド付き
のＬＳＩチップ３Ａ，３Ｂを高密度に実装することがで
きる。また、はんだ付けによる接続も可能である。For example, an anisotropic conductive resin is applied between each member, and the LSI mounting board 1A, the interlayer wiring members 4A and 5A
A, inner layer wiring board 2, interlayer wiring members 4B, 5B, LSI
The laminate composed of the mounting substrate 1B is heated under pressure at about 170 ° C. As a result, the metal particles existing in the resin are crushed to electrically connect the substrates, and the respective members are thermally joined together, so that the electronic component mounting multilayer substrate 10 shown in FIG.
0 can be formed. And L with shield
The mounting area of the SI chips 3A and 3B can be increased three-dimensionally in the laminating direction, so that the shielded LSI chips 3A and 3B can be formed at a higher density than when the LSI chips 3A and 3B are arranged side by side and shielded. Can be implemented. Also, connection by soldering is possible.
【００３３】このようにして得られた電子部品実装多層
基板１００の外面の銅箔に更にエッチングを施して、プ
リント配線パターンを形成して外部回路を構成し、その
外部回路上に抵抗や、コンデンサなどの部品を更に実装
する。この例では、より多くの電子部品を搭載すること
ができると共に、プリント基板の小型化を図ることがで
きる。The copper foil on the outer surface of the electronic component-mounted multilayer board 100 thus obtained is further etched to form a printed wiring pattern to form an external circuit, and a resistor or a capacitor is formed on the external circuit. And other components. In this example, more electronic components can be mounted, and the size of the printed circuit board can be reduced.
【００３４】本発明者らが基板面積をシュミレーション
した結果によれば、実装基板上に平面に５個のＬＳＩチ
ップを表面実装する場合（マルチチップ実装、現行のＣ
ＳＰ；Ｃhip Ｓize Ｐackage：従来方式）に比べて、５
個のＬＳＩチップを基板内に内蔵する本発明方式では、
従来方式の４０〜５０％の小型化が図れることが明確に
なった。従って、当該電子部品実装多層基板１００を適
用した電子機器の小型化を図ることができる。According to the results of the simulation of the substrate area by the present inventors, when five LSI chips are surface-mounted on a mounting substrate on a plane (multi-chip mounting, the current C
SP; Chip Size Package: Conventional method)
In the method of the present invention in which LSI chips are built in a substrate,
It has been clarified that the size can be reduced by 40 to 50% of the conventional system. Therefore, downsizing of an electronic device to which the electronic component mounting multilayer substrate 100 is applied can be achieved.
【００３５】（実施例）図７〜図１１は実施例としての
層間配線部材の構成例を示すイメージ図である。図７〜
図９に示す例では、層間配線部材などの主要部が絶縁材
料から構成される場合であって、その絶縁材料の内面
側、芯部又は外面側に導電部材が設けられ、この導電部
材が接地されるものである。(Embodiment) FIGS. 7 to 11 are image diagrams showing a configuration example of an interlayer wiring member as an embodiment. FIG.
In the example shown in FIG. 9, a main part such as an interlayer wiring member is made of an insulating material, and a conductive member is provided on the inner surface, the core or the outer surface of the insulating material. Is what is done.
【００３６】図７Ａに示す層間配線部材４１の例では、
図５に示した層間配線部材４Ａに関して、その絶縁材料
４の両面から銅箔を除いたものである。従って、層間配
線部材４１のシールド効果に関しては、信号線や電源線
に使用されないスルーホール１５Ａを並列に接続して接
地することにより、電磁シールドを得るものである。こ
の絶縁材料４を取り除いて考えた場合に、接地されたス
ルーホール１５Ａが格子状に配置されることになり、Ｌ
ＳＩチップ３Ａ，３Ｂの側面などを電磁シールドするよ
うな効果が得られる。In the example of the interlayer wiring member 41 shown in FIG.
In the interlayer wiring member 4A shown in FIG. 5, the copper foil is removed from both surfaces of the insulating material 4. Accordingly, regarding the shielding effect of the interlayer wiring member 41, an electromagnetic shield is obtained by connecting the through holes 15A, which are not used for signal lines and power lines, in parallel and grounding them. When this insulating material 4 is removed, the grounded through-holes 15A are arranged in a grid pattern.
An effect of electromagnetically shielding the side surfaces of the SI chips 3A and 3B can be obtained.
【００３７】図７Ｂに示す層間配線部材４２の例では、
図７Ａに示した層間配線部材４１のスルーホール１５Ａ
の位置を左右に分離して配置したものである。スルーホ
ール１５Ａの断面積は１／２になるが、設置数が２倍に
なる。従って、余裕を持って信号線や電源線とシールド
用の格子部分とを完全に分離することができる。この際
のシールド効果に関しては、シールド用の格子部分のス
ルーホール１５Ｃを並列に接続して接地することによ
り、広範囲な電磁シールドを得ることができる。In the example of the interlayer wiring member 42 shown in FIG. 7B,
Through hole 15A of interlayer wiring member 41 shown in FIG. 7A
Are separated from each other on the left and right. Although the cross-sectional area of the through-hole 15A is halved, the number of installations is doubled. Therefore, it is possible to completely separate the signal line and the power supply line from the shielding grid portion with a margin. Regarding the shielding effect at this time, a wide range of electromagnetic shielding can be obtained by connecting the through holes 15C of the shielding grid portion in parallel and grounding.
【００３８】図７Ｃに示す層間配線部材４３の例では、
図５に示した層間配線部材４Ａの芯部から信号線用のス
ルーホールを取り除き、両面の導電部材によって信号線
用のプリント配線パターン１８や、シールドパターン１
９を形成したものである。層間配線部材４３の芯部には
例えば電源線や接地線が設けられる。従って、図７Ｂに
示した層間配線部材４２と同様にして信号線や電源線と
シールドパターン１９とを完全に分離することができ
る。もちろん、層間配線部材４３の左右のいずれか一方
がシールド面と始めから明確になされている場合には、
銅箔をそのまま残して置いてもよい。シールド面が左右
のどちらに位置するかが明確でない場合には、プリント
配線パターン１８として銅箔を加工して置き、シールド
面が決定したところで、シールド面側の配線パターン１
８を並列に接続して接地し、それをシールドパターン１
９として使用すればよい。In the example of the interlayer wiring member 43 shown in FIG.
The through hole for the signal line is removed from the core of the interlayer wiring member 4A shown in FIG. 5, and the printed wiring pattern 18 for the signal line and the shield pattern 1 are formed by the conductive members on both surfaces.
9 is formed. For example, a power supply line and a ground line are provided at the core of the interlayer wiring member 43. Therefore, signal lines and power supply lines and the shield pattern 19 can be completely separated in the same manner as the interlayer wiring member 42 shown in FIG. 7B. Of course, if one of the left and right sides of the interlayer wiring member 43 is clearly defined as the shield surface from the beginning,
The copper foil may be left as it is. If it is not clear whether the shield surface is located on the left or right, a copper foil is processed and placed as the printed wiring pattern 18, and when the shield surface is determined, the wiring pattern 1 on the shield surface side is determined.
8 in parallel and ground, and connect it to shield pattern 1
9 may be used.
【００３９】図８に示す層間配線部材４４の例では、層
間配線部材自身が枠型を有しており、その主要部が絶縁
材料４から構成される場合であって、その絶縁材料４の
芯部に複数のスルーホール（導電部材）１５Ａが設けら
れ、そのスルーホール１５Ａの一部が並列に接続されて
接地されるものである。すべてのスルーホール１５Ａを
並列に接続した場合には、電子部品を包囲するような駕
篭状のシールド壁を構成することができる。通常はスル
ーホール１５Ａの一部は信号線や電源線に使用される。
もちろん、この枠型の層間配線部材４４の内側面及び外
側面に導電部材を設け、この導電部材をシールドパター
ン１９として使用してもよい。電子部品を包囲するよう
なシールド壁が形成され、同様なシールド効果が得られ
る。In the example of the interlayer wiring member 44 shown in FIG. 8, the interlayer wiring member itself has a frame shape, and its main part is made of the insulating material 4. A plurality of through holes (conductive members) 15A are provided in the portion, and a part of the through holes 15A is connected in parallel and grounded. When all the through holes 15A are connected in parallel, a girder-shaped shield wall surrounding the electronic component can be formed. Normally, a part of the through hole 15A is used for a signal line or a power supply line.
Of course, a conductive member may be provided on the inner and outer surfaces of the frame-type interlayer wiring member 44, and the conductive member may be used as the shield pattern 19. A shield wall surrounding the electronic component is formed, and a similar shielding effect can be obtained.
【００４０】図９に示す層間配線部材４５の例では、層
間配線部材自身が「コ」字状を有しており、図８に示し
た枠型の層間配線部材４４の一辺の枠部を取り除いたも
のである。コ字状の層間配線部材４５は例えば回路基板
端部で使用するとよい。これは発熱性の高いＬＳＩチッ
プなどを実装する場合に、回路基板端部に開放部が向く
ようにコ字状の層間配線部材４５を配置することによ
り、その開放部を放熱窓として利用することができる。
絶縁材料５の芯部には枠型の層間配線部材４４と同様に
して、複数のスルーホール１５Ａが設けられ、そのスル
ーホール１５Ａの一部が並列に接続されて接地されるも
のである。In the example of the interlayer wiring member 45 shown in FIG. 9, the interlayer wiring member itself has a U-shape, and the frame portion on one side of the frame type interlayer wiring member 44 shown in FIG. It is a thing. The U-shaped interlayer wiring member 45 may be used, for example, at the end of the circuit board. This is because, when mounting a highly heat-generating LSI chip or the like, the U-shaped interlayer wiring member 45 is arranged so that the open part faces the end of the circuit board, and the open part is used as a heat radiation window. Can be.
A plurality of through holes 15A are provided in the core of the insulating material 5 in the same manner as the frame-type interlayer wiring member 44, and some of the through holes 15A are connected in parallel and grounded.
【００４１】すべてのスルーホール１５Ａを並列に接続
した場合には、電子部品をコ字状に包囲するような一辺
開放型のシールド壁を構成することができる。もちろ
ん、この例でも、コ字状の層間配線部材４５の内側面及
び外側面に導電部材を設け、この導電部材をシールドパ
ターン１９として使用してもよい。電子部品をコ字状に
包囲するようなシールド壁が形成され、同様なシールド
効果が得られる。When all the through holes 15A are connected in parallel, it is possible to form a one-side open shield wall that surrounds the electronic components in a U-shape. Of course, also in this example, a conductive member may be provided on the inner surface and the outer surface of the U-shaped interlayer wiring member 45, and this conductive member may be used as the shield pattern 19. A shield wall surrounding the electronic component in a U-shape is formed, and a similar shielding effect can be obtained.
【００４２】このように、簡単なプロセスでシールド効
果を得ることができる。特に、３次元的にＬＳＩチップ
３Ａ，３Ｂを実装する際に、層間配線部材４１〜４５の
スルーホール１５Ａにより、電磁シールドをすることが
できる。As described above, the shielding effect can be obtained by a simple process. In particular, when the LSI chips 3A and 3B are mounted three-dimensionally, electromagnetic shielding can be provided by the through holes 15A of the interlayer wiring members 41 to 45.
【００４３】図１０及び図１１に示す例では、層間配線
部材が導電材料から構成される場合であって、その導電
材料が柱状又は球状を有している。もちろん、導電材料
は円錐状、円柱状、壁状を有していてもよい。図１０に
示す層間配線部材４６の例では、中空円柱状の４個の銅
パイプ４６Ａ〜４６Ｄにより導電性の層間配線部材が構
成される。この層間配線部材４６は、例えば、ＬＳＩ実
装基板１Ａと内層回路基板２との間において、当該基板
の四隅に配置される。主に、電源線や、クロック信号な
どの供給経路としての機能及び、実装基板の躯体を支え
るために使用される。銅パイプ４６Ａ〜４６Ｄの配置は
四隅に限られることはなく、回路基板に撓みが生じなけ
れば三隅でも、また、広い面積の回路基板同士を多層す
る場合には、躯体応力集中部分や、信号線の入出力位置
に基づいて銅パイプ４６Ａ〜４６Ｄを配置するとよい。
パイプの材質は銅に限定されることはなく、抵抗の少な
い青銅、銀や金、これらの合金でもよい。In the example shown in FIGS. 10 and 11, the interlayer wiring member is made of a conductive material, and the conductive material has a columnar or spherical shape. Of course, the conductive material may have a conical shape, a cylindrical shape, or a wall shape. In the example of the interlayer wiring member 46 shown in FIG. 10, a conductive interlayer wiring member is formed by four hollow cylindrical copper pipes 46A to 46D. The interlayer wiring members 46 are arranged, for example, between the LSI mounting board 1A and the inner circuit board 2 at the four corners of the board. It is mainly used to function as a power supply line, a supply path for clock signals, and the like, and to support the frame of the mounting board. The arrangement of the copper pipes 46A to 46D is not limited to the four corners, and is not limited to the three corners unless the circuit board is bent. The copper pipes 46A to 46D may be arranged on the basis of the input / output positions.
The material of the pipe is not limited to copper, but may be bronze, silver, gold, or an alloy thereof having low resistance.
【００４４】図１１に示す層間配線部材４７の例では、
４個の球状のハンダボール４７Ａ〜４７Ｄにより導電性
の層間配線部材が構成される。この層間配線部材４７
は、例えば、ＬＳＩ実装基板１Ａと内層回路基板２との
間において、図１０で説明したように当該基板の四隅に
配置される。その機能は上述の銅パイプ４６Ａ〜４６Ｄ
と同じである。In the example of the interlayer wiring member 47 shown in FIG.
The four spherical solder balls 47A to 47D form a conductive interlayer wiring member. This interlayer wiring member 47
Are arranged, for example, between the LSI mounting board 1A and the inner layer circuit board 2 at the four corners of the board as described with reference to FIG. Its function is the above copper pipe 46A-46D
Is the same as
【００４５】ハンダボール４７Ａ〜４７Ｄの形成位置は
四隅に限られることはなく、回路基板に撓みが生じなけ
ればラウンド電極に整合させた三隅でも、また、広い面
積の回路基板を多層する場合には、躯体応力集中部分
や、信号線の入出力位置に基づいてハンダボール４７Ａ
〜４７Ｄを配置するとよい。なお、図１０及び図１１に
示した層間配線部材４６，４７の例で、シールド効果を
得るためには、銅パイプ４６Ａ〜４６Ｄやハンダボール
４７Ａ〜４７Ｄを電子部品の周囲に並べて配置し、これ
を電気的に接続して接地すればよい。The positions at which the solder balls 47A to 47D are formed are not limited to the four corners. If the circuit board does not bend, the solder balls 47A to 47D may be formed at the three corners aligned with the round electrodes. Solder ball 47A based on the skeleton stress concentration portion and the input / output position of the signal line.
~ 47D may be arranged. In the example of the interlayer wiring members 46 and 47 shown in FIGS. 10 and 11, in order to obtain a shielding effect, copper pipes 46A to 46D and solder balls 47A to 47D are arranged side by side around the electronic component. May be electrically connected to ground.
【００４６】（２）第２の実施形態 図１２は本発明に係る第２の実施形態としての電子部品
実装多層基板２００の構成例を示す断面図である。この
実施形態に係る電子部品実装多層基板２００は、層間配
線部材がＬＳＩ実装基板と一体化された凹状のキャビテ
ィ構造を有している。このキャビティ構造とは電子部品
収納用の溝部又は穴部をいう。この例でも、内層配線基
板２にはシールドパターン６Ａ，６Ｂが設けられ、シー
ルド付きのＬＳＩチップ３Ａ，３Ｂの実装面積を積層方
向に立体的に増加できるようにしたものである。(2) Second Embodiment FIG. 12 is a cross-sectional view showing a configuration example of an electronic component mounting multilayer substrate 200 as a second embodiment according to the present invention. The electronic component mounting multilayer board 200 according to this embodiment has a concave cavity structure in which an interlayer wiring member is integrated with an LSI mounting board. The cavity structure refers to a groove or a hole for storing an electronic component. Also in this example, the inner layer wiring board 2 is provided with the shield patterns 6A and 6B so that the mounting area of the shielded LSI chips 3A and 3B can be three-dimensionally increased in the stacking direction.
【００４７】図１２に示す電子部品実装多層基板２００
は、ＬＳＩチップ３Ａ，３Ｂなどの電子部品を高密度に
実装したものである。図１２に示す例では、キャビティ
構造のＬＳＩ実装基板２１にＬＳＩチップ３Ａ，３Ｂが
実装され、このＬＳＩ実装基板２１が内層配線基板２の
一方の面に積層されると共に、ＬＳＩ実装基板２１及び
内層配線基板２が電気的に接合され、しかも、その内層
配線基板２の他方の面に、ハンダボール（球状の層間配
線部材）２３Ａ，２３Ｂを挟んで他のＬＳＩ実装基板１
Ｂなどが積層されると共に、ＬＳＩ実装基板１Ｂ及び内
層配線基板２との間がそのハンダボール２３Ａ，２３Ｂ
により電気的に接合された多層構造を成している。Electronic component mounting multilayer board 200 shown in FIG.
Is a device in which electronic components such as LSI chips 3A and 3B are mounted at high density. In the example shown in FIG. 12, the LSI chips 3A and 3B are mounted on the LSI mounting board 21 having a cavity structure, and the LSI mounting board 21 is laminated on one surface of the inner wiring board 2, and the LSI mounting board 21 and the inner The wiring board 2 is electrically joined, and the other LSI mounting board 1 is placed on the other surface of the inner wiring board 2 with solder balls (spherical interlayer wiring members) 23A and 23B interposed therebetween.
B and the like and the solder balls 23A and 23B are provided between the LSI mounting board 1B and the inner wiring board 2.
To form a multi-layered structure electrically connected to each other.
【００４８】この例では、ＬＳＩ実装基板２１は凹状に
突起したキャビティ部２２を有しており、第１の実施形
態で説明した中継ぎ用の層間配線部材４Ａ，４Ｂなどの
機能を備えたものである。キャビティ部２２は、少なく
とも、ＬＳＩ実装基板２１や内層配線基板２を支える躯
体としての性質と、信号などを伝搬する信号線路と、Ｌ
ＳＩチップ３Ａや信号線などをシールドする遮蔽壁とし
ての３つの機能を有している。In this example, the LSI mounting substrate 21 has a cavity portion 22 projecting in a concave shape, and has the functions of the interlayer wiring members 4A and 4B for the relay described in the first embodiment. is there. The cavity portion 22 has at least properties as a frame supporting the LSI mounting board 21 and the inner wiring board 2, a signal line for transmitting signals and the like,
It has three functions as a shielding wall that shields the SI chip 3A, signal lines, and the like.
【００４９】この例でもキャビティ部２２によって画定
される領域内であって、ＬＳＩチップ３Ａに対向する側
の内層配線基板２の一方の面には第１の実施形態で説明
したようなシールドパターン６Ａが設けられ、更に、ハ
ンダボール２３Ａ，２３Ｂによって画定される領域内で
あって、ＬＳＩチップ３Ｂに対向する側の内層配線基板
２の他方の面にも、所定の広さの銅箔から成るシールド
パターン６Ｂが設けられる。これらのシールドパターン
６Ａ，６Ｂが接地される。従って、ＬＳＩ実装基板２１
のキャビティ部２２のＬＳＩチップ３Ａを内層配線基板
２の上面のシールドパターン６Ａにより電磁シールドす
ることができ、同様にして、ＬＳＩ実装基板１Ｂ上のＬ
ＳＩチップ３Ｂを内層配線基板２の下面のシールドパタ
ーン６Ｂにより電磁シールドすることができる。Also in this example, the shield pattern 6A as described in the first embodiment is provided on one surface of the inner wiring substrate 2 in the area defined by the cavity portion 22 and on the side facing the LSI chip 3A. And a shield made of copper foil of a predetermined size is also provided in the area defined by the solder balls 23A and 23B and on the other surface of the inner layer wiring board 2 on the side facing the LSI chip 3B. A pattern 6B is provided. These shield patterns 6A and 6B are grounded. Therefore, the LSI mounting board 21
Of the cavity 22 can be electromagnetically shielded by the shield pattern 6A on the upper surface of the inner layer wiring board 2, and similarly, the LSI chip 3A on the LSI mounting board 1B can be shielded.
The SI chip 3B can be electromagnetically shielded by the shield pattern 6B on the lower surface of the inner wiring board 2.
【００５０】このように、第２の実施形態としての電子
部品実装多層基板２００によれば、層間配線部材の機能
を有した凹状のキャビティ構造のＬＳＩ実装基板２１に
ＬＳＩチップ３Ａが実装され、このＬＳＩ実装基板２１
が内層配線基板２の一方の面に積層されると共に、ＬＳ
Ｉ実装基板２１及び内層配線基板２が電気的に接合され
る。しかも、内層配線基板２の所定の位置にはシールド
パターン６Ａが設けられ、その内層配線基板２の他方の
面に、ハンダボール２３Ａ，２３Ｂを挟んで他のＬＳＩ
実装基板１Ｂが積層されると共に、ＬＳＩ実装基板１Ｂ
及び内層配線基板２との間がそのハンダボール２３Ａ，
２３Ｂにより電気的に接合された多層構造を成してい
る。As described above, according to the electronic component mounting multilayer board 200 of the second embodiment, the LSI chip 3A is mounted on the LSI mounting board 21 having a concave cavity structure having the function of an interlayer wiring member. LSI mounting board 21
Are laminated on one surface of the inner wiring board 2 and LS
The I mounting board 21 and the inner wiring board 2 are electrically connected. In addition, a shield pattern 6A is provided at a predetermined position of the inner wiring board 2, and another LSI is provided on the other surface of the inner wiring board 2 with the solder balls 23A and 23B interposed therebetween.
The mounting substrate 1B is laminated and the LSI mounting substrate 1B
Between the solder ball 23A and the inner wiring board 2;
23B form a multilayer structure electrically connected.
【００５１】従って、ＬＳＩ実装基板２１やＬＳＩ実装
基板１Ｂなどの基板同士の接続を複合的に行うことがで
き、しかも、第１の実施形態のような層間配線部材の積
層処理を同時加圧熱接合工程から分離することができ
る。また、第１の実施形態と同様にして所定の広さのシ
ールドパターン６Ａ，６Ｂによって電気的にシールドさ
れたＬＳＩチップ３Ａ，３Ｂの実装面積を積層方向に立
体的に増加させることができ、ＬＳＩチップ３Ａ，３Ｂ
を平面に並べてシールド実装する場合に比べて、シール
ド付きのＬＳＩチップ３Ａ，３Ｂを高密度に実装するこ
とができる。これにより、当該電子部品実装層基板２０
０を適用した電子機器の小型化を図ることができる。Accordingly, the connection between the substrates such as the LSI mounting substrate 21 and the LSI mounting substrate 1B can be performed in a complex manner. It can be separated from the joining process. Further, similarly to the first embodiment, the mounting area of the LSI chips 3A and 3B electrically shielded by the shield patterns 6A and 6B of a predetermined size can be three-dimensionally increased in the stacking direction. Chip 3A, 3B
, The shielded LSI chips 3A and 3B can be mounted at a higher density than when the chips are arranged in a plane and shielded. Thereby, the electronic component mounting layer substrate 20
0 can be downsized.
【００５２】続いて、電子部品実装多層基板２００の製
造方法について説明をする。図１３及び図１４は電子部
品実装多層基板２００の形成例（その１、２）を示す工
程図である。この例では、第１の実施形態で説明したよ
うなＬＳＩ実装基板１Ｂ及び内層配線基板２が既に準備
されていることを想定する。ＬＳＩ実装基板２１やＬＳ
Ｉ実装基板１Ｂなどの基板同士の接続は複合的に行わ
れ、しかも、第１の実施形態のような層間配線部材の積
層処理を同時加圧熱接合工程から分離するようになされ
る。Next, a method for manufacturing the electronic component mounting multilayer board 200 will be described. FIGS. 13 and 14 are process diagrams showing examples of forming the electronic component-mounted multilayer board 200 (Nos. 1 and 2). In this example, it is assumed that the LSI mounting board 1B and the inner wiring board 2 as described in the first embodiment are already prepared. LSI mounting board 21 or LS
The connection between the substrates such as the I-mount substrate 1B is performed in a complex manner, and the lamination processing of the interlayer wiring member as in the first embodiment is separated from the simultaneous pressing and heat bonding step.
【００５３】これを前提として、まず、図１３Ａに示す
キャビティ構造のＬＳＩ実装基板２１を形成する。この
ＬＳＩ実装基板２１は第１の実施形態で説明したＬＳＩ
実装基板１のように、予め両面銅箔基板を加工して所定
のプリント配線パターンや電極（ラウンド）などを形成
し、その後、例えば、その実装基板１にキャビティ部２
２を立ち上げるものである。キャビティ部２２は第１の
実施形態で説明した層間配線部材４Ａ，５Ａを利用する
ことができる。On the premise of this, first, an LSI mounting substrate 21 having a cavity structure shown in FIG. 13A is formed. This LSI mounting board 21 is the LSI described in the first embodiment.
Like the mounting substrate 1, a double-sided copper foil substrate is processed in advance to form a predetermined printed wiring pattern, an electrode (round), and the like.
2 is launched. The cavity portion 22 can use the interlayer wiring members 4A and 5A described in the first embodiment.
【００５４】例えば、図５に示したような中継ぎ用の層
間配線部材４Ａ，５Ａを最初に実装基板１に接合し固定
する。この際の固定方法は、加圧熱接着により行う。こ
のキャビティ部２２（層間配線部材４Ａ，４Ｂ）の芯部
には他の回路基板への信号出力線や、他の回路基板から
の信号入力線、その他電源線、接地線などを構成するス
ルーホール１５Ａ，１６Ａなどが設けられる。もちろ
ん、その両面（内外面）にシールド用に銅箔（導電部
材）を設けて、内層配線基板２のシールドパターン６
Ａ，６Ｂと共に接地し、電磁シールド効果を得るように
してもしてもよい。For example, the interlayer wiring members 4A and 5A for the relay as shown in FIG. 5 are first joined to the mounting substrate 1 and fixed. The fixing method at this time is performed by pressure heat bonding. Through holes forming signal output lines to other circuit boards, signal input lines from other circuit boards, other power supply lines, ground lines, and the like are provided in the cores of the cavities 22 (interlayer wiring members 4A and 4B). 15A, 16A and the like are provided. Of course, copper foil (conductive member) is provided on both sides (inner and outer surfaces) for shielding, and the shield pattern 6 of the inner layer wiring board 2 is provided.
A and 6B may be grounded to obtain an electromagnetic shielding effect.
【００５５】その後、図１３Ｂに示す実装基板１の凹状
部にＬＳＩチップ３Ａを実装してキャビティ構造のＬＳ
Ｉ実装基板２１を形成する。例えば、ＬＳＩチップ３Ａ
がフリップチップの場合に、予め形成された複数のパッ
ド電極などにバンプ電極を介在してＬＳＩチップ３Ａを
接合する。ＬＳＩチップ３Ａはフリップチップに限定さ
れることはなく、ワイヤーボンディングによる接合方法
でもよい。Thereafter, the LSI chip 3A is mounted on the concave portion of the mounting substrate 1 shown in FIG.
An I-mount substrate 21 is formed. For example, LSI chip 3A
Is a flip chip, the LSI chip 3A is bonded to a plurality of pad electrodes formed in advance via bump electrodes. The LSI chip 3A is not limited to a flip chip, but may be a bonding method using wire bonding.
【００５６】この例でも、ＬＳＩ実装基板２１から動作
検査用の電極が引き出される。この動作検査用の電極に
はキャビティ部２２の芯部に設けられたスルーホール１
５Ａ，１６Ａが兼用される。このスルーホール１５Ａ，
１６Ａは動作検査時に試験電圧を印可したり、テストデ
ータを供給したり、その結果データを引き出すために使
用される。専用のテスト端子を設けなくても済む。Also in this example, electrodes for operation inspection are pulled out from the LSI mounting board 21. This operation test electrode has a through hole 1 provided in the core of the cavity 22.
5A and 16A are also used. This through hole 15A,
16A is used for applying a test voltage during operation inspection, supplying test data, and extracting data as a result. There is no need to provide a dedicated test terminal.
【００５７】上述のキャビティ構造のＬＳＩ実装基板２
１が形成できたら、図４に示したＬＳＩテスタ１０など
によりＬＳＩ実装基板２１毎に電気的な検査を行う。例
えば、キャビティ部２２の芯部に設けられた複数のスル
ーホール１５Ａ，１６Ａに、図示しないＬＳＩテスタ１
０のプローブ１３，１４が一斉に接触され、キャビティ
部２２のスルーホール１５Ａ，１６Ａを含めた実装試験
が行われる。LSI mounting board 2 having the above cavity structure
When 1 is formed, an electrical test is performed for each LSI mounting board 21 by the LSI tester 10 shown in FIG. For example, a plurality of through holes 15A and 16A provided in a core portion of the cavity portion 22 are provided with an LSI tester 1 (not shown).
The probes 13 and 14 of 0 are simultaneously contacted, and a mounting test including the through holes 15A and 16A of the cavity 22 is performed.
【００５８】従って、キャビティ構造のＬＳＩ実装基板
２１を内層配線基板２や、他のＬＳＩ実装基板１Ｂに積
層する前に、ＬＳＩ実装基板２１の不良を早期に除去す
ることができる。この検査結果で良品と判定されたＬＳ
Ｉ実装基板２１や内層配線基板２のみを積層することが
できる。キャビティ構造のＬＳＩ実装基板２１や内層配
線基板２を全部積層した後に電気的な検査を行う場合に
比べて、当該電子部品実装多層基板２００の生産歩留ま
りを向上させることができる。Therefore, before stacking the LSI mounting board 21 having the cavity structure on the inner wiring board 2 or another LSI mounting board 1B, it is possible to remove defects of the LSI mounting board 21 at an early stage. LS determined to be non-defective by this inspection result
Only the I mounting board 21 and the inner wiring board 2 can be stacked. The production yield of the electronic component-mounted multilayer substrate 200 can be improved as compared with the case where an electrical inspection is performed after the LSI mounting substrate 21 and the inner wiring substrate 2 having the cavity structure are all stacked.
【００５９】その後、図１４に示すように、キャビティ
構造のＬＳＩ実装基板２１と、内層配線基板２と、ＬＳ
Ｉ実装基板１Ｂとを位置合わせして積層する。この際
に、ＬＳＩチップ３Ａがシールドパターン６Ａ面に対向
し、ＬＳＩチップ３Ｂがシールドパターン６Ｂ面に対向
するようにＬＳＩ実装基板２１、内層配線基板２及びＬ
ＳＩ実装基板１Ｂを位置合わせする。そして、ＬＳＩ実
装基板２１と内層配線基板２との間に図示しないハンダ
ペーストを塗布すると共に、ＬＳＩ実装基板１Ｂと内層
配線基板２との間にハンダボール２３Ａ，２３Ｂを挟み
込む。この状態で、ＬＳＩ実装基板２１と内層配線基板
２とをハンダペーストにより電気的かつ構造的に接合
し、内層配線基板２とＬＳＩ実装基板１Ｂとをハンダボ
ール２３Ａ，２３Ｂにより電気的かつ構造的に接合す
る。この接合に関しては同一の加圧熱処理工程によって
行われる。Thereafter, as shown in FIG. 14, the LSI mounting board 21 having the cavity structure, the inner wiring board 2 and the LS
The I-mount substrate 1B is aligned and laminated. At this time, the LSI mounting board 21, the inner layer wiring board 2, and the L-layer are arranged such that the LSI chip 3A faces the shield pattern 6A surface and the LSI chip 3B faces the shield pattern 6B surface.
The SI mounting board 1B is aligned. Then, a solder paste (not shown) is applied between the LSI mounting board 21 and the inner wiring board 2, and the solder balls 23A and 23B are sandwiched between the LSI mounting board 1B and the inner wiring board 2. In this state, the LSI mounting board 21 and the inner wiring board 2 are electrically and structurally joined by solder paste, and the inner wiring board 2 and the LSI mounting board 1B are electrically and structurally connected by the solder balls 23A and 23B. Join. This bonding is performed by the same pressure heat treatment process.
【００６０】例えば、キャビティ構造のＬＳＩ実装基板
２１、内層配線基板２及びＬＳＩ実装基板１Ｂから成る
積層物をはんだ付けする。これにより、図１２に示した
電子部品実装多層基板２００を形成することができる。
しかも、第１の実施形態と同様にしてシールド付きのＬ
ＳＩチップ３Ａ，３Ｂの実装面積を積層方向に立体的に
増加させることができる。ここで、回路機能を増加すべ
く、ＬＳＩ実装基板２１の積層数を更に増加した場合
に、平面的なサイズを大きくすること無しに、電子部品
実装多層基板２００を構成することができる。このよう
に、ＬＳＩ実装基板２１を任意の数だけ積み上げること
ができるので、実装面積が増え、多機能な電子機器の小
型化を実現できる。For example, a laminate composed of the LSI mounting board 21 having the cavity structure, the inner wiring board 2 and the LSI mounting board 1B is soldered. Thereby, the electronic component mounting multilayer substrate 200 shown in FIG. 12 can be formed.
Moreover, as in the first embodiment, the shielded L
The mounting area of the SI chips 3A and 3B can be three-dimensionally increased in the stacking direction. Here, when the number of stacked LSI mounting boards 21 is further increased in order to increase the circuit function, the electronic component mounting multilayer board 200 can be configured without increasing the planar size. As described above, since an arbitrary number of LSI mounting boards 21 can be stacked, the mounting area increases, and the miniaturization of a multifunctional electronic device can be realized.
【００６１】各々の実施形態では２個のＬＳＩ実装基板
１Ａ，１ＢやＬＳＩ実装基板２１，１Ｂを積層する場合
について説明したが、ＬＳＩ実装基板１Ａ，１ＢやＬＳ
Ｉ実装基板２１，１Ｂの積層数はこれに限定されるもの
ではない。また、ＬＳＩ実装基板１Ａ，１ＢやＬＳＩ実
装基板２１，１ＢにおけるＬＳＩチップ３Ａ，３Ｂの実
装面も片面について説明したが、これに限定されるもの
ではない。もちろん、両面にＬＳＩチップ３Ａ，３Ｂを
実装してもよい。In each embodiment, the case where the two LSI mounting boards 1A and 1B and the LSI mounting boards 21 and 1B are stacked has been described, but the LSI mounting boards 1A and 1B and the LS
The number of laminations of the I mounting boards 21 and 1B is not limited to this. Further, although the mounting surfaces of the LSI chips 3A and 3B in the LSI mounting substrates 1A and 1B and the LSI mounting substrates 21 and 1B have been described on one side, the present invention is not limited to this. Of course, LSI chips 3A and 3B may be mounted on both sides.
【００６２】また、積層工程における各回路基板間の接
続方法については、ハンダペースト及びハンダボール２
３Ａ，２３Ｂを使用する場合について説明したが、これ
に限定されるものではない。広く部品実装で使用されて
いるハンダ付け、ＡＣＦ（Ａnisotropy Ｃonductive Ｆ
ilm）などに代表される接着剤による実装や、銀ペース
ト接着法等による実装も可能である。個別基板毎にＡＣ
Ｆを適用することも可能であり、より容易で安価な電子
部品実装多層基板２００を製造することができる。The method for connecting the circuit boards in the laminating step is described in detail below.
The case where 3A and 23B are used has been described, but the present invention is not limited to this. Soldering, ACF (Anisotropy Conductive F) widely used in component mounting
Mounting using an adhesive typified by ilm) or the like, or mounting using a silver paste bonding method or the like is also possible. AC for each individual board
It is also possible to apply F, and it is possible to manufacture an electronic component mounting multilayer board 200 that is easier and cheaper.
【００６３】[0063]
【発明の効果】以上説明したように、本発明に係る電子
部品実装多層基板によれば、シールド用の導電部材と対
向した電子部品を実装する実装基板が、層間配線部材を
挟んで積層されると共に、その実装基板間が層間配線部
材により電気的に接合された多層構造を成しているもの
である。この構成によって、所定の広さの導電部材によ
ってシールドされた電子部品の実装面積を積層方向に立
体的に増加させることができ、平面に電子部品を並べて
シールド実装する場合に比べて、シールド付きの電子部
品を高密度に実装することができる。As described above, according to the electronic component mounting multilayer board of the present invention, the mounting board for mounting the electronic component facing the conductive member for shielding is laminated with the interlayer wiring member interposed therebetween. At the same time, the mounting boards form a multilayer structure in which the mounting boards are electrically joined by interlayer wiring members. With this configuration, the mounting area of the electronic component shielded by the conductive member having a predetermined size can be three-dimensionally increased in the stacking direction. Electronic components can be mounted at a high density.
【００６４】本発明に係る電子部品実装多層基板の製造
方法によれば、一方の面又は両面に電子部品を実装して
実装基板を形成する共に、その電子部品に対向する側の
他の実装基板に所定の広さのシールド用の導電部材を形
成し、その後、実装基板間に中継ぎ用の層間配線部材を
挟んで積層し、その実装基板間を層間配線部材により電
気的かつ構造的に接合するようになされる。According to the method of manufacturing an electronic component-mounted multilayer substrate according to the present invention, an electronic component is mounted on one or both surfaces to form a mounting substrate, and the other mounting substrate facing the electronic component is mounted. A conductive member for shielding having a predetermined size is formed on the substrate, and thereafter, an interlayer wiring member for relay is sandwiched between the mounting boards, and the mounting substrates are electrically and structurally joined by the interlayer wiring member. It is done as follows.
【００６５】この構成によって、シールド付きの電子部
品の実装面積を積層方向に立体的に増加させることがで
き、平面に電子部品を並べてシールド実装する場合に比
べて、シールド付きの電子部品を高密度に実装すること
ができる。これにより、当該電子部品実装多層基板を適
用した電子機器の小型化を図ることができる。この発明
はＬＳＩや、抵抗、コンデンサなどの電子部品を高密度
実装した、携帯電話機や、携帯用のパーソナルコンピュ
ータなどの携帯端末装置に適用して極めて好適である。According to this configuration, the mounting area of the shielded electronic component can be increased three-dimensionally in the stacking direction, and the electronic component with the shield can be mounted at a higher density than in the case where the electronic component is arranged and shielded on a plane. Can be implemented. This makes it possible to reduce the size of an electronic device to which the electronic component-mounted multilayer board is applied. INDUSTRIAL APPLICABILITY The present invention is extremely suitable for application to a portable terminal device such as a mobile phone or a portable personal computer on which electronic components such as an LSI, a resistor and a capacitor are mounted at a high density.
【図１】第１の実施形態としての電子部品実装多層基板
１００の構造例を示す断面図である。FIG. 1 is a cross-sectional view illustrating a structural example of an electronic component-mounted multilayer substrate 100 according to a first embodiment.
【図２】その電子部品実装多層基板１００の形成例（そ
の１）を示す断面図である。FIG. 2 is a cross-sectional view illustrating an example (part 1) of forming the electronic component-mounted multilayer board 100.
【図３】Ａ及びＢはその電子部品実装多層基板１００の
形成例（その２）を示す工程図である。FIGS. 3A and 3B are process diagrams showing an example (part 2) of forming the electronic component-mounted multilayer substrate 100. FIGS.
【図４】その電子部品実装多層基板１００の形成時にお
けるＬＳＩ実装基板１の動作検査例を示すイメージ図で
ある。FIG. 4 is an image diagram showing an operation inspection example of the LSI mounting substrate 1 when the electronic component mounting multilayer substrate 100 is formed.
【図５】その電子部品実装多層基板１００の形成例（そ
の３）を示す層間配線部材４Ａ，５Ａの斜視図である。FIG. 5 is a perspective view of interlayer wiring members 4A and 5A showing an example (part 3) of forming the electronic component-mounted multilayer board 100.
【図６】その電子部品実装多層基板１００の形成例（そ
の４）を示す断面図である。FIG. 6 is a cross-sectional view showing an example (part 4) of forming the electronic component-mounted multilayer substrate 100.
【図７】Ａ〜Ｃは実施例としての層間配線部材４１〜４
３の構造例を示す斜視図である。7A to 7C show interlayer wiring members 41 to 4 as examples.
FIG. 4 is a perspective view showing a structural example of No. 3.
【図８】実施例としての層間配線部材４４の構造例を示
す斜視図である。FIG. 8 is a perspective view showing a structural example of an interlayer wiring member 44 as an embodiment.
【図９】実施例としての層間配線部材４５の構造例を示
す斜視図である。FIG. 9 is a perspective view showing a structural example of an interlayer wiring member 45 as an embodiment.
【図１０】実施例としての層間配線部材４６の構造例を
示す斜視図である。FIG. 10 is a perspective view showing a structural example of an interlayer wiring member 46 as an embodiment.
【図１１】実施例としての層間配線部材４７の構造例を
示す斜視図である。FIG. 11 is a perspective view showing a structural example of an interlayer wiring member 47 as an embodiment.
【図１２】第２の実施形態としての電子部品実装多層基
板２００の構造例を示す断面図である。FIG. 12 is a cross-sectional view illustrating a structural example of an electronic component-mounted multilayer substrate 200 as a second embodiment.
【図１３】Ａ及びＢは、その電子部品実装多層基板２０
０の形成例（その１）を示す工程図である。FIGS. 13A and 13B show the electronic component-mounted multilayer substrate 20;
FIG. 4 is a process diagram showing an example (No. 1) of forming 0;
【図１４】その電子部品実装多層基板２００の形成例
（その２）を示す断面図である。FIG. 14 is a cross-sectional view illustrating an example (part 2) of forming the electronic component-mounted multilayer substrate 200.
１・・・実装基板、１Ａ，１Ｂ，２１・・・ＬＳＩ実装
基板（第１の実装基板）、２・・・内層配線基板（第２
の実装基板）、３Ａ，３Ｂ・・・ＬＳＩチップ（電子部
品）、４Ａ，４Ｂ，５Ａ，５Ｂ，４１〜４７・・・層間
配線部材、６Ａ，６Ｂ，１９・・・シールドパターン
（導電部材）、１７・・・導電部材、２２・・・キャビ
ティ部、２３Ａ，２３Ｂ・・・ハンダボール（層間配線
部材）、１００，２００・・・電子部品実装多層基板Reference Signs List 1 mounting board, 1A, 1B, 21 ... LSI mounting board (first mounting board), 2 ... inner wiring board (second
3A, 3B ... LSI chip (electronic component), 4A, 4B, 5A, 5B, 41-47 ... interlayer wiring member, 6A, 6B, 19 ... shield pattern (conductive member) , 17: conductive member, 22: cavity portion, 23A, 23B: solder ball (interlayer wiring member), 100, 200: electronic component mounting multilayer board
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 ＦＩ テーマコート゛(参考） Ｈ０１Ｌ 25/18 Ｈ０５Ｋ 9/00 Ｒ Ｈ０５Ｋ 1/14 Ｈ０１Ｌ 25/08 Ｚ 3/36 9/00 Ｆターム(参考） 5E321 AA14 AA17 BB24 BB25 GG05 GG09 5E344 AA01 AA21 AA26 BB03 BB04 BB15 CC03 CC13 CC24 CD09 DD02 DD05 EE07 EE12 5E346 AA05 AA06 AA11 AA15 AA22 AA41 AA43 AA60 BB02 BB03 BB04 BB11 BB16 CC31 CC40 EE01 EE06 EE07 EE41 FF35 FF36 FF37 FF45 GG28 GG32 HH01 HH21 ──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. 7 Identification symbol FI Theme coat ゛ (Reference) H01L 25/18 H05K 9/00 R H05K 1/14 H01L 25/08 Z 3/36 9/00 F term ( Reference) 5E321 AA14 AA17 BB24 BB25 GG05 GG09 5E344 AA01 AA21 AA26 BB03 BB04 BB15 CC03 CC13 CC24 CD09 DD02 DD05 EE07 EE12 5E346 AA05 AA06 AA11 AA15 AA22 AA41 AA43 AA60 BB02 BB01 BB03 BB01 BB02 BB03 BB03 EE HH01 HH21
Claims (11)
実装基板が複数と、 前記実装基板間に設けられた中継ぎ用の層間配線部材
と、 前記層間配線部材によって画定される領域内であって、
少なくとも、前記電子部品に対向する側の実装基板に設
けられた所定の広さのシールド用の導電部材とを備え、 前記実装基板が層間配線部材を挟んで積層されると共
に、該実装基板間が前記層間配線部材により電気的に接
合された多層構造を成していることを特徴とする電子部
品実装多層基板。A plurality of mounting boards having electronic components mounted on one or both surfaces thereof; an intermediate wiring member provided between the mounting substrates; and a region defined by the interlayer wiring member. hand,
At least a conductive member for shielding having a predetermined size provided on the mounting board on the side facing the electronic component, wherein the mounting boards are stacked with an interlayer wiring member interposed therebetween, and between the mounting boards. An electronic component-mounted multilayer board having a multilayer structure electrically connected by the interlayer wiring member.
と、 前記電子部品に対向するように前記層間配線部材を挟ん
で積層された第２の実装基板とが設けられ、 前記電子部品に対向する側の第２の実装基板に所定の広
さの導電部材が設けられ、前記導電部材が接地されるこ
とを特徴とする請求項１に記載の電子部品実装多層基
板。A first mounting board on which the electronic component is mounted, and a second mounting board laminated with the interlayer wiring member interposed therebetween so as to face the electronic component; 2. The electronic component mounting multilayer board according to claim 1, wherein a conductive member having a predetermined size is provided on the second mounting board on the opposite side, and the conductive member is grounded.
ら構成される場合であって、 前記絶縁材料の内面側、芯部又は外面側に導電部材が設
けられ、 前記導電部材が接地されることを特徴とする請求項１に
記載の電子部品実装多層基板。3. A main part of the interlayer wiring member is made of an insulating material, wherein a conductive member is provided on an inner surface side, a core portion, or an outer surface side of the insulating material, and the conductive member is grounded. The electronic component-mounted multilayer board according to claim 1, wherein:
構造を有していることを特徴とする請求項１に記載の電
子部品実装多層基板。4. The electronic component mounting multilayer board according to claim 1, wherein the mounting substrate has a cavity structure provided with a groove or a hole for storing electronic components.
れる場合であって、 前記導電材料は、壁状、柱状又は球状を有していること
を特徴とする請求項１に記載の電子部品実装多層基板。5. The electronic component according to claim 1, wherein the interlayer wiring member is made of a conductive material, wherein the conductive material has a wall shape, a column shape, or a spherical shape. Mounting multilayer board.
実装基板を形成すると共に、前記電子部品に対向する側
の他の実装基板に所定の広さのシールド用の導電部材を
形成する工程と、 前記電子部品を導電部材に対向するようにして前記実装
基板間に中継ぎ用の層間配線部材を挟んで積層し接合す
る工程と、 前記実装基板間を前記層間配線部材により電気的に接合
する工程とを有することを特徴とする電子部品実装多層
基板の製造方法。6. A mounting substrate is formed by mounting an electronic component on one or both surfaces, and a conductive member for shielding having a predetermined size is formed on another mounting substrate facing the electronic component. And a step of stacking and bonding the electronic component so as to oppose a conductive member with an interlayer wiring member for relay between the mounting boards, and electrically bonding the mounting boards with the interlayer wiring member. And a method of manufacturing an electronic component-mounted multilayer substrate.
積層し接合する工程と、前記層間配線部材により実装基
板間を電気的に接合する工程とを同一の熱処理工程によ
って行うことを特徴とする請求項６に記載の電子部品実
装多層基板の製造方法。7. A step of laminating and bonding between mounting substrates with the interlayer wiring member interposed therebetween and electrically bonding the mounting substrates with the interlayer wiring member by the same heat treatment step. The method for manufacturing an electronic component-mounted multilayer board according to claim 6.
した後に、 前記実装基板毎に電気的な検査を行うことを特徴とする
請求項６に記載の電子部品実装多層基板の製造方法。8. The method for manufacturing an electronic component-mounted multilayer board according to claim 6, wherein an electrical inspection is performed for each of the mounted substrates after the electronic components are mounted to form a mounting substrate.
作検査用の電極を引き出すことを特徴とする請求項６に
記載の電子部品実装多層基板の製造方法。9. The method for manufacturing an electronic component-mounted multilayer board according to claim 6, wherein electrodes for operation inspection are drawn from the mounting substrate on which the electronic component is mounted.
することを特徴とする請求項９に記載の電子部品実装多
層基板の製造方法。10. The method according to claim 9, wherein the operation inspection electrode also serves as an electrode for electrically connecting to the interlayer wiring member.
ことを特徴とする請求項６に記載の電子部品実装多層基
板の製造方法。11. The method according to claim 6, wherein the conductive member for shielding is grounded.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28578799A JP2001111232A (en) | 1999-10-06 | 1999-10-06 | Electronic component mounting multilayer board and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28578799A JP2001111232A (en) | 1999-10-06 | 1999-10-06 | Electronic component mounting multilayer board and manufacturing method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2001111232A true JP2001111232A (en) | 2001-04-20 |
Family
ID=17696077
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP28578799A Pending JP2001111232A (en) | 1999-10-06 | 1999-10-06 | Electronic component mounting multilayer board and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2001111232A (en) |
Cited By (38)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002246536A (en) * | 2001-02-14 | 2002-08-30 | Ibiden Co Ltd | Method for manufacturing three-dimensional mounting package and package module for its manufacturing |
| JP2002270754A (en) * | 2001-03-09 | 2002-09-20 | Fujitsu Ltd | Semiconductor device |
| JP2003046058A (en) * | 2001-07-30 | 2003-02-14 | Mitsubishi Electric Corp | Semiconductor device |
| JP2004165318A (en) * | 2002-11-12 | 2004-06-10 | Ibiden Co Ltd | Multilayer printed wiring board |
| JP2005019568A (en) * | 2003-06-24 | 2005-01-20 | Fujitsu Ltd | Stacked semiconductor device |
| JP2005183410A (en) * | 2003-12-15 | 2005-07-07 | Nec Saitama Ltd | Wireless circuit module and wireless circuit board |
| JP2005535127A (en) * | 2002-08-01 | 2005-11-17 | レイセオン・カンパニー | Dielectric interconnect frame including electromagnetic shielding and hydrogen absorber for tile T / R module |
| JP2006053159A (en) * | 2005-10-17 | 2006-02-23 | Hitachi Ltd | In-vehicle electric wave type radar installation and its manufacturing method |
| JP2006094547A (en) * | 2005-10-17 | 2006-04-06 | Hitachi Ltd | Vehicle-mounted signal processing apparatus and vehicle-mounted radar installation |
| WO2006093155A1 (en) * | 2005-03-01 | 2006-09-08 | Matsushita Electric Industrial Co., Ltd. | Connector between substrates, and circuit board device using connector between substrates |
| JP2006310649A (en) * | 2005-04-28 | 2006-11-09 | Sharp Corp | Semiconductor device package and its manufacturing method |
| JP2006344847A (en) * | 2005-06-10 | 2006-12-21 | Murata Mfg Co Ltd | Substrate with built-in component, module equipped with built-in component using same, and method of manufacturing same |
| US7177161B2 (en) | 2003-09-05 | 2007-02-13 | Seiko Epson Corporation | Compact radio equipment and method of mounting the same |
| JP2007067279A (en) * | 2005-09-01 | 2007-03-15 | Mitsubishi Electric Corp | Shield structure |
| JP2007287820A (en) * | 2006-04-14 | 2007-11-01 | Renesas Technology Corp | Electronic device, and manufacturing method therefor |
| JP2007324354A (en) * | 2006-05-31 | 2007-12-13 | Sony Corp | Semiconductor device |
| JP2008053653A (en) * | 2006-08-28 | 2008-03-06 | Clover Denshi Kogyo Kk | Process for manufacturing multilayer printed wiring board |
| EP2056349A1 (en) * | 2001-10-18 | 2009-05-06 | Panasonic Corporation | Component built-in module and method for producing the same |
| WO2009093414A1 (en) * | 2008-01-22 | 2009-07-30 | Olympus Corporation | Multilayer packaging structure |
| KR101204224B1 (en) | 2005-03-17 | 2012-11-26 | 파나소닉 주식회사 | Module board |
| EP1657749A3 (en) * | 2004-10-29 | 2013-05-29 | Thales | Multilevel microelectronic package with internal shielding |
| JP2013167646A (en) * | 2013-05-22 | 2013-08-29 | Olympus Corp | Laminated mounting structure |
| CN103943599A (en) * | 2013-01-17 | 2014-07-23 | 中国科学院微电子研究所 | Interconnection structure and manufacture method thereof |
| EP2883432A4 (en) * | 2012-08-10 | 2016-05-11 | Ericsson Telefon Ab L M | Radio module and relavent manufacturing method |
| JP2018120950A (en) * | 2017-01-25 | 2018-08-02 | 株式会社ディスコ | Semiconductor package manufacturing method |
| JP2018182449A (en) * | 2017-04-07 | 2018-11-15 | 株式会社東芝 | Antenna module |
| JP2019114616A (en) * | 2017-12-21 | 2019-07-11 | 新光電気工業株式会社 | Protection circuit module, electronic equipment |
| US20200037437A1 (en) * | 2018-07-24 | 2020-01-30 | Samsung Electro-Mechanics Co., Ltd. | Electronic device module |
| WO2020085706A1 (en) * | 2018-10-22 | 2020-04-30 | 삼성전자 주식회사 | Electronic device filled with phase change material between plurality of circuit boards connected by connecting members |
| KR20200090718A (en) * | 2018-07-24 | 2020-07-29 | 삼성전기주식회사 | Electronic component module |
| CN113192935A (en) * | 2021-04-30 | 2021-07-30 | 苏州汉天下电子有限公司 | Semiconductor packaging structure and semiconductor packaging method |
| WO2021172739A1 (en) * | 2020-02-26 | 2021-09-02 | 삼성전자 주식회사 | Electronic device comprising interposer |
| JP2021132139A (en) * | 2020-02-20 | 2021-09-09 | 上銀科技股▲分▼有限公司 | Circuit board device |
| WO2022039453A1 (en) * | 2020-08-18 | 2022-02-24 | 삼성전자 주식회사 | Circuit board module and electronic device comprising same |
| WO2023095488A1 (en) * | 2021-11-25 | 2023-06-01 | 株式会社村田製作所 | Module |
| US11785718B2 (en) | 2019-04-02 | 2023-10-10 | Mitsubishi Electric Corporation | Composite printed wiring board and method of manufacturing the same |
| WO2023209926A1 (en) * | 2022-04-28 | 2023-11-02 | 三菱電機株式会社 | Semiconductor device |
| WO2024047809A1 (en) * | 2022-08-31 | 2024-03-07 | 日立Astemo株式会社 | Electronic control device |
-
1999
- 1999-10-06 JP JP28578799A patent/JP2001111232A/en active Pending
Cited By (58)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002246536A (en) * | 2001-02-14 | 2002-08-30 | Ibiden Co Ltd | Method for manufacturing three-dimensional mounting package and package module for its manufacturing |
| JP4694007B2 (en) * | 2001-02-14 | 2011-06-01 | イビデン株式会社 | Manufacturing method of three-dimensional mounting package |
| JP2002270754A (en) * | 2001-03-09 | 2002-09-20 | Fujitsu Ltd | Semiconductor device |
| JP4695769B2 (en) * | 2001-03-09 | 2011-06-08 | 富士通セミコンダクター株式会社 | Semiconductor device |
| JP2003046058A (en) * | 2001-07-30 | 2003-02-14 | Mitsubishi Electric Corp | Semiconductor device |
| JP4601874B2 (en) * | 2001-07-30 | 2010-12-22 | 三菱電機株式会社 | Semiconductor device |
| EP2056349A1 (en) * | 2001-10-18 | 2009-05-06 | Panasonic Corporation | Component built-in module and method for producing the same |
| JP2005535127A (en) * | 2002-08-01 | 2005-11-17 | レイセオン・カンパニー | Dielectric interconnect frame including electromagnetic shielding and hydrogen absorber for tile T / R module |
| JP2004165318A (en) * | 2002-11-12 | 2004-06-10 | Ibiden Co Ltd | Multilayer printed wiring board |
| JP2005019568A (en) * | 2003-06-24 | 2005-01-20 | Fujitsu Ltd | Stacked semiconductor device |
| US7177161B2 (en) | 2003-09-05 | 2007-02-13 | Seiko Epson Corporation | Compact radio equipment and method of mounting the same |
| JP2005183410A (en) * | 2003-12-15 | 2005-07-07 | Nec Saitama Ltd | Wireless circuit module and wireless circuit board |
| EP1657749A3 (en) * | 2004-10-29 | 2013-05-29 | Thales | Multilevel microelectronic package with internal shielding |
| JPWO2006093155A1 (en) * | 2005-03-01 | 2008-08-07 | 松下電器産業株式会社 | Board-to-board connector and circuit board device using board-to-board connector |
| WO2006093155A1 (en) * | 2005-03-01 | 2006-09-08 | Matsushita Electric Industrial Co., Ltd. | Connector between substrates, and circuit board device using connector between substrates |
| KR101204224B1 (en) | 2005-03-17 | 2012-11-26 | 파나소닉 주식회사 | Module board |
| US8675369B2 (en) | 2005-03-17 | 2014-03-18 | Panasonic Corporation | Module board |
| JP2006310649A (en) * | 2005-04-28 | 2006-11-09 | Sharp Corp | Semiconductor device package and its manufacturing method |
| JP2006344847A (en) * | 2005-06-10 | 2006-12-21 | Murata Mfg Co Ltd | Substrate with built-in component, module equipped with built-in component using same, and method of manufacturing same |
| JP4527035B2 (en) * | 2005-09-01 | 2010-08-18 | 三菱電機株式会社 | Shield structure |
| JP2007067279A (en) * | 2005-09-01 | 2007-03-15 | Mitsubishi Electric Corp | Shield structure |
| WO2007029355A1 (en) * | 2005-09-01 | 2007-03-15 | Mitsubishi Denki Kabushiki Kaisha | Shield structure |
| JP2006094547A (en) * | 2005-10-17 | 2006-04-06 | Hitachi Ltd | Vehicle-mounted signal processing apparatus and vehicle-mounted radar installation |
| JP2006053159A (en) * | 2005-10-17 | 2006-02-23 | Hitachi Ltd | In-vehicle electric wave type radar installation and its manufacturing method |
| JP2007287820A (en) * | 2006-04-14 | 2007-11-01 | Renesas Technology Corp | Electronic device, and manufacturing method therefor |
| JP2007324354A (en) * | 2006-05-31 | 2007-12-13 | Sony Corp | Semiconductor device |
| JP2008053653A (en) * | 2006-08-28 | 2008-03-06 | Clover Denshi Kogyo Kk | Process for manufacturing multilayer printed wiring board |
| US8385081B2 (en) | 2008-01-22 | 2013-02-26 | Olympus Corporation | Stacked mounting structure |
| JP2009174910A (en) * | 2008-01-22 | 2009-08-06 | Olympus Corp | Multilayered/mounted structure |
| WO2009093414A1 (en) * | 2008-01-22 | 2009-07-30 | Olympus Corporation | Multilayer packaging structure |
| EP2883432A4 (en) * | 2012-08-10 | 2016-05-11 | Ericsson Telefon Ab L M | Radio module and relavent manufacturing method |
| CN103943599A (en) * | 2013-01-17 | 2014-07-23 | 中国科学院微电子研究所 | Interconnection structure and manufacture method thereof |
| JP2013167646A (en) * | 2013-05-22 | 2013-08-29 | Olympus Corp | Laminated mounting structure |
| JP2018120950A (en) * | 2017-01-25 | 2018-08-02 | 株式会社ディスコ | Semiconductor package manufacturing method |
| JP2018182449A (en) * | 2017-04-07 | 2018-11-15 | 株式会社東芝 | Antenna module |
| JP2019114616A (en) * | 2017-12-21 | 2019-07-11 | 新光電気工業株式会社 | Protection circuit module, electronic equipment |
| JP6991059B2 (en) | 2017-12-21 | 2022-01-12 | 新光電気工業株式会社 | Protection circuit module, electronic device |
| US20200037437A1 (en) * | 2018-07-24 | 2020-01-30 | Samsung Electro-Mechanics Co., Ltd. | Electronic device module |
| KR102387747B1 (en) * | 2018-07-24 | 2022-04-15 | 삼성전기주식회사 | Electronic component module |
| KR20200090718A (en) * | 2018-07-24 | 2020-07-29 | 삼성전기주식회사 | Electronic component module |
| KR102146802B1 (en) * | 2018-07-24 | 2020-08-21 | 삼성전기주식회사 | Electronic component module |
| US10897811B2 (en) | 2018-07-24 | 2021-01-19 | Samsung Electro-Mechanics Co., Ltd. | Electronic device module |
| KR20200011180A (en) * | 2018-07-24 | 2020-02-03 | 삼성전기주식회사 | Electronic component module |
| US11252812B2 (en) | 2018-07-24 | 2022-02-15 | Samsung Electro-Mechanics Co., Ltd. | Electronic device module |
| WO2020085706A1 (en) * | 2018-10-22 | 2020-04-30 | 삼성전자 주식회사 | Electronic device filled with phase change material between plurality of circuit boards connected by connecting members |
| US11895767B2 (en) | 2018-10-22 | 2024-02-06 | Samsung Electronics Co., Ltd | Electronic device filled with phase change material between plurality of circuit boards connected by connecting members |
| US11785718B2 (en) | 2019-04-02 | 2023-10-10 | Mitsubishi Electric Corporation | Composite printed wiring board and method of manufacturing the same |
| JP2021132139A (en) * | 2020-02-20 | 2021-09-09 | 上銀科技股▲分▼有限公司 | Circuit board device |
| WO2021172739A1 (en) * | 2020-02-26 | 2021-09-02 | 삼성전자 주식회사 | Electronic device comprising interposer |
| WO2022039453A1 (en) * | 2020-08-18 | 2022-02-24 | 삼성전자 주식회사 | Circuit board module and electronic device comprising same |
| US11832389B2 (en) | 2020-08-18 | 2023-11-28 | Samsung Electronics Co., Ltd. | Printed circuit module and electronic device including the same |
| CN113192935A (en) * | 2021-04-30 | 2021-07-30 | 苏州汉天下电子有限公司 | Semiconductor packaging structure and semiconductor packaging method |
| CN113192935B (en) * | 2021-04-30 | 2023-04-07 | 苏州汉天下电子有限公司 | Semiconductor packaging structure and semiconductor packaging method |
| WO2022228470A1 (en) * | 2021-04-30 | 2022-11-03 | 苏州汉天下电子有限公司 | Semiconductor packaging structure and semiconductor packaging method |
| WO2023095488A1 (en) * | 2021-11-25 | 2023-06-01 | 株式会社村田製作所 | Module |
| WO2023209926A1 (en) * | 2022-04-28 | 2023-11-02 | 三菱電機株式会社 | Semiconductor device |
| JP7471538B2 (en) | 2022-04-28 | 2024-04-19 | 三菱電機株式会社 | Semiconductor Device |
| WO2024047809A1 (en) * | 2022-08-31 | 2024-03-07 | 日立Astemo株式会社 | Electronic control device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2001111232A (en) | Electronic component mounting multilayer board and manufacturing method thereof | |
| US8238109B2 (en) | Flex-rigid wiring board and electronic device | |
| US7989706B2 (en) | Circuit board with embedded component and method of manufacturing same | |
| KR101155624B1 (en) | Embedded pcb and manufacturing method for the same | |
| JP2008047917A (en) | Multilayer printed circuit board with electronic components built-in and its manufacturing method | |
| JP2001177045A (en) | Semiconductor device and method for manufacturing the same | |
| JP2003197809A (en) | Package for semiconductor device, the manufacturing method and semiconductor device | |
| JP2011029236A (en) | Wiring board and semiconductor device | |
| JP2001119147A (en) | Multilayer board incorporating electronic device and production method therefor | |
| JP2000243873A (en) | Wiring board, core substrate with built-in capacitor, main body of core substrate, capacitor and their manufacture | |
| JP2002016327A (en) | Wiring board and its manufacturing method | |
| JPWO2008050521A1 (en) | 3D electronic circuit device | |
| JP2006073684A (en) | Multilayer wiring board and manufacturing method thereof | |
| JP2005150443A (en) | Laminated semiconductor device and its manufacturing method | |
| JP2004296562A (en) | Substrate with built-in electronic components, and its manufacturing method | |
| JP3086332B2 (en) | Manufacturing method of multilayer printed wiring board | |
| JP4107932B2 (en) | Manufacturing method of electronic component mounting apparatus | |
| JPH01256161A (en) | Printed wiring board device | |
| JP2004056115A (en) | Multilayer wiring board | |
| JP2001119148A (en) | Multilayer board incorporating ic chips and production method therefor | |
| JPH01175296A (en) | Multilayer printed circuit board device | |
| JP2002110901A (en) | Laminated semiconductor device and its manufacturing method | |
| JP3582645B2 (en) | Manufacturing method of three-dimensional wiring board | |
| JP3360492B2 (en) | Electronic circuit board | |
| JP2002084071A (en) | Wiring board |