JP4601874B2 - Semiconductor device - Google Patents

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JP4601874B2
JP4601874B2 JP2001229453A JP2001229453A JP4601874B2 JP 4601874 B2 JP4601874 B2 JP 4601874B2 JP 2001229453 A JP2001229453 A JP 2001229453A JP 2001229453 A JP2001229453 A JP 2001229453A JP 4601874 B2 JP4601874 B2 JP 4601874B2
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control
terminal
conductor
semiconductor device
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JP2003046058A (en
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靖夫 高武
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Mitsubishi Electric Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48111—Disposition the wire connector extending above another semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Conversion In General (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device having noise prevented from being applied to a control terminal. SOLUTION: Cylindrical control terminals T1 and T2, which are stretched vertically to a common pattern 7 are arranged on the common pattern 7. A gate and a current sensing electrode of an IGBT element 1 are connected with terminal tables 211 and 231 which are arranged on base parts of the control terminals T1 and T2, respectively via metal wires WR. The control terminals T1 and T2 have structures, where a columnar or prism-shaped gate electrode 21 and a current sense terminal 23 are made central conductors, the peripheries are enclosed with insulation members IZ1, and the outer peripheries of the insulation members IZ1 are enclosed with control emitter terminals 22, respectively. The gate electrode 21 and the current sensing terminal 23 are protruded from end surfaces of the insulation members IZ1 and the control emitter terminals 22 which are arranged peripherally, and electrically connected with a control substrate 30, which is arranged above a relay terminal substrate 6.

Description

【０００１】
【発明の属する技術分野】
本発明は半導体装置に関し、特にモジュール化された電力用半導体装置に関する。
【０００２】
【従来の技術】
従来からトランジスタ素子、ＩＧＢＴ（Insulated Gate Bipolar Transistor）素子、ダイオード素子等の電力用半導体素子をパッケージングしてモジュール化した構成（以後、半導体装置モジュールと呼称）が知られている。
【０００３】
ここで、半導体装置モジュールの一例として、図８にＩＧＢＴ素子１およびダイオード素子２を有した構成を示す。
【０００４】
図８に示すようにダイオード素子２は、フリーホイールダイオードとして機能するように、ＩＧＢＴ素子１に対して順電流が還流する向きに並列に接続されている。
【０００５】
ＩＧＢＴ素子１のコレクタは主コレクタ端子板１２に接続され、エミッタは主エミッタ端子板１１に接続されるとともに、制御エミッタ端子２２にも接続されている。
【０００６】
制御エミッタ端子２２はＩＧＢＴ素子１の駆動に際して使用され、制御エミッタ端子２２とゲート端子２１との間にゲート−エミッタ間電圧（例えば１５Ｖ程度）を印加することでＩＧＢＴ素子１を駆動することができる。
【０００７】
また、ＩＧＢＴ素子１には電流センス電極が設けられており、当該電流センス電極は電流センス端子２３に接続されている。電流センス電極とは主エミッタ電極に流れる電流の数千分の１の電流（センス電流）が流れるように形成された電極であり、センス電流を検出することで、ＩＧＢＴ素子１をフィードバック制御して、過電流保護および短絡保護が可能となる。
【０００８】
ゲート端子２１、制御エミッタ端子２２、電流センス端子２３等の制御端子は、半導体装置モジュールの外部に導出されて、外部からの制御信号を受けたり、検出したセンス電流を外部に出力するように構成される場合もあるが、昨今では、電力用半導体素子の駆動回路や保護回路等の制御回路を内蔵したＩＰＭ（Intelligent Power Module）が開発され、パッケージ内に内蔵された制御回路基板に制御端子が接続される構成も多くなっている。
【０００９】
【発明が解決しようとする課題】
制御端子が外部に導出される半導体装置モジュールにしても、ＩＰＭにしても、制御端子のそれぞれは、端子間電圧による絶縁破壊を防止するため、それぞれ端子間距離を有して配設されている。そして、複数の制御端子は、モジュールの小型化や、半導体素子との接続の関係から隣接して配設されている。
【００１０】
そのため、ゲート端子２１と制御エミッタ端子２２、制御エミッタ端子２２と電流センス端子２３が送信アンテナと受信アンテナのような関係になり、例えばＩＧＢＴ素子１のスイッチング動作により、エミッタにノイズが出力された場合には、制御エミッタ端子２２のノイズがゲート端子２１あるいは電流センス端子２３に印加され、それぞれの信号がノイズを含む可能性がある。
【００１１】
その一例を図９に示す。図９(ａ)には、ゲート−エミッタ間電圧の正常な波形を、図９(ｂ)には、ゲート−エミッタ間電圧の波形にノイズを含む場合を示す。
【００１２】
なお、このようなノイズは、ＩＧＢＴ素子１のスイッチング動作に起因して発生するだけでなく、外部から与えられる場合もある。
【００１３】
本発明は上記のような問題点を解消するためになされたもので、制御端子にノイズが印加されることを防止した半導体装置を提供することを目的とする。
【００１４】
【課題を解決するための手段】
本発明に係る請求項１記載の半導体装置は、パッケージの底面部に収納された電力用半導体素子と、前記電力用半導体素子に電気的に接続され、前記電力用半導体素子の制御のための制御信号の中継に使用される制御端子とを備え、前記制御端子は、前記底面部に対して垂直方向に延在するように配設され、前記制御信号が流れる中心導体と、前記中心導体を取り囲むように配設された絶縁体と、前記絶縁体を取り囲むように配設された外周導体とを有し、前記外周導体は、前記電力用半導体素子の駆動に際して、基準電位に相当する電位が与えられ、前記中心導体の前記底面部側の第１の端部は、前記外周導体と絶縁を保って前記外周導体の側面から突出して前記電力用半導体素子との電気的接続のための端子台をなし、前記中心導体の前記底面部とは反対側の第２の端部は、前記絶縁体および前記外周導体の端面よりも突出し、前記制御信号の授受部をなしている。
【００１５】
本発明に係る請求項２記載の半導体装置は、前記制御端子が複数であって、前記複数の制御端子のそれぞれは、単一の前記中心導体、前記絶縁体および前記外周導体を備えている。
【００１６】
本発明に係る請求項３記載の半導体装置は、前記中心導体が複数であって、前記絶縁体は、前記複数の中心導体を個々に取り囲むように複数配設され、前記外周導体は、前記複数の絶縁体を共通して取り囲むように配設されている。
【００１７】
本発明に係る請求項４記載の半導体装置は、前記制御端子が、前記パッケージの前記底面部に平行に配設された導体パターン上に配設され、前記外周導体の端面が前記導体パターンに直接に接続される。
【００２０】
本発明に係る請求項５記載の半導体装置は、前記半導体装置が、前記電力用半導体素子の駆動制御を行う制御回路が配設された制御基板を内蔵してさらに備え、前記授受部は、前記制御基板に直接に接続される。
【００２１】
本発明に係る請求項６記載の半導体装置は、前記半導体装置が、前記電力用半導体素子の駆動制御を行う制御回路が配設された制御基板を、前記パッケージの外部においてさらに備え、前記授受部は、前記パッケージから突出して前記制御基板に直接に接続される。
【００２２】
【発明の実施の形態】
＜Ａ．実施の形態１＞
＜Ａ−１．装置構成＞
本発明に係る半導体装置の実施の形態１として、図１に半導体装置モジュール１００の構成を示す。
【００２３】
図１は半導体装置モジュール１００の内部構成を示す斜視図であり、樹脂パッケージ１０を部分的に省略して内部構成を示している。
【００２４】
図１に示すように、樹脂パッケージ１０の底部には絶縁性を有する絶縁基板３および中継端子基板６が間隔を開けて配設され、絶縁基板３上にはエミッタパターン４、コレクタパターン５が互いに電気的に分離されて配設され、中継端子基板６上には共通パターン７が配設されている。なお、中継端子基板６は絶縁性を有する基板であれば何でも良い。
【００２５】
そして、コレクタパターン５上にはＩＧＢＴ素子１およびダイオード素子２が１個ずつ配設され、ＩＧＢＴ素子１とエミッタパターン４との間、ダイオード素子２とエミッタパターン４との間は、複数の金属ワイヤーＷＲによって電気的に接続されている。
【００２６】
また、共通パターン７上には、共通パターン７に垂直に延在する円筒状の制御端子Ｔ１およびＴ２が配設され、ＩＧＢＴ素子１のゲートおよび電流センス電極は、金属ワイヤーＷＲを介して、それぞれ制御端子Ｔ１およびＴ２の基部に設けられた端子台２１１および２３１に接続されている。また、ＩＧＢＴ素子１のエミッタは、金属ワイヤーＷＲを介して共通パターン７に接続されている。
【００２７】
制御端子Ｔ１およびＴ２は、それぞれ円柱状あるいは角柱状のゲート端子２１および電流センス端子２３を中心導体として、その周囲を絶縁体ＩＺ１で囲み、絶縁体ＩＺ１の外周をそれぞれ制御エミッタ端子２２で囲んだ構造を有している。なお、制御エミッタ端子２２は絶縁体ＩＺ１の外周を囲むように配設されるので外周導体と呼称することができる。
【００２８】
そして、制御端子Ｔ１およびＴ２においては、周設された絶縁体ＩＺ１および制御エミッタ端子２２の端面よりもゲート端子２１および電流センス端子２３が突出しており、ゲート端子２１および電流センス端子２３は、中継端子基板６の上方に配設された制御基板３０に電気的に接続される構成となっている。
【００２９】
制御基板３０には、ＩＧＢＴ素子１の駆動回路や保護回路等の制御回路が配設されており、制御基板３０を内蔵することで半導体装置モジュール１００はＩＰＭとなっている。なお、制御基板３０を内蔵することで、電力用半導体素子からの信号経路が短くなり、制御信号にノイズが印加される可能性を低減できる。
【００３０】
また、エミッタパターン４およびコレクタパターン５には、主エミッタ端子板１１および主コレクタ端子板１２が接続されている。主エミッタ端子板１１および主コレクタ端子板１２は、細長形状を有し、その長手方向の一端の主面がエミッタパターン４およびコレクタパターン５に接続されるように折り曲げられ、他端の主面が樹脂パッケージ１０の上面において露出するように配設されている。
【００３１】
ここで、制御端子Ｔ２におけるＡ−Ａ線での断面構成を図２に示す。また、図３に制御端子Ｔ２の基部の構造を斜視図で示す。
【００３２】
図２に示すように、電流センス端子２３の断面形状はＬ字形状をなし、Ｌ字形状の長辺にあたる部分が中心導体として絶縁体ＩＺ１および制御エミッタ端子２２で囲まれ、Ｌ字形状の短辺にあたる部分が端子台２３１として露出している。
【００３３】
なお、制御エミッタ端子２２は、その底面部において中継端子基板６の主面上の共通パターン７に半田付け等で接続されるので、共通パターン７との接触抵抗を低くすることができ、また、制御エミッタ端子２２は、その上面部において制御基板３０の下主面に設けられた導体パターン３０２に半田付け等で接続されているので、導体パターン３０２との接触抵抗を低くすることができる。
【００３４】
電流センス端子２３は、ＩＧＢＴ素子１のセンス電極に流れるセンス電流の検出信号を制御基板３０に中継するので、そこに流れる電気信号は、ＩＧＢＴ素子１を直接に制御するものではないが、センス電流に基づいてＩＧＢＴ素子１がフィードバック制御されるので、電流センス端子２３に流れる電気信号を制御信号と呼称する。
【００３５】
なお、図２および図３で示すように、端子台２３１の下部は絶縁体ＩＺ１で覆われ、共通パターン７とは電気的に絶縁されている。
【００３６】
一方、電流センス端子２３の長辺先端部は制御基板３０を貫通して制御基板３０の上主面から突出し、制御基板３０の上主面に設けられた導体パターン３０１に半田付け等で接続されている。導体パターン３０１および３０２は、制御基板３０上に設けられた制御回路の所定部分に接続され、電気信号（制御信号）の授受によりＩＧＢＴ素子１およびダイオード素子２の動作を制御することになるが、制御回路の構造および動作については本発明との関連が薄いので説明は省略する。
【００３７】
このような構成により、中継端子基板６の主面上の共通パターン７は、制御エミッタ端子２２を介して制御基板３０の下主面に設けられた導体パターン３０２に電気的に接続され、電流センス端子２３は、制御基板３０の上主面に設けられた導体パターン３０１に電気的に接続されることになる。なお、制御端子Ｔ１の構成も制御端子Ｔ２と同様である。
【００３８】
＜Ａ−２．作用効果＞
以上説明したように、本発明に係る半導体装置モジュール１００においては、ゲート端子２１および電流センス端子２３を中心導体として、その周囲を絶縁体ＩＺ１で囲み、絶縁体ＩＺ１の外周を、基準電位に相当する電位が与えられる制御エミッタ端子２２で囲んだ構造の制御端子Ｔ１およびＴ２を有しているので、制御信号の中継に際して、ゲート端子２１と制御エミッタ端子２２、制御エミッタ端子２２と電流センス端子２３が送信アンテナと受信アンテナのような関係になることが防止され、ＩＧＢＴ素子１のスイッチング動作に起因して発生するノイズがゲート端子２１および電流センス端子２３に流れる電気信号（制御信号）に印加されることを防止できる。
【００３９】
また、ゲート端子２１および電流センス端子２３を電気的にシールドでき、外部からのノイズがゲート端子２１および電流センス端子２３に流れる電気信号に印加されることを防止できる。
【００４０】
さらに、制御端子Ｔ１およびＴ２が独立しているので、制御端子の配設が自由にできる。
【００４１】
＜Ｂ．実施の形態２＞
＜Ｂ−１．装置構成＞
本発明に係る半導体装置の実施の形態２として、図４に半導体装置モジュール２００の構成を示す。
【００４２】
図４は半導体装置モジュール２００の内部構成を示す斜視図であるが、制御端子Ｔ３以外の構成は図１を用いて説明した半導体装置モジュール１００と同じであるので、図示および説明は省略する。
【００４３】
図４において、中継端子基板６主面の共通パターン７上には、共通パターン７に垂直に延在する制御端子Ｔ３が配設されている。そして、ＩＧＢＴ素子１のゲートおよび電流センス電極は、金属ワイヤーＷＲを介して、それぞれ制御端子Ｔ３の基部に設けられた端子台２１１および２３１に接続されている。また、ＩＧＢＴ素子１のエミッタは、金属ワイヤーＷＲを介して共通パターン７に接続されている。
【００４４】
制御端子Ｔ３は、共通パターン７上に間を開けて垂直に延在するように配設されたゲート端子２１および電流センス端子２３を中心導体とし、その周囲をそれぞれ絶縁体ＩＺ１で囲み、２つの絶縁体ＩＺ１の外周を制御エミッタ端子２２で共通に囲んだ構造を有している。なお、制御エミッタ端子２２は２つの絶縁体ＩＺ１の外周を囲むように配設されるので外周導体と呼称することができる。
【００４５】
また、ゲート端子２１および電流センス端子２３の構造は、図２を用いて説明した制御端子Ｔ２と同様である。
【００４６】
そして、ゲート端子２１および電流センス端子２３に周設されたそれぞれの絶縁体ＩＺ１および、２つの絶縁体ＩＺ１を共通に取り囲む制御エミッタ端子２２の端面よりも、ゲート端子２１および電流センス端子２３が突出しており、ゲート端子２１および電流センス端子２３は、中継端子基板６の上方に配設された制御基板３０に電気的に接続される構成となっている。
【００４７】
＜Ｂ−２．作用効果＞
以上説明したように、本発明に係る半導体装置モジュール２００においては、ゲート端子２１および電流センス端子２３を中心導体として、その周囲をそれぞれ絶縁体ＩＺ１で囲み、２つの絶縁体ＩＺ１を基準電位に相当する電位が与えられる制御エミッタ端子２２で共通に取り囲んだ構造の制御端子Ｔ３を有しているので、制御エミッタ端子２２の断面積を広くでき、制御信号の中継に際して、ゲート端子２１および電流センス端子２３に対する電気的なシールド性能を高めることができ、外部からのノイズがゲート端子２１および電流センス端子２３に流れる電気信号（制御信号）に印加されることを、より効果的に防止できる。
【００４８】
＜Ｃ．実施の形態３＞
＜Ｃ−１．装置構成＞
本発明に係る半導体装置の実施の形態３として、図５に半導体装置モジュール３００の構成を示す。
【００４９】
実施の形態１および２として、図１および図４を用いて説明した半導体装置モジュール１００および２００においては、円柱状あるいは角柱状のゲート端子２１および電流センス端子２３を中心導体として、その周囲を絶縁体ＩＺ１が囲む構造の制御端子を有していたが、図５に示す半導体装置モジュール３００においては、平板状をなすゲート端子２１０、制御エミッタ端子２２０および電流センス端子２３０等の制御端子を、それらの主面が対向するように配設する構成となっている。
【００５０】
すなわち、制御端子であるゲート端子２１０、制御エミッタ端子２２０および電流センス端子２３０は、平面視形状が矩形状の本体部ＢＤ２１、ＢＤ２２およびＢＤ２３と、それぞれの一方の長辺から延在する突片２１２、２２２および２３２と、他方の長辺から延在する突片２１１、２２１および２３１とを有し、突片２１１、２２１および２３１の主面が中継端子基板６の主面上に接続されるように折り曲げられ、それぞれ端子台２１１、２２１および２３１となっている。
【００５１】
そして、基準電位に相当する電位が与えられる制御エミッタ端子２２０を中央に配置し、制御エミッタ端子２２０の両主面にそれぞれの主面が対向するようにゲート端子２１０および電流センス端子２３０が配設されている。
【００５２】
なお、端子台２１１、２２１および２３１は、互いに電気的に分離される必要があるので、突片２１１、２２１および２３１は、本体部ＢＤ２１、ＢＤ２２およびＢＤ２３の一方の長辺のそれぞれ異なる位置から延在し、互いに接触しないように折り曲げられている。
【００５３】
また、中継端子基板６上には、端子台２１１、２２１および２３１が共通して接続されるような導体パターンは設けられておらず、端子台２１１、２２１および２３１をそれぞれ半田付け等で、中継端子基板６上に接続するための部分的な導体パターンが設けられているが、それらは端子台２１１、２２１および２３１と同等の面積を有していれば良いので、端子台２１１、２２１および２３１の載置によって隠れ、図中には示されていない。
【００５４】
そして、突片２１２、２２２および２３２が、中継端子基板６の上方に配設された制御基板３０に電気的に接続される構成となっている。
【００５５】
なお、ゲート端子２１０、制御エミッタ端子２２０および電流センス端子２３０の、それぞれの本体部ＢＤ２１、ＢＤ２２およびＢＤ２３の間には、樹脂パッケージ１０を成形する際に、モールド樹脂が充填されるので、組み立ての段階では間隙を有する構造としていても良いが、確実な絶縁を行うために、絶縁材を挟むようにしても良い。
【００５６】
図５に、ゲート端子２１０、制御エミッタ端子２２０および電流センス端子２３０を図４の矢示Ｂ方向から見た図を示す。図５に示すように、本体部ＢＤ２１とＢＤ２２との主面間、および本体部ＢＤ２２とＢＤ２３との主面間に、絶縁体ＩＺ２を挟み込んだ構成にすることで、各主面間隔を一定にでき、また、確実な絶縁が可能となる。
【００５７】
なお、絶縁体ＩＺ２は、ゲル状の絶縁材を塗布して硬化させて形成しても良く、絶縁シートを挟み込む構成としても良い。
【００５８】
なお、その他の構成は図１を用いて説明した半導体装置モジュール１００と同じであるので、図示および説明は省略する。
【００５９】
＜Ｃ−２．作用効果＞
以上説明したように、本発明に係る半導体装置モジュール３００においては、基準電位に相当する電位が与えられる制御エミッタ端子２２０を中央に配置し、制御エミッタ端子２２０の両主面にそれぞれの主面が対向するようにゲート端子２１０および電流センス端子２３０が配設されているので、制御信号の中継に際して、ゲート端子２１０と制御エミッタ端子２２０、制御エミッタ端子２２０と電流センス端子２３０が送信アンテナと受信アンテナのような関係になることが防止され、ＩＧＢＴ素子１のスイッチング動作に起因して発生するノイズがゲート端子２１０および電流センス端子２３０に流れる電気信号（制御信号）に印加されることを防止できる。また、各端子の主面間隔を絶縁破壊しない程度まで狭くすることで、外部からのノイズがゲート端子２１０および電流センス端子２３０に流れる電気信号（制御信号）に印加されることを防止できる。
【００６０】
なお、以上の説明においては、制御端子が３つの場合について言及したが、制御端子が３つを越える場合であっても、制御エミッタ端子２２０を複数設け、それらの両主面に対向するように残りの制御端子を配設することで、制御エミッタ端子２２０と他の制御端子との間で、送信アンテナと受信アンテナのような関係になることが防止される。
【００６１】
＜Ｄ．変形例＞
以上説明した実施の形態１〜３の半導体装置モジュール１００〜３００においては、制御基板３０を内蔵したＩＰＭとして説明したが、制御基板３０が外部に配設される構成であっても良い。
【００６２】
その場合、制御基板３０は樹脂パッケージ１０の上面上部に配設され、そこに、例えば、図１に示す制御端子Ｔ１およびＴ２のゲート端子２１および電流センス端子２３が樹脂パッケージ１０の上面から突出して接続され、また、図４に示す制御端子Ｔ３のゲート端子２１および電流センス端子２３が樹脂パッケージ１０の上面から突出して接続され、また、図５に示すゲート端子２１０、制御エミッタ端子２２０および電流センス端子２３０の突片２１２、２２２および２３２が樹脂パッケージ１０の上面から突出して接続されることになる。このような構成により、半導体装置モジュールを小型化できる。
【００６３】
また、実施の形態１〜３の半導体装置モジュール１００〜３００においては、図８に示したように、ＩＧＢＴ素子１とダイオード素子２の１組の電力用半導体素子を備える構成として説明したが、ＩＧＢＴ素子１とダイオード素子２の組は１組に限定されるものではなく、複数の組が並列に接続されていても良く、また直列に接続されて構成であっても良い。
【００６４】
例えば、図７に示すように、ＩＧＢＴ素子１Ａおよび１Ｂが直列に接続され、ＩＧＢＴ素子１Ａおよび１Ｂには、それぞれダイオード素子１Ａおよび１Ｂが逆並列に接続されている。
【００６５】
ＩＧＢＴ素子１Ａのコレクタは主コレクタ端子板１２１に接続され、ＩＧＢＴ素子１ＡのエミッタおよびＩＧＢＴ素子１Ｂのコレクタは、共通して出力端子板１２２に接続されている。この出力端子板１２２は、外部に設けられたモータなどの誘導性負荷に接続される。そして、ＩＧＢＴ素子１Ｂのエミッタは主エミッタ端子板１２３に接続されている。
【００６６】
また、ＩＧＢＴ素子１Ａおよび１Ｂのエミッタは、それぞれ制御エミッタ端子２２Ａおよび２２Ｂに接続され、ＩＧＢＴ素子１Ａおよび１Ｂの電流センス電極は、それぞれ電流センス端子２３Ａおよび２３Ｂに接続され、ＩＧＢＴ素子１Ａおよび１Ｂのゲートは、それぞれゲート端子２１Ａおよび２１Ｂに接続されている。
【００６７】
このような構成において、ゲート端子２１Ａ、制御エミッタ端子２２Ａおよび電流センス端子２３Ａの３つの制御端子で１組をなし、ゲート端子２１Ｂ、制御エミッタ端子２２Ｂおよび電流センス端子２３Ｂの３つの制御端子で１組をなすので、制御端子のそれぞれの組において、実施の形態１〜３の半導体装置モジュール１００〜３００において示した制御端子の構成を採るようにすれば良い。
【００６８】
【発明の効果】
本発明に係る請求項１記載の半導体装置によれば、制御信号が流れる中心導体の周囲を絶縁体で囲み、絶縁体の外周を、基準電位に相当する電位が与えられる外周導体で囲んだ構造の制御端子を備えるので、中心導体がアンテナとなることを防止でき、制御信号の中継に際して、電力用半導体素子のスイッチング動作に起因して発生するノイズが制御信号に印加されることを防止できる。また、中心導体を電気的にシールドでき、外部からのノイズが制御信号に印加されることを防止できる。
【００６９】
本発明に係る請求項２記載の半導体装置によれば、外周導体が、複数の制御端子のそれぞれに配設されるので、各制御端子の独立性を保つことができ、制御端子の配設が自由にできる。
【００７０】
本発明に係る請求項３記載の半導体装置によれば、複数の中心導体の周囲をそれぞれ絶縁体で囲み、複数の絶縁体の外周を、基準電位に相当する電位が与えられる外周導体で共通に囲んだ構造の制御端子を備えるので、外周導体の断面積を広くでき、制御信号の中継に際して、複数の中心導体に対する電気的なシールド性能を高めることができ、外部からのノイズが複数の中心導体に流れる制御信号に印加されることを、より効果的に防止できる。
【００７１】
本発明に係る請求項４記載の半導体装置によれば、外周導体の端面が導体パターンに直接に接続されるので、外周導体と導体パターンとの接触面積を広くでき、接触抵抗を低減できる。
【００７４】
本発明に係る請求項５記載の半導体装置によれば、電力用半導体素子の駆動制御を行う制御回路が配設された制御基板を内蔵し、制御信号の授受部が制御基板に直接に接続されるので、電力用半導体素子から制御基板までの信号経路が短くなり、制御信号にノイズが印加される可能性を低減できる。
【００７５】
本発明に係る請求項６記載の半導体装置によれば、電力用半導体素子の駆動制御を行う制御回路が配設された制御基板を、樹脂パッケージの外部において備えるので、半導体装置モジュールを小型化できる。
【図面の簡単な説明】
【図１】 本発明に係る実施の形態１の半導体装置モジュールの内部構成を示す斜視図である。
【図２】 本発明に係る実施の形態１の半導体装置モジュールの制御端子の構成を示す断面図である。
【図３】 本発明に係る実施の形態１の半導体装置モジュールの制御端子の構成を示す斜視図である。
【図４】 本発明に係る実施の形態２の半導体装置モジュールの内部構成を示す斜視図である。
【図５】 本発明に係る実施の形態３の半導体装置モジュールの内部構成を示す斜視図である。
【図６】 本発明に係る実施の形態３の半導体装置モジュールの制御端子の構成を示す側面図である。
【図７】 電力用半導体素子の組み合わせの一例を示す図である。
【図８】 電力用半導体素子と制御端子との接続関係を示す図である。
【図９】 従来の半導体装置モジュールの問題点を示す図である。
【符号の説明】
２１，２１０ ゲート端子、２２，２２０ 制御エミッタ端子、２３，２３０電流センス端子、２１１，２３１ 端子台、Ｔ１，Ｔ２，Ｔ３ 制御端子、ＩＺ１，ＩＺ２ 絶縁体。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device, and more particularly to a modularized power semiconductor device.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, a configuration in which a power semiconductor element such as a transistor element, an IGBT (Insulated Gate Bipolar Transistor) element, or a diode element is packaged into a module (hereinafter referred to as a semiconductor device module) is known.
[0003]
Here, as an example of the semiconductor device module, FIG. 8 shows a configuration having an IGBT element 1 and a diode element 2.
[0004]
As shown in FIG. 8, the diode element 2 is connected in parallel to the IGBT element 1 in a direction in which forward current flows back so as to function as a free wheel diode.
[0005]
The collector of the IGBT element 1 is connected to the main collector terminal plate 12, and the emitter is connected to the main emitter terminal plate 11 and also to the control emitter terminal 22.
[0006]
The control emitter terminal 22 is used when driving the IGBT element 1, and the IGBT element 1 can be driven by applying a gate-emitter voltage (for example, about 15 V) between the control emitter terminal 22 and the gate terminal 21. .
[0007]
The IGBT element 1 is provided with a current sense electrode, and the current sense electrode is connected to the current sense terminal 23. The current sense electrode is an electrode formed such that a current that is one thousandth of the current flowing through the main emitter electrode (sense current) flows. By detecting the sense current, feedback control of the IGBT element 1 is performed. Overcurrent protection and short circuit protection are possible.
[0008]
Control terminals such as the gate terminal 21, the control emitter terminal 22, and the current sense terminal 23 are derived to the outside of the semiconductor device module so as to receive an external control signal and output a detected sense current to the outside. Recently, IPM (Intelligent Power Module) with built-in control circuits such as drive circuit and protection circuit for power semiconductor elements has been developed, and control terminals are provided on the control circuit board built in the package. The number of connected components is also increasing.
[0009]
[Problems to be solved by the invention]
Regardless of whether the control terminal is a semiconductor device module derived from the outside or the IPM, each of the control terminals is disposed with a distance between the terminals in order to prevent dielectric breakdown due to the voltage between the terminals. . The plurality of control terminals are arranged adjacent to each other in view of the miniaturization of the module and the connection with the semiconductor element.
[0010]
Therefore, when the gate terminal 21 and the control emitter terminal 22, the control emitter terminal 22 and the current sense terminal 23 are in a relationship like a transmission antenna and a reception antenna, for example, when noise is output to the emitter by the switching operation of the IGBT element 1. In this case, the noise of the control emitter terminal 22 is applied to the gate terminal 21 or the current sense terminal 23, and each signal may contain noise.
[0011]
An example is shown in FIG. FIG. 9A shows a normal waveform of the gate-emitter voltage, and FIG. 9B shows a case where noise is included in the waveform of the gate-emitter voltage.
[0012]
Such noise is not only generated due to the switching operation of the IGBT element 1, but may be given from the outside.
[0013]
The present invention has been made to solve the above-described problems, and an object thereof is to provide a semiconductor device in which noise is not applied to a control terminal.
[0014]
[Means for Solving the Problems]
According to a first aspect of the present invention, there is provided a semiconductor device comprising: a power semiconductor element housed in a bottom portion of a package; and a control for controlling the power semiconductor element that is electrically connected to the power semiconductor element. A control terminal used for signal relay, the control terminal being arranged to extend in a direction perpendicular to the bottom surface portion, and surrounding a central conductor through which the control signal flows And an outer conductor disposed so as to surround the insulator, and the outer conductor is given a potential corresponding to a reference potential when driving the power semiconductor element. A first end portion of the center conductor on the bottom surface side that protrudes from a side surface of the outer peripheral conductor while maintaining insulation with the outer peripheral conductor, and serves as a terminal block for electrical connection with the power semiconductor element. None, before the center conductor The bottom portion second end opposite the insulating body and the outer peripheral conductor protrudes from the end face of the forms a transfer portion of said control signal.
[0015]
In a semiconductor device according to a second aspect of the present invention, the control terminal includes a plurality of control terminals, and each of the plurality of control terminals includes the single central conductor, the insulator, and the outer peripheral conductor.
[0016]
According to a third aspect of the present invention, there is provided the semiconductor device according to the third aspect, wherein the plurality of central conductors are provided, the plurality of insulators are disposed so as to individually surround the plurality of central conductors, and the outer peripheral conductors are provided in the plurality. These insulators are arranged so as to surround them in common.
[0017]
According to a fourth aspect of the present invention, in the semiconductor device according to the present invention, the control terminal is disposed on a conductor pattern disposed in parallel to the bottom surface portion of the package, and an end surface of the outer peripheral conductor is directly on the conductor pattern. Connected to.
[0020]
According to a fifth aspect of the present invention, the semiconductor device further includes a built-in control board on which a control circuit that performs drive control of the power semiconductor element is disposed, and Connected directly to the control board.
[0021]
According to a sixth aspect of the present invention, in the semiconductor device, the semiconductor device further includes a control board on which a control circuit for controlling driving of the power semiconductor element is disposed outside the package, and the transfer unit Protrudes from the package and is directly connected to the control board.
[0022]
DETAILED DESCRIPTION OF THE INVENTION
<A. Embodiment 1>
<A-1. Device configuration>
FIG. 1 shows a configuration of a semiconductor device module 100 as a first embodiment of a semiconductor device according to the present invention.
[0023]
FIG. 1 is a perspective view showing an internal configuration of the semiconductor device module 100, in which the resin package 10 is partially omitted to show the internal configuration.
[0024]
As shown in FIG. 1, an insulating substrate 3 and a relay terminal substrate 6 having insulating properties are disposed at the bottom of the resin package 10 at an interval, and an emitter pattern 4 and a collector pattern 5 are arranged on the insulating substrate 3. The common pattern 7 is disposed on the relay terminal board 6. The relay terminal board 6 may be anything as long as it is an insulating board.
[0025]
One IGBT element 1 and one diode element 2 are disposed on the collector pattern 5, and a plurality of metal wires are provided between the IGBT element 1 and the emitter pattern 4 and between the diode element 2 and the emitter pattern 4. It is electrically connected by WR.
[0026]
Further, on the common pattern 7, cylindrical control terminals T1 and T2 extending perpendicularly to the common pattern 7 are disposed, and the gate and current sense electrode of the IGBT element 1 are respectively connected via the metal wire WR. It is connected to terminal blocks 211 and 231 provided at the bases of the control terminals T1 and T2. The emitter of the IGBT element 1 is connected to the common pattern 7 via the metal wire WR.
[0027]
The control terminals T1 and T2 each have a cylindrical or prismatic gate terminal 21 and a current sense terminal 23 as center conductors, the periphery thereof being surrounded by an insulator IZ1, and the outer periphery of the insulator IZ1 being surrounded by a control emitter terminal 22, respectively. It has a structure. Since the control emitter terminal 22 is disposed so as to surround the outer periphery of the insulator IZ1, it can be called an outer peripheral conductor.
[0028]
At the control terminals T1 and T2, the gate terminal 21 and the current sense terminal 23 protrude from the peripheral surfaces of the insulator IZ1 and the control emitter terminal 22, and the gate terminal 21 and the current sense terminal 23 are relayed. It is configured to be electrically connected to a control board 30 disposed above the terminal board 6.
[0029]
The control board 30 is provided with a control circuit such as a drive circuit and a protection circuit for the IGBT element 1. By incorporating the control board 30, the semiconductor device module 100 is an IPM. By incorporating the control board 30, the signal path from the power semiconductor element is shortened, and the possibility that noise is applied to the control signal can be reduced.
[0030]
A main emitter terminal plate 11 and a main collector terminal plate 12 are connected to the emitter pattern 4 and the collector pattern 5. The main emitter terminal plate 11 and the main collector terminal plate 12 have an elongated shape, and are bent so that the main surface at one end in the longitudinal direction is connected to the emitter pattern 4 and the collector pattern 5, and the main surface at the other end is The resin package 10 is disposed so as to be exposed on the upper surface.
[0031]
Here, FIG. 2 shows a cross-sectional configuration of the control terminal T2 along the line AA. FIG. 3 is a perspective view showing the structure of the base of the control terminal T2.
[0032]
As shown in FIG. 2, the cross section of the current sense terminal 23 is L-shaped, and the portion corresponding to the long side of the L-shape is surrounded by the insulator IZ1 and the control emitter terminal 22 as a central conductor, and the short shape of the L-shape is short. A portion corresponding to the side is exposed as a terminal block 231.
[0033]
In addition, since the control emitter terminal 22 is connected to the common pattern 7 on the main surface of the relay terminal substrate 6 by soldering or the like at the bottom surface portion thereof, the contact resistance with the common pattern 7 can be lowered, Since the control emitter terminal 22 is connected to the conductor pattern 302 provided on the lower main surface of the control board 30 by soldering or the like on the upper surface portion thereof, the contact resistance with the conductor pattern 302 can be lowered.
[0034]
Since the current sense terminal 23 relays the detection signal of the sense current flowing through the sense electrode of the IGBT element 1 to the control board 30, the electric signal flowing there does not directly control the IGBT element 1, but the sense current Since the IGBT element 1 is feedback-controlled based on the above, the electric signal flowing through the current sense terminal 23 is referred to as a control signal.
[0035]
2 and 3, the lower portion of the terminal block 231 is covered with an insulator IZ1 and is electrically insulated from the common pattern 7.
[0036]
On the other hand, the front end of the long side of the current sense terminal 23 penetrates the control board 30 and protrudes from the upper main surface of the control board 30 and is connected to the conductor pattern 301 provided on the upper main surface of the control board 30 by soldering or the like. ing. The conductor patterns 301 and 302 are connected to a predetermined portion of a control circuit provided on the control board 30 and control the operations of the IGBT element 1 and the diode element 2 by sending and receiving electrical signals (control signals). The structure and operation of the control circuit are not related to the present invention, and thus description thereof is omitted.
[0037]
With such a configuration, the common pattern 7 on the main surface of the relay terminal board 6 is electrically connected to the conductor pattern 302 provided on the lower main surface of the control board 30 via the control emitter terminal 22, and current sensing is performed. The terminal 23 is electrically connected to the conductor pattern 301 provided on the upper main surface of the control board 30. The configuration of the control terminal T1 is the same as that of the control terminal T2.
[0038]
<A-2. Effect>
As described above, in the semiconductor device module 100 according to the present invention, the gate terminal 21 and the current sense terminal 23 are the central conductors, the periphery thereof is surrounded by the insulator IZ1, and the outer periphery of the insulator IZ1 corresponds to the reference potential. Control terminals T1 and T2 having a structure surrounded by a control emitter terminal 22 to which a potential to be applied is provided. Therefore, when relaying a control signal, the gate terminal 21 and the control emitter terminal 22, and the control emitter terminal 22 and the current sense terminal 23 are provided. Becomes a relationship between the transmitting antenna and the receiving antenna, and noise generated due to the switching operation of the IGBT element 1 is applied to the electric signal (control signal) flowing through the gate terminal 21 and the current sense terminal 23. Can be prevented.
[0039]
Further, the gate terminal 21 and the current sense terminal 23 can be electrically shielded, and external noise can be prevented from being applied to the electric signal flowing through the gate terminal 21 and the current sense terminal 23.
[0040]
Further, since the control terminals T1 and T2 are independent, the control terminals can be arranged freely.
[0041]
<B. Second Embodiment>
<B-1. Device configuration>
As a second embodiment of the semiconductor device according to the present invention, FIG. 4 shows a configuration of a semiconductor device module 200.
[0042]
FIG. 4 is a perspective view showing the internal configuration of the semiconductor device module 200, but the configuration other than the control terminal T3 is the same as that of the semiconductor device module 100 described with reference to FIG.
[0043]
In FIG. 4, a control terminal T <b> 3 extending perpendicularly to the common pattern 7 is disposed on the common pattern 7 on the main surface of the relay terminal board 6. The gate and current sense electrode of the IGBT element 1 are connected to terminal blocks 211 and 231 provided at the base of the control terminal T3, respectively, via a metal wire WR. The emitter of the IGBT element 1 is connected to the common pattern 7 via the metal wire WR.
[0044]
The control terminal T3 has a gate terminal 21 and a current sense terminal 23 arranged so as to extend vertically on the common pattern 7 with a central conductor, and the periphery thereof is surrounded by an insulator IZ1. The outer periphery of the insulator IZ1 is commonly surrounded by the control emitter terminal 22. Since the control emitter terminal 22 is disposed so as to surround the outer periphery of the two insulators IZ1, it can be called an outer peripheral conductor.
[0045]
The structures of the gate terminal 21 and the current sense terminal 23 are the same as the control terminal T2 described with reference to FIG.
[0046]
Then, the gate terminal 21 and the current sense terminal 23 protrude from the insulators IZ1 provided around the gate terminal 21 and the current sense terminal 23 and the end face of the control emitter terminal 22 that commonly surrounds the two insulators IZ1. The gate terminal 21 and the current sense terminal 23 are electrically connected to a control board 30 disposed above the relay terminal board 6.
[0047]
<B-2. Effect>
As described above, in the semiconductor device module 200 according to the present invention, the gate terminal 21 and the current sense terminal 23 are the central conductors, and the periphery is surrounded by the insulator IZ1, and the two insulators IZ1 correspond to the reference potential. Since the control terminal T3 having a structure commonly surrounded by the control emitter terminal 22 to which the potential to be applied is provided, the cross-sectional area of the control emitter terminal 22 can be increased, and the gate terminal 21 and the current sense terminal are relayed when relaying the control signal. Therefore, it is possible to more effectively prevent external noise from being applied to an electrical signal (control signal) flowing through the gate terminal 21 and the current sense terminal 23.
[0048]
<C. Embodiment 3>
<C-1. Device configuration>
FIG. 5 shows a configuration of a semiconductor device module 300 as a third embodiment of the semiconductor device according to the present invention.
[0049]
In the semiconductor device modules 100 and 200 described with reference to FIGS. 1 and 4 as the first and second embodiments, the cylindrical or prismatic gate terminal 21 and the current sense terminal 23 are used as the central conductor, and the periphery thereof is insulated. In the semiconductor device module 300 shown in FIG. 5, the control terminals such as the gate terminal 210, the control emitter terminal 220, and the current sense terminal 230 having a flat plate shape are provided. It has the structure arrange | positioned so that the main surface may face.
[0050]
That is, the gate terminal 210, the control emitter terminal 220, and the current sense terminal 230, which are control terminals, are the main body portions BD21, BD22, and BD23 having a rectangular shape in plan view, and the protrusions 212 extending from one of the long sides. , 222 and 232 and projecting pieces 211, 221 and 231 extending from the other long side, and the main surfaces of the projecting pieces 211, 221 and 231 are connected to the main surface of the relay terminal board 6. To be terminal blocks 211, 221 and 231 respectively.
[0051]
The control emitter terminal 220 to which a potential corresponding to the reference potential is applied is disposed in the center, and the gate terminal 210 and the current sense terminal 230 are disposed so that the main surfaces of the control emitter terminal 220 face each other. Has been.
[0052]
Since the terminal blocks 211, 221 and 231 need to be electrically separated from each other, the projecting pieces 211, 221 and 231 extend from different positions on one of the long sides of the main body portions BD21, BD22 and BD23. Existing and bent so as not to contact each other.
[0053]
Also, no conductor pattern is provided on the relay terminal board 6 so that the terminal blocks 211, 221 and 231 are connected in common, and the terminal blocks 211, 221 and 231 are respectively relayed by soldering or the like. Although partial conductor patterns for connection on the terminal board 6 are provided, they need only have the same area as the terminal blocks 211, 221 and 231, so that the terminal blocks 211, 221 and 231 are provided. It is hidden by the placement of and is not shown in the figure.
[0054]
The projecting pieces 212, 222 and 232 are electrically connected to the control board 30 disposed above the relay terminal board 6.
[0055]
The molding resin is filled between the main body portions BD21, BD22, and BD23 of the gate terminal 210, the control emitter terminal 220, and the current sense terminal 230 when the resin package 10 is molded. A structure having a gap may be used at the stage, but an insulating material may be sandwiched in order to perform reliable insulation.
[0056]
FIG. 5 shows a view of the gate terminal 210, the control emitter terminal 220, and the current sense terminal 230 as seen from the direction of arrow B in FIG. As shown in FIG. 5, the main surface interval between the main surfaces BD21 and BD22 and between the main surfaces of the main body portions BD22 and BD23 is made constant by sandwiching the insulator IZ2. And reliable insulation is possible.
[0057]
The insulator IZ2 may be formed by applying and curing a gel-like insulating material, or may be configured to sandwich an insulating sheet.
[0058]
Since other configurations are the same as those of the semiconductor device module 100 described with reference to FIG. 1, illustration and description thereof are omitted.
[0059]
<C-2. Effect>
As described above, in the semiconductor device module 300 according to the present invention, the control emitter terminal 220 to which a potential corresponding to the reference potential is applied is arranged in the center, and the main surfaces of the control emitter terminal 220 are respectively main surfaces. Since the gate terminal 210 and the current sense terminal 230 are disposed so as to face each other, when relaying the control signal, the gate terminal 210 and the control emitter terminal 220, and the control emitter terminal 220 and the current sense terminal 230 are the transmission antenna and the reception antenna. Thus, the noise generated due to the switching operation of the IGBT element 1 can be prevented from being applied to the electrical signal (control signal) flowing through the gate terminal 210 and the current sense terminal 230. Further, by narrowing the main surface spacing of each terminal to such an extent that dielectric breakdown does not occur, it is possible to prevent external noise from being applied to an electrical signal (control signal) flowing through the gate terminal 210 and the current sense terminal 230.
[0060]
In the above description, the case where there are three control terminals has been described. However, even when the number of control terminals exceeds three, a plurality of control emitter terminals 220 are provided so as to face both main surfaces. By providing the remaining control terminals, it is possible to prevent the transmission emitter and the reception antenna from being in a relationship between the control emitter terminal 220 and the other control terminals.
[0061]
<D. Modification>
In the semiconductor device modules 100 to 300 according to the first to third embodiments described above, the IPM including the control board 30 is described. However, the control board 30 may be disposed outside.
[0062]
In that case, the control board 30 is disposed on the upper surface of the resin package 10, and, for example, the gate terminals 21 and the current sense terminals 23 of the control terminals T1 and T2 shown in FIG. The gate terminal 21 and the current sense terminal 23 of the control terminal T3 shown in FIG. 4 are connected to protrude from the upper surface of the resin package 10, and the gate terminal 210, the control emitter terminal 220 and the current sense shown in FIG. The projecting pieces 212, 222, and 232 of the terminal 230 project from the upper surface of the resin package 10 and are connected. With such a configuration, the semiconductor device module can be reduced in size.
[0063]
Moreover, in the semiconductor device modules 100 to 300 of the first to third embodiments, as illustrated in FIG. 8, the description has been given as the configuration including a pair of power semiconductor elements of the IGBT element 1 and the diode element 2. The set of the element 1 and the diode element 2 is not limited to one set, and a plurality of sets may be connected in parallel, or may be configured in series.
[0064]
For example, as shown in FIG. 7, IGBT elements 1A and 1B are connected in series, and diode elements 1A and 1B are connected in antiparallel to IGBT elements 1A and 1B, respectively.
[0065]
The collector of the IGBT element 1A is connected to the main collector terminal plate 121, and the emitter of the IGBT element 1A and the collector of the IGBT element 1B are commonly connected to the output terminal plate 122. The output terminal plate 122 is connected to an inductive load such as a motor provided outside. The emitter of the IGBT element 1B is connected to the main emitter terminal plate 123.
[0066]
The emitters of IGBT elements 1A and 1B are connected to control emitter terminals 22A and 22B, respectively. Current sense electrodes of IGBT elements 1A and 1B are connected to current sense terminals 23A and 23B, respectively. The gates are connected to gate terminals 21A and 21B, respectively.
[0067]
In such a configuration, the gate terminal 21A, the control emitter terminal 22A and the current sense terminal 23A form one set, and the gate terminal 21B, the control emitter terminal 22B and the current sense terminal 23B have one set. Since a group is formed, the control terminal configuration shown in the semiconductor device modules 100 to 300 of the first to third embodiments may be adopted in each group of control terminals.
[0068]
【The invention's effect】
According to the semiconductor device of the first aspect of the present invention, the center conductor through which the control signal flows is surrounded by the insulator, and the outer periphery of the insulator is surrounded by the outer conductor to which a potential corresponding to the reference potential is applied. Thus, the center conductor can be prevented from becoming an antenna, and noise generated due to the switching operation of the power semiconductor element can be prevented from being applied to the control signal when the control signal is relayed. Further, the central conductor can be electrically shielded, and external noise can be prevented from being applied to the control signal.
[0069]
According to the semiconductor device of the second aspect of the present invention, since the outer conductor is arranged on each of the plurality of control terminals, the independence of each control terminal can be maintained, and the arrangement of the control terminals can be maintained. You can do it freely.
[0070]
According to the semiconductor device of the third aspect of the present invention, the periphery of the plurality of central conductors is respectively surrounded by the insulator, and the outer periphery of the plurality of insulators is shared by the peripheral conductor to which a potential corresponding to the reference potential is applied. Since the control terminal with the enclosed structure is provided, the cross-sectional area of the outer peripheral conductor can be widened, and when the control signal is relayed, the electrical shield performance for the plurality of center conductors can be enhanced, and external noise is generated by the plurality of center conductors. It can prevent more effectively that it is applied to the control signal which flows into.
[0071]
According to the semiconductor device of the fourth aspect of the present invention, since the end face of the outer conductor is directly connected to the conductor pattern, the contact area between the outer conductor and the conductor pattern can be increased, and the contact resistance can be reduced.
[0074]
According to the semiconductor device of the fifth aspect of the present invention, the control board on which the control circuit for controlling the driving of the power semiconductor element is provided is built in, and the control signal transmission / reception unit is directly connected to the control board. Therefore, the signal path from the power semiconductor element to the control board is shortened, and the possibility that noise is applied to the control signal can be reduced.
[0075]
According to the semiconductor device of the sixth aspect of the present invention, since the control board on which the control circuit for controlling the driving of the power semiconductor element is disposed is provided outside the resin package, the semiconductor device module can be reduced in size. .
[Brief description of the drawings]
FIG. 1 is a perspective view showing an internal configuration of a semiconductor device module according to a first embodiment of the present invention.
FIG. 2 is a sectional view showing a configuration of a control terminal of the semiconductor device module according to the first embodiment of the present invention.
FIG. 3 is a perspective view showing a configuration of a control terminal of the semiconductor device module according to the first embodiment of the present invention.
FIG. 4 is a perspective view showing an internal configuration of a semiconductor device module according to a second embodiment of the present invention.
FIG. 5 is a perspective view showing an internal configuration of a semiconductor device module according to a third embodiment of the present invention.
FIG. 6 is a side view showing a configuration of a control terminal of a semiconductor device module according to a third embodiment of the present invention.
FIG. 7 is a diagram showing an example of a combination of power semiconductor elements.
FIG. 8 is a diagram illustrating a connection relationship between a power semiconductor element and a control terminal.
FIG. 9 is a diagram showing a problem of a conventional semiconductor device module.
[Explanation of symbols]
21,210 Gate terminal, 22,220 Control emitter terminal, 23,230 Current sense terminal, 211,231 terminal block, T1, T2, T3 control terminal, IZ1, IZ2 insulator.

Claims (6)

パッケージの底面部に収納された電力用半導体素子と、
前記電力用半導体素子に電気的に接続され、前記電力用半導体素子の制御のための制御信号の中継に使用される制御端子と、を備え、
前記制御端子は、
前記底面部に対して垂直方向に延在するように配設され、前記制御信号が流れる中心導体と、
前記中心導体を取り囲むように配設された絶縁体と、
前記絶縁体を取り囲むように配設された外周導体と、を有し、
前記外周導体は、前記電力用半導体素子の駆動に際して、基準電位に相当する電位が与えられ、
前記中心導体の前記底面部側の第１の端部は、前記外周導体と絶縁を保って前記外周導体の側面から突出して前記電力用半導体素子との電気的接続のための端子台をなし、
前記中心導体の前記底面部とは反対側の第２の端部は、前記絶縁体および前記外周導体の端面よりも突出し、前記制御信号の授受部をなす、半導体装置。A power semiconductor element housed in the bottom of the package;
A control terminal electrically connected to the power semiconductor element and used for relaying a control signal for controlling the power semiconductor element;
The control terminal is
A central conductor disposed so as to extend in a direction perpendicular to the bottom surface portion and through which the control signal flows;
An insulator disposed to surround the central conductor;
An outer peripheral conductor disposed so as to surround the insulator,
The outer peripheral conductor is given a potential corresponding to a reference potential when driving the power semiconductor element,
The first end portion on the bottom surface side of the center conductor is a terminal block for electrical connection with the power semiconductor element protruding from the side surface of the outer conductor while maintaining insulation from the outer conductor,
A semiconductor device, wherein a second end portion of the center conductor opposite to the bottom surface portion protrudes from end surfaces of the insulator and the outer peripheral conductor and serves as a control signal transmitting / receiving portion. 前記制御端子は複数であって、
前記複数の制御端子のそれぞれは、単一の前記中心導体、前記絶縁体および前記外周導体を備える、請求項１記載の半導体装置。The control terminal is plural,
The semiconductor device according to claim 1, wherein each of the plurality of control terminals includes a single central conductor, the insulator, and the outer peripheral conductor. 前記中心導体は複数であって、
前記絶縁体は、前記複数の中心導体を個々に取り囲むように複数配設され、
前記外周導体は、前記複数の絶縁体を共通して取り囲むように配設される、請求項１記載の半導体装置。The center conductor is plural,
A plurality of the insulators are disposed so as to individually surround the plurality of central conductors,
The semiconductor device according to claim 1, wherein the outer peripheral conductor is disposed so as to surround the plurality of insulators in common. 前記制御端子は、
前記パッケージの前記底面部に平行に配設された導体パターン上に配設され、
前記外周導体の端面が前記導体パターンに直接に接続される、請求項１記載の半導体装置。The control terminal is
Disposed on a conductor pattern disposed in parallel to the bottom surface of the package;
The semiconductor device according to claim 1, wherein an end face of the outer peripheral conductor is directly connected to the conductor pattern. 前記半導体装置は、
前記電力用半導体素子の駆動制御を行う制御回路が配設された制御基板を内蔵してさらに備え、
前記授受部は、前記制御基板に直接に接続される、請求項１記載の半導体装置。 The semiconductor device includes:
Further comprising a control board on which a control circuit for controlling the driving of the power semiconductor element is provided,
The semiconductor device according to claim 1, wherein the transfer unit is directly connected to the control board . 前記半導体装置は、
前記電力用半導体素子の駆動制御を行う制御回路が配設された制御基板を、前記パッケージの外部においてさらに備え、
前記授受部は、前記パッケージから突出して前記制御基板に直接に接続される、請求項１記載の半導体装置。 The semiconductor device includes:
A control board on which a control circuit for controlling the driving of the power semiconductor element is disposed, and further provided outside the package;
The transfer unit is configured to protrude from the package are connected directly to the control board, a semiconductor device according to claim 1, wherein.
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