JP2005150443A - Laminated semiconductor device and its manufacturing method - Google Patents

Laminated semiconductor device and its manufacturing method Download PDF

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JP2005150443A
JP2005150443A JP2003386563A JP2003386563A JP2005150443A JP 2005150443 A JP2005150443 A JP 2005150443A JP 2003386563 A JP2003386563 A JP 2003386563A JP 2003386563 A JP2003386563 A JP 2003386563A JP 2005150443 A JP2005150443 A JP 2005150443A
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intermediate member
circuit board
semiconductor device
bare chip
circuit boards
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Naoki Sakota
直樹 迫田
Koki Kitaoka
幸喜 北岡
Akira Yoshida
陽 吉田
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Sharp Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01087—Francium [Fr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Abstract

<P>PROBLEM TO BE SOLVED: To laminate electronic components and magnetically seal between the facing electronic components. <P>SOLUTION: On one face of an intermediate member 15, a first circuit board 11 mounted with first and third bare chip semiconductor elements 13, 20 on the front and rear faces are laminated via a jointing member 16a so that the first bare chip semiconductor element 13 is opposed to a sealed pattern 17a. On the other face of the intermediate member 15, a second circuit board 12 mounted with a second bare chip semiconductor element 14 is laminated via a jointing member 16b so that the second bare chip semiconductor element 14 is opposed to a sealed pattern 17b. Thus, a multilayer structure is formed, a space between the first and second bare chip semiconductor elements 13 and 14 is sealed, and the first circuit substrate 11 is electrically connected to the second circuit board 12 by a jointing member 16. Namely, electronic components can be laminated and can magnetically seal in between the facing electronic components. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

この発明は、半導体集積回路や受動素子等の電子部品を高密度に実装可能な積層型半導体装置およびその製造方法に関する。   The present invention relates to a stacked semiconductor device capable of mounting electronic components such as semiconductor integrated circuits and passive elements at high density, and a method for manufacturing the same.

近年、ハイエンドプロセッサから携帯電話に代表される携帯機器に至るまでの急速な普及の原動力として、一つには機器の飛躍的な小型化がある。これら電子機器の小型化,軽量化,薄型化に伴って、電子機器に使用される半導体装置にも小型化,薄型化が要求されてきている。このような小型化,薄型化の要求に対処すべく、半導体装置においては、ベアチップ半導体素子を用いたマルチチップモジュール(ＭＣＭ)が実用化されている。   In recent years, as a driving force for rapid spread from high-end processors to portable devices typified by mobile phones, one is the dramatic downsizing of devices. As these electronic devices become smaller, lighter, and thinner, semiconductor devices used in electronic devices are also required to be smaller and thinner. In order to meet such demands for miniaturization and thinning, multichip modules (MCM) using bare chip semiconductor elements have been put into practical use in semiconductor devices.

この種の半導体装置では、回路基板に個々の半導体チップがモールド成形されることはなく、複数のベアチップ半導体素子が同一の回路基板上に平面的に並べられて配置されている。一方、他方の面には、抵抗やコンデンサ等の電子部品が実装されており、部品搭載面積に限界が生じ始めている。そこで、各回路基板を積層して部品搭載面積の高密度化を図ることが試みられている。   In this type of semiconductor device, individual semiconductor chips are not molded on a circuit board, and a plurality of bare chip semiconductor elements are arranged in a plane on the same circuit board. On the other hand, electronic components such as resistors and capacitors are mounted on the other surface, and there is a limit to the component mounting area. Therefore, attempts have been made to increase the component mounting area by stacking circuit boards.

また、複数のベアチップ半導体素子を同一の回路基板上に実装した場合には、複数のベアチップ半導体素子間で高周波信号が相互に干渉してノイズが発生したり、特性が悪化して正常に回路が動作しなくなるという問題点が生ずる。この問題点に関しては、個々のベアチップ半導体素子に金属の筐体を覆い被せてシールドするようにしている。   In addition, when multiple bare chip semiconductor elements are mounted on the same circuit board, high frequency signals interfere with each other between the multiple bare chip semiconductor elements to generate noise, or the characteristics deteriorate and the circuit normally operates. There is a problem that it does not work. Regarding this problem, each bare chip semiconductor element is covered with a metal casing and shielded.

上述のようなベアチップ半導体素子間での高周波信号の相互干渉の問題に対して、図８に示すような電磁シールドを図る半導体素子の実装構造が提案されている(例えば、特許文献１参照)。図８において、１は実装用基板、２は信号配線、３は接続パッド、４はベアチップ半導体素子、５は蓋基板、６は接着剤、７は導体端子、８は間隙設定部材、９は封止樹脂、１０は絶縁膜である。   In order to deal with the problem of mutual interference of high-frequency signals between bare chip semiconductor elements as described above, a semiconductor element mounting structure for electromagnetic shielding as shown in FIG. 8 has been proposed (see, for example, Patent Document 1). In FIG. 8, 1 is a mounting substrate, 2 is a signal wiring, 3 is a connection pad, 4 is a bare chip semiconductor element, 5 is a lid substrate, 6 is an adhesive, 7 is a conductor terminal, 8 is a gap setting member, and 9 is a seal. Stop resin 10 is an insulating film.

図８に示すように、上記ベアチップ半導体素子４は導電性の蓋基板５上に接着剤６によってダイボンドされており、ベアチップ半導体素子４と実装用基板１上の接続パッド３とは、金バンプや半田バンプ等の接続バンプあるいは導電性ペーストによって形成された導体端子７を介して電気的に接続されている。また、蓋基板５の下面周辺部には間隙設定部材８を複数個設置し、実装用基板１と蓋基板５とを封止樹脂９によって接合して封止することによって、電磁シールドを図っている。   As shown in FIG. 8, the bare chip semiconductor element 4 is die-bonded on a conductive lid substrate 5 with an adhesive 6, and the bare chip semiconductor element 4 and the connection pad 3 on the mounting substrate 1 are made of gold bumps, They are electrically connected via connection terminals such as solder bumps or conductive terminals 7 formed of conductive paste. Further, a plurality of gap setting members 8 are provided on the periphery of the lower surface of the lid substrate 5, and the mounting substrate 1 and the lid substrate 5 are joined and sealed with a sealing resin 9 to achieve an electromagnetic shield. Yes.

しかしながら、上記従来の特許文献１に開示された半導体素子の実装構造においては、以下のような問題がある。すなわち、図８に示すように、ベアチップ半導体素子４を実装用基板１と蓋基板５との間に封止樹脂９によって封止するようにしている。したがって、このような実装構造では、ベアチップ半導体素子４の実装面積を積層方向に増加させることができないのである。
特開２０００‐３１３１２号公報 However, the semiconductor element mounting structure disclosed in Patent Document 1 has the following problems. That is, as shown in FIG. 8, the bare chip semiconductor element 4 is sealed between the mounting substrate 1 and the lid substrate 5 by the sealing resin 9. Therefore, with such a mounting structure, the mounting area of the bare chip semiconductor element 4 cannot be increased in the stacking direction.
Japanese Patent Laid-Open No. 2000-331312

そこで、この発明の課題は、電子部品を立体的に積層しても対向する電子部品間で高周波信号が相互干渉しない積層型半導体装置およびその製造方法を提供することにある。   Accordingly, an object of the present invention is to provide a stacked semiconductor device in which high-frequency signals do not interfere with each other even when electronic components are three-dimensionally stacked, and a method for manufacturing the same.

上記課題を解決するため、この発明の積層型半導体装置は、ベアチップ半導体素子等の電子部品が搭載された複数の回路基板を順次積層する際に、上記積層された複数の回路基板のうち互いに隣接している回路基板であって搭載されている電子部品が互いに対向している２つの回路基板の間に,導電層を有する中間部材を挟設し、この中間部材を介して、上記互いに隣接している２つの回路基板間を電気的に且つ機械的に接続している。   In order to solve the above-described problem, the stacked semiconductor device according to the present invention is configured such that when a plurality of circuit boards on which electronic components such as bare chip semiconductor elements are mounted are sequentially stacked, the stacked circuit boards are adjacent to each other. An intermediate member having a conductive layer is sandwiched between two circuit boards which are mounted circuit boards and mounted electronic components are facing each other. The two circuit boards are electrically and mechanically connected.

上記構成によれば、互いに隣接している２つの回路基板の間に、導電層を有する中間部材が挟設されている。したがって、上記２つの回路基板に搭載されて互いに対向している電子部品の間が、上記導電層によって磁気シールドされる。さらに、上記互いに隣接している２つの回路基板間が、上記中間部材を介して電気的に且つ機械的に接続されている。したがって、上記電子部品が搭載された複数の回路基板を積層して上記電子部品の実装面積を増加させることが可能になる。その場合でも、対向する上記電子部品間で高周波信号が相互干渉することはなく、ノイズの発生や回路が正常に動作しなくなったりすることが防止される。   According to the above configuration, the intermediate member having the conductive layer is sandwiched between the two circuit boards adjacent to each other. Therefore, a space between the electronic components mounted on the two circuit boards and facing each other is magnetically shielded by the conductive layer. Further, the two adjacent circuit boards are electrically and mechanically connected via the intermediate member. Therefore, it is possible to increase the mounting area of the electronic component by stacking a plurality of circuit boards on which the electronic component is mounted. Even in this case, the high frequency signals do not interfere with each other between the electronic components facing each other, and it is possible to prevent the generation of noise and the malfunction of the circuit.

また、１実施例の積層型半導体装置では、上記中間部材の導電層は、対峙している上記電子部品の面積よりも広い面積を有すると共に、当該中間部材の表面または内部に上記電子部品と積層方向に重なり合うように形成されている。   Further, in the stacked semiconductor device of one embodiment, the conductive layer of the intermediate member has an area larger than that of the facing electronic component, and the electronic component is laminated on the surface or inside of the intermediate member. It is formed to overlap in the direction.

この実施例によれば、上記中間部材の導電層は、上記電子部品よりも広い面積を有して上記電子部品と積層方向に重なり合うように形成されている。したがって、上記中間部材による磁気シールド効果がより高められる。   According to this embodiment, the conductive layer of the intermediate member has a larger area than the electronic component and is formed so as to overlap the electronic component in the stacking direction. Therefore, the magnetic shielding effect by the intermediate member is further enhanced.

また、１実施例の積層型半導体装置では、上記中間部材の導電層は、上記互いに隣接している２つの回路基板のグランド端子と上記互いに対向している電子部品のグランド端子とに接続されている。   In the stacked semiconductor device of one embodiment, the conductive layer of the intermediate member is connected to the ground terminals of the two circuit boards adjacent to each other and the ground terminals of the electronic components facing each other. Yes.

この実施例によれば、上記中間部材の導電層は、上記両回路基板および両電子部品のグランド端子を介して接地されている。したがって、互いに対向している上記電子部品の間が、上記導電層によって、確実に磁気シールドされる。   According to this embodiment, the conductive layer of the intermediate member is grounded via the ground terminals of both the circuit boards and both electronic components. Therefore, between the electronic components facing each other, the magnetic shielding is surely performed by the conductive layer.

また、１実施例の積層型半導体装置では、上記電子部品は、上記回路基板にフリップチップ実装されることによって搭載されている。   In the stacked semiconductor device of one embodiment, the electronic component is mounted on the circuit board by flip chip mounting.

この実施例によれば、上記電子部品が搭載された複数の回路基板が積層されて、上記電子部品の実装面積が増加されるに加えて、上記電子部品が回路基板にフリップチップ実装されている。したがって、フェイスアップ実装やワイヤボンディング等に比して高密度実装化が図られて、電子機器のより一層の小型化を図ることが可能になる。   According to this embodiment, a plurality of circuit boards on which the electronic components are mounted are stacked to increase the mounting area of the electronic components, and the electronic components are flip-chip mounted on the circuit board. . Therefore, high-density mounting is achieved as compared with face-up mounting, wire bonding, and the like, and the electronic device can be further downsized.

また、この発明の積層型半導体装置の製造方法は、電子部品が搭載された複数の回路基板を順次積層する際に、上記電子部品を上記回路基板上に実装し、絶縁体で成る中間部材に導電層を形成し、少なくとも２つの上記回路基板と１つの上記中間部材とを用いて、上記２つの上記回路基板のうちの一方である第１回路基板を,この第１回路基板上の電子部品を当該中間部材の導電層に対向させて,当該中間部材の一面に接合部材を介して積層すると共に接合し、上記２つの上記回路基板のうちの他方である第２回路基板を,この第２回路基板上の電子部品を当該中間部材の導電層に対向させて,当該中間部材の他面に接合部材を介して積層すると共に接合している。   Also, in the method of manufacturing a stacked semiconductor device according to the present invention, when sequentially stacking a plurality of circuit boards on which electronic components are mounted, the electronic components are mounted on the circuit board, and an intermediate member made of an insulator is used. A conductive layer is formed, and at least two circuit boards and one intermediate member are used, and a first circuit board that is one of the two circuit boards is used as an electronic component on the first circuit board. The second circuit board, which is the other of the two circuit boards, is bonded to the second member of the two circuit boards by laminating and bonding to one surface of the intermediate member with a bonding member facing the conductive layer of the intermediate member. The electronic component on the circuit board is opposed to the conductive layer of the intermediate member, and is laminated and bonded to the other surface of the intermediate member via a bonding member.

上記構成によれば、互いに隣接している２つの回路基板の間に、導電層を有する中間部材が挟設される。したがって、上記２つの回路基板に搭載されて互いに対向している電子部品の間が、上記導電層によって磁気シールドされる。さらに、上記互いに隣接している２つの回路基板間が、上記中間部材を介して電気的に且つ機械的に接続されている。したがって、上記電子部品が搭載された複数の回路基板を積層して、上記電子部品の実装面積を増加させることが可能になる。その場合でも、対向する上記電子部品間で高周波信号が相互干渉することはなく、ノイズの発生や回路が正常に動作しなくなったりすることが防止される。   According to the above configuration, the intermediate member having the conductive layer is sandwiched between the two circuit boards adjacent to each other. Therefore, a space between the electronic components mounted on the two circuit boards and facing each other is magnetically shielded by the conductive layer. Further, the two adjacent circuit boards are electrically and mechanically connected via the intermediate member. Accordingly, a plurality of circuit boards on which the electronic components are mounted can be stacked to increase the mounting area of the electronic components. Even in this case, the high frequency signals do not interfere with each other between the electronic components facing each other, and it is possible to prevent the generation of noise and the malfunction of the circuit.

以上より明らかなように、この発明の積層型半導体装置は、互いに対向する電子部品の間に導電層を有する中間部材を挟設し、この中間部材を介して、互いに対向する２つの回路基板間を電気的に且つ機械的に接続したので、上記互いに対向する電子部品間を電磁シールドすることができる。したがって、上記電子部品がノイズを発生したり誤動作することを防止することができる。さらに、上記電子部品が搭載された複数の回路基板を積層して上記電子部品の実装面積を増加させることが可能になる。その場合でも、上記電子部品を正常に動作させることができる。   As is clear from the above, the stacked semiconductor device of the present invention has an intermediate member having a conductive layer interposed between electronic components facing each other, and between the two circuit boards facing each other through the intermediate member. Are electrically and mechanically connected, so that the above-mentioned electronic components facing each other can be electromagnetically shielded. Therefore, it is possible to prevent the electronic component from generating noise or malfunctioning. Further, it is possible to increase the mounting area of the electronic component by stacking a plurality of circuit boards on which the electronic component is mounted. Even in that case, the electronic component can be operated normally.

さらに、対向する回路基板間に中間部材を配置するだけなので高さが大幅に増大することがなく、薄型な積層半導体装置を維持することができる。   Furthermore, since the intermediate member is only disposed between the opposing circuit boards, the height does not increase significantly, and a thin laminated semiconductor device can be maintained.

また、この発明の積層型半導体装置の製造方法は、少なくとも第１回路基板上の電子部品を、中間部材の導電層に対向させて接合部材を介して積層して接合し、第２回路基板上の電子部品を、上記中間部材の導電層に対向させて接合部材を介して積層して接合するので、互いに対向する電子部品の間に導電層を有する中間部材を挟設した積層型半導体装置を作成することができる。   According to the method of manufacturing the stacked semiconductor device of the present invention, at least the electronic components on the first circuit board are stacked and bonded via the bonding member so as to face the conductive layer of the intermediate member, and on the second circuit board. Since the electronic component is laminated and bonded via the bonding member so as to face the conductive layer of the intermediate member, a stacked semiconductor device in which an intermediate member having a conductive layer is interposed between the electronic components facing each other is obtained. Can be created.

したがって、上記電子部品が搭載された複数の回路基板を積層して上記電子部品の実装面積を増加させるに際して、互いに対向する電子部品間を電磁シールドし、上記電子部品がノイズを発生したり誤動作することを防止できる。   Therefore, when a plurality of circuit boards on which the electronic components are mounted are stacked to increase the mounting area of the electronic components, the electronic components facing each other are electromagnetically shielded, and the electronic components generate noise or malfunction. Can be prevented.

以下、この発明を図示の実施の形態により詳細に説明する。尚、以下の各実施の形態においては、積層される回路基板に電子部品の１例としてべアチップ半導体素子を実装する場合を例示しているが、この発明における電子部品は、これに限定されるものではない。   Hereinafter, the present invention will be described in detail with reference to the illustrated embodiments. In each of the following embodiments, a case where a bear chip semiconductor element is mounted as an example of an electronic component on a circuit board to be laminated is illustrated, but the electronic component in the present invention is limited to this. It is not a thing.

・第１実施の形態
図１は、本実施の形態における積層型半導体装置の一例を模式的に示す断面図である。この積層型半導体装置２１は、第１のベアチップ半導体素子がフリップチップ実装された第１の回路基板と、第２のベアチップ半導体素子が実装された第２の回路基板とを対向させた際に、第１のベアチップ半導体素子の駆動電圧と第２のベアチップ半導体素子の駆動電圧とに差がある場合には、第１,第２のベアチップ半導体素子間で電磁干渉が生じ、ベアチップ半導体素子が誤動作する。これを回避するために、上記両回路基板の接続端子に電気的に導通接続されている導電層を有する中間部材を上記両回路基板の間に配置したものである。 First Embodiment FIG. 1 is a cross-sectional view schematically showing an example of a stacked semiconductor device according to the present embodiment. In the stacked semiconductor device 21, when the first circuit board on which the first bare chip semiconductor element is flip-chip mounted and the second circuit board on which the second bare chip semiconductor element is mounted face each other, When there is a difference between the drive voltage of the first bare chip semiconductor element and the drive voltage of the second bare chip semiconductor element, electromagnetic interference occurs between the first and second bare chip semiconductor elements, and the bare chip semiconductor element malfunctions. . In order to avoid this, an intermediate member having a conductive layer electrically connected to the connection terminals of both circuit boards is disposed between the circuit boards.

図１において、１１は第１回路基板、１２は第２回路基板、１３は第１ベアチップ半導体素子、１４は第２ベアチップ半導体素子、１５は中間部材、１６は両回路基板１１,１２間の接合部材、１７は導電層、１８は外部端子、１９はバンプ、２０は第３ベアチップ半導体素子である。ここで、第１,第２回路基板１１,１２の材料としては、ガラス布エポキシ樹脂またはアラミド繊維不織布エポキシ樹脂や液晶ポリマー樹脂等の絶縁材料で構成された有機基板を用いる。また、アルミナセラミックス等の絶縁材料で構成された無機基板を用いても構わない。   In FIG. 1, 11 is a first circuit board, 12 is a second circuit board, 13 is a first bare chip semiconductor element, 14 is a second bare chip semiconductor element, 15 is an intermediate member, and 16 is a joint between both circuit boards 11 and 12. A member, 17 is a conductive layer, 18 is an external terminal, 19 is a bump, and 20 is a third bare chip semiconductor element. Here, as the material of the first and second circuit boards 11 and 12, an organic substrate made of an insulating material such as a glass cloth epoxy resin, an aramid fiber nonwoven fabric epoxy resin, or a liquid crystal polymer resin is used. An inorganic substrate made of an insulating material such as alumina ceramics may be used.

本実施の形態においては、図１に示すように、上記第１,第２ベアチップ半導体素子１３,１４を中間部材１５のシールド用の導電部材１７a,１７bに対向させて、接合部材１６を介して、電子部品が実装された第１,第２回路基板１１,１２を配置する。そして、接合部材１６によって第１,第２回路基板１１,１２間を電気的に接続して、電子部品の実装面積を積層方向に立体的に増加しつつ電磁シールドが可能なようにしている。   In the present embodiment, as shown in FIG. 1, the first and second bare chip semiconductor elements 13 and 14 are opposed to the shielding conductive members 17a and 17b of the intermediate member 15 via the joining member 16. First and second circuit boards 11 and 12 on which electronic components are mounted are arranged. Then, the first and second circuit boards 11 and 12 are electrically connected by the joining member 16 so as to enable electromagnetic shielding while increasing the mounting area of the electronic component in the stacking direction in a three-dimensional manner.

上記第１,第２回路基板１１,１２は、上記第１,第２ベアチップ半導体素子１３,１４等の電子部品が高密度に実装されている基板である。第１,第２ベアチップ半導体素子１３,１４の厚みは１５０μmであり、第１,第２回路基板１１,１２の厚みは約０.５mmである。また、図１に示す積層型半導体装置２１の厚みは約２mmである。   The first and second circuit boards 11 and 12 are boards on which electronic components such as the first and second bare chip semiconductor elements 13 and 14 are mounted at a high density. The thickness of the first and second bare chip semiconductor elements 13 and 14 is 150 μm, and the thickness of the first and second circuit boards 11 and 12 is about 0.5 mm. The thickness of the stacked semiconductor device 21 shown in FIG. 1 is about 2 mm.

一側の面に第１ベアチップ半導体素子１３が実装される一方、他側の面に第３ベアチップ半導体素子２０が実装された第１回路基板１１が、接合部材１６aを挟んで中間部材１５の一方の面上に積層されると共に、第１回路基板１１と中間部材１５との間が接合部材１６aによって電気的に接続されている。また、中間部材１５の他方の面上には、他の接合部材１６bを挟んで、一側の面に第２ベアチップ半導体素子１４が実装された第２回路基板１２が積層されると共に、第２回路基板１２と中間部材１５との間が接合部材１６bによって電気的に接続されている。こうして、積層型半導体装置２１は多層構造を成している。   The first circuit board 11 on which the first bare chip semiconductor element 13 is mounted on one surface and the third bare chip semiconductor element 20 is mounted on the other surface is one of the intermediate members 15 with the bonding member 16a interposed therebetween. The first circuit board 11 and the intermediate member 15 are electrically connected by a bonding member 16a. Further, on the other surface of the intermediate member 15, the second circuit board 12 on which the second bare chip semiconductor element 14 is mounted on one surface is stacked with the other bonding member 16 b interposed therebetween, and the second circuit board 12 is stacked. The circuit board 12 and the intermediate member 15 are electrically connected by a bonding member 16b. Thus, the stacked semiconductor device 21 has a multilayer structure.

つまり、上記接合部材１６aは第１回路基板１１と中間部材１５との間に設けられる一方、接合部材１６bは第２回路基板１２と中間部材１５との間に設けられており、少なくとも第１,第２回路基板１１,１２や中間部材１５を保持する機能と、第１,第２回路基板１１,１２間を電気的に接続する機能と、第１,第２ベアチップ半導体素子１３,１４間を電磁シールドする機能との３つの機能を有している。そして、接合部材１６a,１６bによって画定される領域内であって、中間部材１５における少なくとも第１,第２ベアチップ半導体素子１３,１４に対向する側(つまり、中間部材１５の表層または内層)には、所定の広さのシールド用の導電層１７が設けられる。図１においては、導電層１７を、中間部材１５の表面と裏面とに形成された銅箔パターン(以下、シールドパターンと言う)１７a,１７bで構成すると共に、後に詳述するように接地している。尚、シールドパターン１７a,１７bは、中間部材１５の形成時にランド電極や配線パターンと同時に形成される。   That is, the joining member 16a is provided between the first circuit board 11 and the intermediate member 15, while the joining member 16b is provided between the second circuit board 12 and the intermediate member 15, and at least the first, The function of holding the second circuit boards 11 and 12 and the intermediate member 15, the function of electrically connecting the first and second circuit boards 11 and 12, and the connection between the first and second bare chip semiconductor elements 13 and 14 It has three functions, namely the function of electromagnetic shielding. In the region defined by the joining members 16a and 16b and on the side of the intermediate member 15 facing at least the first and second bare chip semiconductor elements 13 and 14 (that is, the surface layer or the inner layer of the intermediate member 15). A conductive layer 17 for shielding having a predetermined area is provided. In FIG. 1, the conductive layer 17 is composed of copper foil patterns (hereinafter referred to as shield patterns) 17a and 17b formed on the front and back surfaces of the intermediate member 15, and grounded as will be described in detail later. Yes. The shield patterns 17a and 17b are formed simultaneously with the land electrode and the wiring pattern when the intermediate member 15 is formed.

このシールドパターン１７a,１７bの面積は、電磁シールド効果を上げるために、第１,第２ベアチップ半導体素子１３,１４の中間部材１５への投影面積よりも広い方が好ましい。本実施の形態においては、第１回路基板１１下面の第１ベアチップ半導体素子１３を中間部材１５上面のシールドパターン１７aによって電磁シールドすることができ、同様に、第２回路基板１２上面の第２ベアチップ半導体素子１４を中間部材１５下面のシールドパターン１７bによって電磁シールドすることができるようになっている。   The area of the shield patterns 17a and 17b is preferably wider than the projected area of the first and second bare chip semiconductor elements 13 and 14 onto the intermediate member 15 in order to increase the electromagnetic shielding effect. In the present embodiment, the first bare chip semiconductor element 13 on the lower surface of the first circuit board 11 can be electromagnetically shielded by the shield pattern 17a on the upper surface of the intermediate member 15. Similarly, the second bare chip on the upper surface of the second circuit board 12 can be used. The semiconductor element 14 can be electromagnetically shielded by the shield pattern 17b on the lower surface of the intermediate member 15.

また、上記第１,第２ベアチップ半導体素子１３,１４等の電子部品は、第１,第２回路基板１１,１２における一方の面のみに実装されるものではなく、上記電子部品の密度を高めるために、第１,第２回路基板１１,１２における両面に実装してもよい。例えば、一方の面にベアチップ半導体素子を実装し、他方の面にチップ状の抵抗やコンデンサ等の受動素子を実装する場合や、図１に示す第１回路基板１１のように、両面に第１,第３ベアチップ半導体素子１３,２０を実装する場合も含まれている。   Further, the electronic components such as the first and second bare chip semiconductor elements 13 and 14 are not mounted only on one surface of the first and second circuit boards 11 and 12, and the density of the electronic components is increased. Therefore, it may be mounted on both surfaces of the first and second circuit boards 11 and 12. For example, when a bare chip semiconductor element is mounted on one surface and a passive element such as a chip-like resistor or capacitor is mounted on the other surface, or the first circuit board 11 shown in FIG. The case where the third bare chip semiconductor elements 13 and 20 are mounted is also included.

このように、本実施形態の積層型半導体装置２１によれば、上記中間部材１５の一方の面側には、第１,第３ベアチップ半導体素子１３,２０が実装された第１回路基板１１を、第１ベアチップ半導体素子１３を中間部材１５の上記一方の面に形成されたシールドパターン１７aに対向させて、接合部材１６aを介して積層している。同様に、中間部材１５の他方の面側には、第２ベアチップ半導体素子１４が実装された第２回路基板１２を、第２ベアチップ半導体素子１４を中間部材１５の上記他方の面に形成されたシールドパターン１７bに対向させて、接合部材１６bを介して積層している。こうして、第１回路基板１１と第２回路基板１２とを中間部材１５の両面に積層して多層構造を成すと共に、第１ベアチップ半導体素子１３と第２ベアチップ半導体素子１４との間をシールドし、第１回路基板１１と第２回路基板１２との間を接合部材１６によって電気的に接続している。   As described above, according to the stacked semiconductor device 21 of the present embodiment, the first circuit board 11 on which the first and third bare chip semiconductor elements 13 and 20 are mounted is provided on one surface side of the intermediate member 15. The first bare chip semiconductor element 13 is laminated via the bonding member 16a so as to face the shield pattern 17a formed on the one surface of the intermediate member 15. Similarly, the second circuit board 12 on which the second bare chip semiconductor element 14 is mounted is formed on the other surface side of the intermediate member 15, and the second bare chip semiconductor element 14 is formed on the other surface of the intermediate member 15. The shield pattern 17b is opposed so as to be laminated via a joining member 16b. Thus, the first circuit board 11 and the second circuit board 12 are laminated on both surfaces of the intermediate member 15 to form a multilayer structure, and the space between the first bare chip semiconductor element 13 and the second bare chip semiconductor element 14 is shielded, The first circuit board 11 and the second circuit board 12 are electrically connected by a bonding member 16.

したがって、上記所定の広さのシールドパターン１７a,１７bと接合部材１６a,１６bとによって電気的にシールドされた第１,第２ベアチップ半導体素子１３,１４の実装面積を積層方向に立体的に増加させることができ、第１,第２のベアチップ半導体素子を回路基板上に平面に配置し、各ベアチップ半導体素子を金属蓋等で電磁シールドする場合に比して、積層方向に第１,第２ベアチップ半導体素子１３,１４を高密度に実装することができる。更に加えて、各積層間に設けられたシールドパターン１７a,１７bによって、第１,第２回路基板１１,１２に形成された回路間のノイズによるクロストークも防止することができる。   Therefore, the mounting area of the first and second bare chip semiconductor elements 13 and 14 electrically shielded by the shield patterns 17a and 17b having the predetermined width and the joining members 16a and 16b is increased three-dimensionally in the stacking direction. Compared to the case where the first and second bare chip semiconductor elements are arranged on a circuit board in a plane and each bare chip semiconductor element is electromagnetically shielded with a metal lid or the like, the first and second bare chips are arranged in the stacking direction. The semiconductor elements 13 and 14 can be mounted with high density. In addition, the crosstalk caused by noise between circuits formed on the first and second circuit boards 11 and 12 can be prevented by the shield patterns 17a and 17b provided between the stacked layers.

すなわち、本実施の形態の積層型半導体装置２１を用いることによって、電子機器の小型化および信頼性の向上を図ることができるのである。   That is, by using the stacked semiconductor device 21 of the present embodiment, it is possible to reduce the size and improve the reliability of the electronic device.

以下、上記積層型半導体装置２１の製造方法について説明する。図２乃至図５は、積層型半導体装置２１の製造方法の一例を示す工程図である。この例においては、中間部材１５の両面に所定の広さのシールドパターン１７a,１７bで成るシールド用の導電層１７を形成する。シールドパターン１７a,１７bは、銅箔等によってランド電極や配線パターンの形成時に同時に形成され、接地線用の端子に共通に接続されて、第１回路基板１１と第２回路基板１２とを積層する際に一括して接地される。   Hereinafter, a method for manufacturing the stacked semiconductor device 21 will be described. 2 to 5 are process diagrams showing an example of a method for manufacturing the stacked semiconductor device 21. In this example, a shield conductive layer 17 composed of shield patterns 17a and 17b having a predetermined width is formed on both surfaces of the intermediate member 15. The shield patterns 17a and 17b are formed simultaneously with the formation of land electrodes and wiring patterns with copper foil or the like, and are connected in common to the ground line terminal, and the first circuit board 11 and the second circuit board 12 are laminated. At the same time, they are grounded together.

また、第１回路基板(以下、第１回路基板１１で代表して説明するが第２回路基板１２の場合も同様)１１の一方の面には、図２に示すように、第１ベアチップ半導体素子１３を実装する。ここで、第１回路基板１１は、ガラス布基材エポキシ樹脂銅張積層板(ＦＲ‐４)等の多層銅張積層基板を加工して、予め所定の配線パターンやランド等を形成して用いられる。尚、配線パターンやランドの形成は、例えば次のようにして行われる。すなわち、多層銅張積層基板の片面毎にレジスト材料を塗布し、その後に配線パターンやランド等の形状のレチクル(例えばネガフィルムや乾板)を用いてレジスト材料を露光し、得られたレジスト膜をマスクにして銅箔をエッチングすることによって配線パターンやランド等が形成される。   In addition, as shown in FIG. 2, a first bare chip semiconductor is provided on one surface of a first circuit board 11 (hereinafter, described by using the first circuit board 11 as a representative but the same applies to the second circuit board 12). The element 13 is mounted. Here, the first circuit board 11 is formed by processing a multilayer copper-clad laminate such as a glass cloth base epoxy resin copper-clad laminate (FR-4) to form a predetermined wiring pattern, land, or the like in advance. It is done. The wiring pattern and land are formed as follows, for example. That is, a resist material is applied to each side of a multilayer copper-clad laminate substrate, and then the resist material is exposed using a reticle (for example, a negative film or a dry plate) having a shape such as a wiring pattern or land, and the resulting resist film is formed. Wiring patterns, lands, and the like are formed by etching the copper foil using a mask.

また、上記多層銅張積層基板として、耐熱性や寸法度安定性に優れているポリイミド系樹脂銅張積層基板や、ビスマレイミド‐トリアジン(ＢＴ)レジン系樹脂銅張積層基板を用いてもよい。   In addition, as the multilayer copper-clad laminate, a polyimide resin copper-clad laminate excellent in heat resistance and dimensional stability, or a bismaleimide-triazine (BT) resin copper-clad laminate may be used.

上述のような第１回路基板１１には、上記配線パターンに接続して予め形成された複数のパッド電極等に、Ａu等のバンプ１９を介して、第１ベアチップ半導体素子１３が接合される。   On the first circuit board 11 as described above, the first bare chip semiconductor element 13 is bonded to a plurality of pad electrodes formed in advance connected to the wiring pattern via bumps 19 such as Au.

上記バンプ１９としては、Ａuバンプ以外に、ＮiコアＡu等の金属突起や、必要に応じて導体フィラーを混入したペースト等による導電突起を用いることも可能である。但し、上記導電突起は金属突起よりも電気抵抗が高い。したがって、バンプ１９としては、導電突起よりも金属突起の方が望ましい。尚、バンプ１９は、第１回路基板１１の面上に形成してもよいし、第１ベアチップ半導体素子１３の面上に形成してもよい。   In addition to the Au bump, the bump 19 may be a metal protrusion such as Ni core Au, or a conductive protrusion made of a paste mixed with a conductive filler as required. However, the conductive protrusion has a higher electrical resistance than the metal protrusion. Therefore, the bump 19 is preferably a metal protrusion rather than a conductive protrusion. The bumps 19 may be formed on the surface of the first circuit board 11 or may be formed on the surface of the first bare chip semiconductor element 13.

上記第１ベアチップ半導体素子１３を第１回路基板１１に接続する方法は、第１回路基板１１と第１ベアチップ半導体素子１３との間に封止材料(封止樹脂)を介在させ、加熱・加圧によって接続部であるバンプ１９を圧接する方法や超音波を印加して接続する方法によって行う。尚、第１回路基板１１の場合には、同様にして、他方の面上にバンプ１９を介して第３ベアチップ半導体素子２０が実装される。   The method for connecting the first bare chip semiconductor element 13 to the first circuit board 11 includes heating and applying a sealing material (sealing resin) between the first circuit board 11 and the first bare chip semiconductor element 13. This is performed by a method of pressing the bumps 19 that are connection portions by pressure or a method of connecting by applying ultrasonic waves. In the case of the first circuit board 11, the third bare chip semiconductor element 20 is similarly mounted on the other surface via the bumps 19.

また、上記第１回路基板１１における第１ベアチップ半導体素子１３の実装面上に動作検査用電極２２が形成される。この動作検査用電極２２は、試験電圧の印加やテストデータの供給を行った後の出力データを引き出す際に使用される。この動作検査用電極２２として動作検査専用の電極を設けてもよい。しかしながら、本実施の形態においては、電極数を極力少なくする観点から、例えば、接合部材１６と電気的に接続されるランド電極２３等の信号入力線や信号出力線に接続された本来の電極を兼用するのである。   Further, an operation inspection electrode 22 is formed on the mounting surface of the first bare chip semiconductor element 13 in the first circuit board 11. The operation inspection electrode 22 is used when extracting output data after applying a test voltage or supplying test data. An electrode dedicated for operation inspection may be provided as the operation inspection electrode 22. However, in the present embodiment, from the viewpoint of reducing the number of electrodes as much as possible, for example, an original electrode connected to a signal input line or a signal output line such as a land electrode 23 electrically connected to the bonding member 16 is not used. They are also used.

尚、上述したように、上記第１回路基板１１は両面銅箔基板を積層してなる多層銅張積層基板であり、図２にその断面を示すように、複数の接地用ランド電極２４同士が、コンタクト孔に埋め込まれた導電部材２６と１枚の銅箔２５とを介して電気的に接続されている。また、この接地用の銅箔２５には、上記第１ベアチップ半導体素子１３の接地用の電極(図示せず)も、バンプ１９,接地用ランド電極(図示せず)およびコンタクト孔に埋め込まれた導電部材(図示せず)を介して、電気的に接続されている。   As described above, the first circuit board 11 is a multilayer copper-clad laminate formed by laminating double-sided copper foil substrates. As shown in the cross section of FIG. The conductive member 26 embedded in the contact hole and one copper foil 25 are electrically connected to each other. Further, in the grounding copper foil 25, the grounding electrode (not shown) of the first bare chip semiconductor element 13 is also embedded in the bump 19, the grounding land electrode (not shown) and the contact hole. It is electrically connected via a conductive member (not shown).

次に、両面に上記シールドパターン１７a,１７bを有する中間部材１５を形成する。図３は、中間部材１５の平面図である。尚、本実施の形態においては、第１,第２回路基板１１,１２を形成した後に中間部材１５を形成するようにしているが、第１,第２回路基板１１,１２と中間部材１５との形成順序は本実施の形態の順序に限定されることはなく、中間部材１５を形成した後に第１,第２回路基板１１,１２を形成しても一向に差し支えない。ここで、中間部材１５は絶縁フィルムで構成され、望ましくは耐熱性に優れるポリイミドより構成されることが望ましい。   Next, the intermediate member 15 having the shield patterns 17a and 17b on both sides is formed. FIG. 3 is a plan view of the intermediate member 15. In the present embodiment, the intermediate member 15 is formed after the first and second circuit boards 11 and 12 are formed. However, the first and second circuit boards 11 and 12 and the intermediate member 15 The order in which the first and second circuit boards 11 and 12 are formed after the intermediate member 15 is formed is not limited to the order in the present embodiment. Here, the intermediate member 15 is made of an insulating film, and preferably made of polyimide having excellent heat resistance.

上記シールドパターン１７a,１７bは、両面銅箔基板で成る中間部材１５の両面に形成された銅箔に、予めエッチング加工を施して所定の大きさに形成する。例えば、中間部材１５の片面毎にレジスト材を塗布し、その後に、スルーホール用のランド電極２７,２８や配線パターンやシールドパターン１７a,１７bなどの形を有するレチクルを用いて上記レジスト材を露光して、上記エッチング用のマスクを形成する。その際におけるシールドパターン１７a,１７bの形状は、接地線用のスルーホール(図示せず)に接続される２つのランド電極(接地用ランド電極)２８に至るようにパターニングされている。その後、上記マスクを用いて上記銅箔をエッチングする。こうして、スルーホール用のランド電極２７や接地用ランド電極２８や配線パターンと、シールドパターン１７a,１７bとが、同時に形成されるのである。   The shield patterns 17a and 17b are formed in a predetermined size by previously etching the copper foil formed on both surfaces of the intermediate member 15 made of a double-sided copper foil substrate. For example, a resist material is applied to each side of the intermediate member 15, and then the resist material is exposed using a reticle having shapes such as land electrodes 27, 28 for through holes, wiring patterns, shield patterns 17a, 17b, and the like. Then, the etching mask is formed. The shapes of the shield patterns 17a and 17b at that time are patterned so as to reach two land electrodes (grounding land electrodes) 28 connected to through holes (not shown) for grounding wires. Thereafter, the copper foil is etched using the mask. Thus, the through-hole land electrode 27, the ground land electrode 28, the wiring pattern, and the shield patterns 17a and 17b are formed simultaneously.

尚、本実施の形態においては、図３に示すように、中間部材１５の両面に形成されたシールドパターン１７a,１７bによって導電層１７を構成している。しかしながら、本実施の形態はこれに限定されるものではない。図４に示すように、導電層１７を中間部材１５の内層に形成すると共に、表層にスルーホール用のランド電極２９を形成し、ランド電極２９を介して接地するようにしても差し支えない。   In the present embodiment, as shown in FIG. 3, the conductive layer 17 is composed of shield patterns 17 a and 17 b formed on both surfaces of the intermediate member 15. However, the present embodiment is not limited to this. As shown in FIG. 4, the conductive layer 17 may be formed on the inner layer of the intermediate member 15, and a land electrode 29 for through holes may be formed on the surface layer and grounded via the land electrode 29.

次に、上記接合部材１６を形成する。この接合部材１６は、第１回路基板１１用の接合部材１６aと第２回路基板１２用の接合部材１６bとで構成される。そして、各接合部材１６a,１６bは、その主要部が金属のコアボールで構成されている。例えば、ＣuまたはＮi等から成る略球状の金属塊の表面を半田や錫等のメッキで被覆して形成される。上記金属のコアボールは、第１,第２回路基板１１,１２への信号出力線や第１,第２回路基板１１,１２からの信号入力線や電源線や接地線等に対応して配置される。   Next, the joining member 16 is formed. The bonding member 16 includes a bonding member 16 a for the first circuit board 11 and a bonding member 16 b for the second circuit board 12. And each joining member 16a, 16b is comprised by the core ball | bowl with the main part. For example, the surface of a substantially spherical metal lump made of Cu or Ni or the like is coated with a plating such as solder or tin. The metal core balls are arranged corresponding to signal output lines to the first and second circuit boards 11 and 12, signal input lines from the first and second circuit boards 11 and 12, power supply lines, ground lines, and the like. Is done.

その後、図５に示すように、上記中間部材１５上における周縁部に形成されたランド電極２７,２８上に接合部材１６a,１６a'を配置し、加熱処理を行って中間部材１５の一面上に接合部材１６a,１６a'を搭載する。次に、第２回路基板１２上における周縁部に形成されたランド電極２３,２４上に接合部材１６b,１６b'を配置し、同様に加熱処理を行って第２回路基板１２の一面上に接合部材１６b,１６b'を搭載する。   After that, as shown in FIG. 5, the joining members 16 a and 16 a ′ are arranged on the land electrodes 27 and 28 formed on the peripheral portion on the intermediate member 15, and heat treatment is performed on one surface of the intermediate member 15. The joining members 16a and 16a ′ are mounted. Next, the joining members 16b and 16b ′ are arranged on the land electrodes 23 and 24 formed on the peripheral edge on the second circuit board 12, and similarly heat-treated to join on one surface of the second circuit board 12. The members 16b and 16b ′ are mounted.

そうした後に、上記第２回路基板１２における接合部材１６b,１６b'の搭載面上に上記中間部材１５を、中間部材１５における接合部材１６a,１６a'の搭載面上に第１回路基板１１を、互いの接合部材１６とランド電極２３,２４,２７,２８との位置を合わせて積層する。こうすることによって、第１ベアチップ半導体素子１３がシールドパターン１７aの面に対向し、第２ベアチップ半導体素子１４がシールドパターン１７bの面に対向するように、第１回路基板１１と中間部材１５と第２回路基板１２との位置が合わせられる。   After that, the intermediate member 15 is placed on the mounting surface of the joining members 16b and 16b 'in the second circuit board 12, and the first circuit board 11 is placed on the mounting surface of the joining members 16a and 16a' in the intermediate member 15. The bonding member 16 and the land electrodes 23, 24, 27, and 28 are aligned and laminated. By doing so, the first circuit board 11, the intermediate member 15, and the first member are arranged so that the first bare chip semiconductor element 13 faces the surface of the shield pattern 17 a and the second bare chip semiconductor element 14 faces the surface of the shield pattern 17 b. The position with the two-circuit board 12 is adjusted.

その結果、上記第１回路基板１１と中間部材１５との間には接合部材１６a,１６a'が挟み込まれ、さらに中間部材１５と第２回路基板１２との間には接合部材１６b,１６b'が挟み込まれて、第１回路基板１１と中間部材１５とを接合部材１６a,１６a'によって電気的に且つ構造的に接続し、中間部材１５と第２回路基板１２とを接合部材１６b,１６b'によって電気的且つ構造的に接続した構造が得られるのである。尚、その際における上記接続は、リフロー炉等を用いた加熱工程によって行われる。   As a result, the joining members 16a and 16a ′ are sandwiched between the first circuit board 11 and the intermediate member 15, and the joining members 16b and 16b ′ are further interposed between the intermediate member 15 and the second circuit board 12. The first circuit board 11 and the intermediate member 15 are electrically and structurally connected by the joining members 16a and 16a ', and the intermediate member 15 and the second circuit board 12 are joined by the joining members 16b and 16b'. An electrically and structurally connected structure is obtained. In addition, the said connection in that case is performed by the heating process using a reflow furnace etc.

ここで、上記中間部材１５におけるランド電極２７,２８は、図３に示すように、シールドパターン１７a,１７bの周囲に２列に配列されており、そのうち接地用ランド電極２８は図中斜線で示すように内側に配置されている。また、第１,第２回路基板１１,１２におけるランド電極２３,２４は、図２に示すように、第１,第２ベアチップ半導体素子１３,１４の周囲に２列に配列されており、接地用ランド電極２４は総て内側に配置されて内層された銅箔２５に接続されている。そして、外部端子１８が設けられる側の第２回路基板１２の銅箔２５は、何れかの外部端子１８によって接地される。   Here, as shown in FIG. 3, the land electrodes 27 and 28 in the intermediate member 15 are arranged in two rows around the shield patterns 17a and 17b, of which the grounding land electrodes 28 are indicated by diagonal lines in the figure. Is arranged on the inside. The land electrodes 23 and 24 on the first and second circuit boards 11 and 12 are arranged in two rows around the first and second bare chip semiconductor elements 13 and 14 as shown in FIG. All the land electrodes 24 are connected to a copper foil 25 which is disposed on the inner side and is an inner layer. The copper foil 25 of the second circuit board 12 on the side where the external terminals 18 are provided is grounded by any of the external terminals 18.

その結果、上記第１,第２ベアチップ半導体素子１３,１４の周辺に並べて配置された接合部材１６a',１６b'が、中間部材１５におけるシールドパターン１７a,１７bの周囲内側に配置された接地用ランド電極２８および接地用スルーホールと、第２回路基板１２における第２ベアチップ半導体素子１４の周囲内側に配置された接地用ランド電極２４,導電部材２６および銅箔２５とを、介して接地される。こうして、第１,第２ベアチップ半導体素子１３,１４に近い側の接合部材１６a',１６b'と中間部材１５上のシールドパターン１７a,１７bとが接地されて、電磁シールドが得られるのである。また、その際に、第１回路基板１１と第２回路基板１２との間を封止樹脂によって封止する必要がない。したがって、回路基板を任意の数だけ積層することができることになり、実装面積が増え、多機能な電子機器の小型化を実現することができるのである。   As a result, the bonding members 16a 'and 16b' arranged side by side around the first and second bare chip semiconductor elements 13 and 14 are connected to the grounding land arranged inside the shield pattern 17a and 17b in the intermediate member 15. The electrode 28 and the grounding through hole are grounded via the grounding land electrode 24, the conductive member 26, and the copper foil 25 disposed on the inner periphery of the second bare chip semiconductor element 14 in the second circuit board 12. In this way, the joining members 16a ′ and 16b ′ near the first and second bare chip semiconductor elements 13 and 14 and the shield patterns 17a and 17b on the intermediate member 15 are grounded to obtain an electromagnetic shield. At this time, it is not necessary to seal between the first circuit board 11 and the second circuit board 12 with a sealing resin. Therefore, an arbitrary number of circuit boards can be stacked, the mounting area is increased, and downsizing of a multifunctional electronic device can be realized.

・第２実施の形態
図６は、本実施の形態における積層型半導体装置を示す断面図である。また、図７は、図６における中間基板３５の平面図である。本実装の形態における積層型半導体装置４３は、上記第１実施の形態の積層型半導体装置２１における中間部材１５と接合部材１６とを一体化したものである。すなわち、本実施の形態の積層型半導体装置４３における第１回路基板３１,第２回路基板３２,第１ベアチップ半導体素子３３,第２ベアチップ半導体素子３４,導電層３７,外部端子３８およびバンプ３９は、上記第１実施の形態の積層型半導体装置における上記第１回路基板１１,第２回路基板１２,第１ベアチップ半導体素子１３,第２ベアチップ半導体素子１４,導電層１７,外部端子１８およびバンプ１９と同じである。 Second Embodiment FIG. 6 is a cross-sectional view showing a stacked semiconductor device according to the present embodiment. FIG. 7 is a plan view of the intermediate substrate 35 in FIG. The stacked semiconductor device 43 in the present embodiment is obtained by integrating the intermediate member 15 and the bonding member 16 in the stacked semiconductor device 21 in the first embodiment. That is, the first circuit board 31, the second circuit board 32, the first bare chip semiconductor element 33, the second bare chip semiconductor element 34, the conductive layer 37, the external terminal 38, and the bump 39 in the stacked semiconductor device 43 of the present embodiment are The first circuit board 11, the second circuit board 12, the first bare chip semiconductor element 13, the second bare chip semiconductor element 14, the conductive layer 17, the external terminal 18, and the bump 19 in the stacked semiconductor device of the first embodiment. Is the same.

本実施の形態の積層型半導体装置４３における中間部材３５は、次のようにして形成される。すなわち、両面に銅箔が形成された絶縁基板である銅張基板３６上の上記銅箔に対して、上記第１実施の形態の場合と同様にしてシールドパターン３７a,３７bが形成されて、中間部材３５の本体が形成される。   The intermediate member 35 in the stacked semiconductor device 43 of the present embodiment is formed as follows. That is, shield patterns 37a and 37b are formed on the copper foil on the copper-clad substrate 36, which is an insulating substrate having copper foil formed on both sides, in the same manner as in the first embodiment, and the intermediate The main body of the member 35 is formed.

次に、上記中間部材３５の本体に用いられた上記銅張基板３６よりも厚さが厚い直線状の銅張基板４０を８枚用意し、夫々の銅張基板４０にレーザによって穴が空けられる。さらに、図７に示すように、シールドパターン３７a,３７bが形成された上記本体を成す銅張基板３６の表裏４辺に、穴空けされた８枚の銅張基板４０がそのランド(図示せず)同士の位置が合わられて貼り付けられる。こうして、中間部材３５が形成される。最後に、印刷または鍍金によって、銅張基板４０の穴が導電部材４１によって埋められる。その結果、シールドパターン３７a,３７bと銅張基板４０とが、接続端子４２を介して電気的に接続される。   Next, eight linear copper-clad boards 40 having a thickness greater than that of the copper-clad board 36 used in the body of the intermediate member 35 are prepared, and each copper-clad board 40 is drilled with a laser. . Further, as shown in FIG. 7, eight copper-clad boards 40 perforated on the front and back sides of the copper-clad board 36 forming the main body on which the shield patterns 37a and 37b are formed are lands (not shown). ) The positions of each other are aligned and pasted. Thus, the intermediate member 35 is formed. Finally, the hole of the copper-clad substrate 40 is filled with the conductive member 41 by printing or plating. As a result, the shield patterns 37 a and 37 b and the copper-clad substrate 40 are electrically connected via the connection terminal 42.

上述のように形成された中間部材３５と第１,第２回路基板３１,３２とは、異方性導電樹脂を各々の接続部に塗布した後に、第１回路基板３１と中間部材３５と第２回路基板３２とを積層し、得られた積層構造物を１７０℃程度で加圧・加熱することによって、第１回路基板３１と第２回路基板３２との間には中間部材３５が挟み込まれ、第１回路基板３１と第２回路基板３２とを中間部材３５によって電気的に且つ構造的に接続した積層型半導体装置４３が得られるのである。尚、本積層型半導体装置４３の構造によっても、上記第１実施の形態における積層型半導体装置２１と同様に、互いに対向する第１,第２ベアチップ半導体素子３３,３４の電磁シールド効果を得ることができる。   The intermediate member 35 and the first and second circuit boards 31 and 32 formed as described above are formed by applying the anisotropic conductive resin to the respective connection portions, and then the first circuit board 31, the intermediate member 35, and the first circuit board 31 and 32. The intermediate member 35 is sandwiched between the first circuit board 31 and the second circuit board 32 by laminating the two circuit boards 32 and pressurizing and heating the obtained laminated structure at about 170 ° C. Thus, the stacked semiconductor device 43 in which the first circuit board 31 and the second circuit board 32 are electrically and structurally connected by the intermediate member 35 is obtained. Note that, also by the structure of the stacked semiconductor device 43, the electromagnetic shielding effect of the first and second bare chip semiconductor elements 33 and 34 facing each other can be obtained in the same manner as the stacked semiconductor device 21 in the first embodiment. Can do.

また、本実施の形態の場合にも、上記第１回路基板３１と第２回路基板３２との間を封止樹脂によって封止する必要がない。したがって、回路基板を任意の数だけ積層することができることになり、実装面積が増え、多機能な電子機器の小型化を実現することができるのである。   Also in the case of the present embodiment, it is not necessary to seal between the first circuit board 31 and the second circuit board 32 with a sealing resin. Therefore, an arbitrary number of circuit boards can be stacked, the mounting area is increased, and downsizing of a multifunctional electronic device can be realized.

尚、本実施の形態においては、上記中間部材３５として銅張基板３６を用いる場合について説明したが、中央部がポリイミド基板であり且つ周辺部がリジット基板であるリジットフレキ基板を用いても構わない。   In this embodiment, the case where the copper-clad substrate 36 is used as the intermediate member 35 has been described. However, a rigid-flexible substrate in which the central portion is a polyimide substrate and the peripheral portion is a rigid substrate may be used. .

また、上記各実施の形態においては、２枚の回路基板１１,１２：３１,３２を積層する場合を例に説明しているが、回路基板の積層数は２枚に限定されるものではなく、３枚以上の回路基板を積層する場合にも適用できる。そして、そのような場合であって同様な効果を得ることができるのである。   In each of the above embodiments, the case where two circuit boards 11, 12, 31 and 32 are stacked is described as an example. However, the number of circuit boards stacked is not limited to two. The present invention can also be applied when three or more circuit boards are stacked. In such a case, the same effect can be obtained.

本発明の積層型半導体装置およびその製造方法は、半導体集積回路や受動素子等の電子部品を高密度に実装するのに有用であり、小型化,薄型化が要求される電子機器等に利用することができる。   INDUSTRIAL APPLICABILITY The stacked semiconductor device and the manufacturing method thereof according to the present invention are useful for mounting electronic components such as semiconductor integrated circuits and passive elements at high density, and are used for electronic devices that are required to be downsized and thinned. be able to.

この発明の積層型半導体装置における断面図である。It is sectional drawing in the laminated semiconductor device of this invention. 第１ベアチップ半導体素子が実装された第１回路基板の斜視図である。It is a perspective view of the 1st circuit board with which the 1st bare chip semiconductor element was mounted. 図１における中間部材の平面図である。It is a top view of the intermediate member in FIG. 図１および図３とは異なる中間部材の断面図である。It is sectional drawing of the intermediate member different from FIG. 1 and FIG. 図１における第１回路基板,中間部材および第２回路基板の積層手順を示す図である。It is a figure which shows the lamination | stacking procedure of the 1st circuit board in FIG. 1, an intermediate member, and a 2nd circuit board. 図１とは異なる積層型半導体装置における断面図である。FIG. 2 is a cross-sectional view of a stacked semiconductor device different from FIG. 1. 図６における中間基板の平面図である。FIG. 7 is a plan view of the intermediate substrate in FIG. 6. 電磁シールドを図る従来の半導体素子の実装構造における断面図である。It is sectional drawing in the mounting structure of the conventional semiconductor element which aims at electromagnetic shielding.

符号の説明Explanation of symbols

１１,３１…第１回路基板、
１２,３２…第２回路基板、
１３,３３…第１ベアチップ半導体素子、
１４,３４…第２ベアチップ半導体素子、
１５,３５…中間部材、
１６,１６a,１６b…接合部材、
１７,３７…導電層、
１７a,１７b,３７a,３７b…シールドパターン、
１８,３８…外部端子、
１９,３９…バンプ、
２０…第３ベアチップ半導体素子、
２１,４３…積層型半導体装置、
２２…動作検査用電極、
２３,２７…スルーホール用のランド電極、
２４,２８…接地用ランド電極、
３６,４０…銅張基板、
４１…導電部材。
11, 31 ... 1st circuit board,
12, 32 ... second circuit board,
13, 33 ... first bare chip semiconductor element,
14, 34 ... second bare chip semiconductor element,
15, 35 ... intermediate member,
16, 16a, 16b ... joining members,
17, 37 ... conductive layer,
17a, 17b, 37a, 37b ... shield pattern,
18, 38 ... external terminals,
19,39 ... Bump,
20 ... Third bare chip semiconductor element,
21, 43 ... Stacked semiconductor device,
22 ... Electrode for operation inspection,
23, 27 ... land electrodes for through holes,
24, 28 ... Land electrode for grounding,
36, 40 ... Copper-clad substrate,
41: Conductive member.

Claims (5)

電子部品が搭載された複数の回路基板を順次積層してなる積層型半導体装置において、
上記積層された複数の回路基板のうち互いに隣接している回路基板であって、搭載されている電子部品が互いに対向している２つの回路基板の間に、導電層を有する中間部材を挟設し、
上記中間部材を介して、上記互いに隣接している２つの回路基板間を、電気的に且つ機械的に接続したことを特徴とする積層型半導体装置。 In a stacked semiconductor device formed by sequentially stacking a plurality of circuit boards on which electronic components are mounted,
An intermediate member having a conductive layer is sandwiched between two circuit boards that are adjacent to each other among the plurality of circuit boards stacked above and on which the mounted electronic components face each other. And
2. A stacked semiconductor device characterized in that the two circuit boards adjacent to each other are electrically and mechanically connected via the intermediate member. 請求項１に記載の積層型半導体装置において、
上記中間部材の導電層は、対峙している上記電子部品の面積よりも広い面積を有すると共に、当該中間部材の表面または内部に上記電子部品と積層方向に重なり合うように形成されていることを特徴とする積層型半導体装置。 The stacked semiconductor device according to claim 1,
The conductive layer of the intermediate member has an area larger than that of the facing electronic component, and is formed on the surface or inside of the intermediate member so as to overlap the electronic component in the stacking direction. A stacked semiconductor device. 請求項１に記載の積層型半導体装置において、
上記中間部材の導電層は、上記互いに隣接している２つの回路基板のグランド端子と上記互いに対向している電子部品のグランド端子とに、接続されていることを特徴とする積層型半導体装置。 The stacked semiconductor device according to claim 1,
The conductive layer of the intermediate member is connected to the ground terminals of the two circuit boards adjacent to each other and the ground terminals of the electronic components facing each other. 請求項１に記載の積層型半導体装置において、
上記電子部品は、上記回路基板にフリップチップ実装されることによって搭載されていることを特徴とする積層型半導体装置。 The stacked semiconductor device according to claim 1,
2. The stacked semiconductor device according to claim 1, wherein the electronic component is mounted on the circuit board by flip chip mounting. 電子部品が搭載された複数の回路基板を順次積層してなる積層型半導体装置の製造方法において、
上記電子部品を上記回路基板上に実装し、
絶縁体で成る中間部材に導電層を形成し、
少なくとも、２つの上記回路基板と１つの上記中間部材とを用いて、
上記２つの上記回路基板のうちの一方である第１回路基板を、この第１回路基板上の電子部品を当該中間部材の導電層に対向させて、当該中間部材の一面に接合部材を介して積層すると共に接合し、
上記２つの上記回路基板のうちの他方である第２回路基板を、この第２回路基板上の電子部品を当該中間部材の導電層に対向させて、当該中間部材の他面に接合部材を介して積層すると共に接合する
ことを特徴とする積層型半導体装置の製造方法。
In a manufacturing method of a stacked semiconductor device in which a plurality of circuit boards on which electronic components are mounted are sequentially stacked,
Mounting the electronic component on the circuit board;
Forming a conductive layer on an intermediate member made of an insulator;
Using at least two circuit boards and one intermediate member,
The first circuit board, which is one of the two circuit boards, is arranged with the electronic component on the first circuit board opposed to the conductive layer of the intermediate member, and a bonding member is provided on one surface of the intermediate member. Laminate and join,
The second circuit board, which is the other of the two circuit boards, is placed with the electronic component on the second circuit board facing the conductive layer of the intermediate member, and a bonding member is interposed on the other surface of the intermediate member. A method of manufacturing a stacked semiconductor device, wherein the stacked semiconductor devices are stacked and bonded together.
JP2003386563A 2003-11-17 2003-11-17 Laminated semiconductor device and its manufacturing method Pending JP2005150443A (en)

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