JP2001053447A - Multilayer wiring board with built-in part and manufacturing method thereof - Google Patents

Multilayer wiring board with built-in part and manufacturing method thereof

Info

Publication number
JP2001053447A
JP2001053447A JP11221976A JP22197699A JP2001053447A JP 2001053447 A JP2001053447 A JP 2001053447A JP 11221976 A JP11221976 A JP 11221976A JP 22197699 A JP22197699 A JP 22197699A JP 2001053447 A JP2001053447 A JP 2001053447A
Authority
JP
Japan
Prior art keywords
wiring board
built
component
multilayer wiring
inner layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11221976A
Other languages
Japanese (ja)
Inventor
Hiroyasu Yamamoto
博康 山本
Naoshige Ejiri
直繁 江尻
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Iwaki Electronics Co Ltd
Original Assignee
Iwaki Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Iwaki Electronics Co Ltd filed Critical Iwaki Electronics Co Ltd
Priority to JP11221976A priority Critical patent/JP2001053447A/en
Publication of JP2001053447A publication Critical patent/JP2001053447A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24153—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
    • H01L2224/24195—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being a discrete passive component
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/15165—Monolayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor

Abstract

PROBLEM TO BE SOLVED: To realize a multilayer with built-in parts which does not depend on soldering. SOLUTION: Circuit parts 22 and 23 are embedded in an inner layer 20, and an insulating layer 26 is formed on terminal faces 22a and 23a of the circuit parts 22 and 23. A connecting hole 27 is perforated in the insulating layer 26 so that the terminal faces 22a and 23a of the circuit parts 22 and 23 can be exposed, and the connection with the circuit parts can be operated in a batch by the through-hole formation with the connecting hole 27 and etching processing. This system is made executable as a series of works in the conventional manufacturing process of a multilayer wiring board so that the process can be simplified, and it is not necessary to use solder being an environmental load substance for inter-part or interlayer connection so that this multilayer wiring board can be made suitable even for an environment.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、内層に小型回路部
品を埋め込んで成る部品内蔵型多層配線基板およびその
製造方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a component built-in type multilayer wiring board having a small circuit component embedded in an inner layer, and a method of manufacturing the same.

【０００２】[0002]

【従来の技術】近年、電子機器の小型・軽量化と共に高
速化、高多機能化傾向が一段と高まってきており、プリ
ント配線基板においては信頼性の高い高密度実装技術の
追求が進められている。このような傾向の中で、単層基
板や多層基板を使用し、その表裏面にディスクリート部
品やチップ部品等を実装していた従来の表面実装技術に
代って３層以上の多層配線基板を使用し、内層にチップ
型のコンデンサ、抵抗、ＩＣ等のベアーチップを埋め込
むようにした三次元実装・配線技術が注目されるように
なってきた。係る多層配線基板の製造技術により部品実
装密度は飛躍的に向上し、これによる配線距離の短縮化
も手伝って高密度実装化と共に高速化、高信頼性化が実
現されるようになった。2. Description of the Related Art In recent years, the trend toward higher speeds and higher functions has been further increased along with the reduction in size and weight of electronic devices, and the pursuit of highly reliable high-density packaging technology for printed wiring boards has been pursued. . In such a tendency, a multilayer wiring board of three or more layers is used instead of the conventional surface mounting technology in which a single-layer board or a multilayer board is used, and discrete components or chip components are mounted on the front and back surfaces. Attention has been paid to three-dimensional mounting / wiring technology in which a bare chip such as a chip-type capacitor, resistor, or IC is embedded in an inner layer. With such a multilayer wiring board manufacturing technology, the component mounting density has been dramatically improved, and this has helped to shorten the wiring distance, thereby realizing high-density mounting, as well as high speed and high reliability.

【０００３】係る部品内蔵型の多層配線基板技術とし
て、例えば、特開平６−１２０６７１号公報が開示され
ている。この技術は内層にチップ部品を埋め込み、層間
導通および内蔵部品間の接続をそれぞれ融点の異なる半
田材を使用して数工程に分けて行うものである。[0003] As such a multi-layer wiring board technology with a built-in component, for example, Japanese Patent Application Laid-Open No. H6-120671 is disclosed. In this technique, chip components are embedded in an inner layer, and interlayer conduction and connection between built-in components are performed in several steps by using solder materials having different melting points.

【０００４】[0004]

【発明が解決しようとする課題】しかしながら、上記開
示技術は、半田接続箇所に応じて数回の半田付け工程を
要すること、溶融温度を安定に維持するための半田素材
の品質管理が必要なこと等の理由から配線基板の製造工
程が複雑化するといった欠点を有していた。また、近
年、半田材料は環境負荷物質として基板製造工程におけ
る環境汚染や作業者への有害性が指摘されるようになっ
てきている。However, the disclosed technique requires several soldering steps depending on the solder connection location, and requires quality control of the solder material to stably maintain the melting temperature. For this reason, there is a disadvantage that the manufacturing process of the wiring board is complicated. In recent years, solder materials have been pointed out as environmentally harmful substances, for example, environmental pollution and harmfulness to workers in a substrate manufacturing process.

【０００５】本発明は、上記従来の問題点に鑑みて成さ
れたもので、内蔵部品への接続をスルホール形成とエッ
チング処理により行うようにして、配線基板の製造工程
を簡略化すると共に、半田の使用を極力無くすようにし
た部品内蔵型多層配線基板およびその製造方法を提供す
ることを目的としている。SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned conventional problems, and the connection to a built-in component is performed by forming a through hole and an etching process, thereby simplifying a manufacturing process of a wiring board and improving soldering. It is an object of the present invention to provide a multi-layer wiring board with a built-in component and a method of manufacturing the same, which minimizes the use of a component.

【０００６】[0006]

【課題を解決するための手段】すなわち、請求項１に記
載の部品内蔵型多層配線基板では、内層に複数の回路部
品を埋め込んで成る多層配線基板において、前記回路部
品への接続がメッキにて行われることを特徴とするもの
である。According to a first aspect of the present invention, in the multilayer wiring board with a built-in component, a plurality of circuit parts are embedded in an inner layer, and the connection to the circuit parts is made by plating. It is characterized by being performed.

【０００７】これにより、部品の高密度実装化が可能と
なると共に、層間或いは内蔵部品の接続手段に環境負荷
物質である半田を使用しなくて済むことから、製造工程
における環境汚染等の問題に対して極めて好適である。As a result, high-density mounting of components becomes possible, and since there is no need to use solder, which is an environmentally harmful substance, between layers or means for connecting built-in components, problems such as environmental pollution in the manufacturing process can be solved. Very suitable for this.

【０００８】また、請求項２に記載の部品内蔵型多層配
線基板の製造方法では、内層に複数の回路部品を埋め込
み、当該回路部品の端子面上に絶縁層を形成し、当該絶
縁層に接続孔を穿設して前記回路部品の端子面を露出さ
せ、前記接続孔によるスルーホール形成とエッチング処
理により前記回路部品への接続を一括して行うことを特
徴とするものである。According to a second aspect of the present invention, a plurality of circuit components are embedded in an inner layer, an insulating layer is formed on a terminal surface of the circuit component, and a connection is made to the insulating layer. A hole is formed to expose a terminal surface of the circuit component, and connection to the circuit component is collectively performed by forming a through hole using the connection hole and etching.

【０００９】本方式では、従来の多層配線基板の製造工
程の中で一連の作業として実施可能であり、よって、従
来の配線基板の製造設備、治工具、製造技術等をそのま
ま活用できるものである。The present method can be implemented as a series of operations in the conventional multi-layer wiring board manufacturing process, and therefore, the conventional wiring board manufacturing equipment, jigs and tools, manufacturing technology, etc. can be utilized as it is. .

【００１０】[0010]

【発明の実施の形態】以下、図面に基づいて本発明の第
１実施形態を説明する。図１は本発明の第１実施形態に
係る部品内蔵型多層配線基板の製造工程図、図２はその
製造工程における内層板の断面図である。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a manufacturing process diagram of a component built-in type multilayer wiring board according to a first embodiment of the present invention, and FIG. 2 is a sectional view of an inner layer plate in the manufacturing process.

【００１１】本発明の第１実施形態は、図６に示す従来
工法による多層配線基板（例えば、４層構成で、内層に
部品を内蔵しない基板）の製造工程の中で一連の作業と
して実施するものであって、図１中の太線枠で示す内層
板の形成工程が従来のビルドアップ工法による内層パタ
ーン形成工程（図６の工程ａ〜ｃに示す内層パターン形
成−エッチング−内層表面処理）と相違するところであ
って、内層板と外層板の積層接着工程や外層パターン形
成工程等それ以降の工程は全て同じである。The first embodiment of the present invention is carried out as a series of operations in a manufacturing process of a multilayer wiring board (for example, a board having a four-layer structure and having no component built in an inner layer) by a conventional method shown in FIG. The inner layer plate forming step indicated by a bold line frame in FIG. 1 includes an inner layer pattern forming step (inner layer pattern forming-etching-inner surface treatment shown in steps a to c in FIG. 6) by a conventional build-up method. The difference is that the subsequent steps such as the step of laminating and bonding the inner layer plate and the outer layer plate and the step of forming the outer layer pattern are all the same.

【００１２】以下、図１および図２に基づき前記した内
層板の形成工程を説明する。尚、本実施形態に係る多層
配線基板は外層用の片面基板（１層と４層）と内層板２
０（２層と３層）とによる４層構造とした。Hereinafter, a process of forming the above-described inner layer plate will be described with reference to FIGS. The multilayer wiring board according to the present embodiment includes a single-sided board (one and four layers) for the outer layer and an inner layer board 2.
0 (two layers and three layers).

【００１３】先ず、図１の工程ａで、内層板２０（コア
材２０）に各々チップ型の回路部品を収容するための部
品埋込用穴２１の加工を行う（図２ａ参照）。コア材２
０としては、外層用の銅張積層板や樹脂付き銅箔等によ
る配線基板材と同程度の熱膨張率を有する物を使用する
ことにより、積層工程における基板の反りが防止でき
る。First, in step a in FIG. 1, a component embedding hole 21 for accommodating a chip-type circuit component is formed in the inner layer plate 20 (core material 20) (see FIG. 2a). Core material 2
As the value of 0, the use of a copper-clad laminate for the outer layer, a copper foil with resin, or the like having a thermal expansion coefficient similar to that of a wiring board material can prevent the board from warping in the laminating step.

【００１４】次に、図１の工程ｂで、前記部品埋込用穴
２１に、例えば、ＩＣチップ２２やチップ型コンデンサ
２３等を埋め込み、隙間に樹脂を充填して接着・固定す
る（図２ｂ参照）。ここで、ＩＣチップ２２は横実装型
であるから部品埋込用穴２１は凹溝形状であり、チップ
型コンデンサ２３は縦実装型であるから部品埋込用穴２
１は貫通孔とされている。Next, in the step b of FIG. 1, for example, an IC chip 22 or a chip type capacitor 23 is buried in the component embedding hole 21, and the gap is filled with a resin and adhered and fixed (FIG. 2b). reference). Here, since the IC chip 22 is a horizontal mounting type, the component embedding hole 21 has a concave groove shape, and the chip type capacitor 23 is a vertical mounting type, so that the component embedding hole 2
1 is a through hole.

【００１５】次に、図１の工程ｃで、回路部品が埋め込
まれた内層板２０の上下両面に絶縁層（絶縁膜）を印刷
・焼き付けして絶縁層２６を形成する（図２ｃ参照）。Next, in step c of FIG. 1, an insulating layer (insulating film) is printed and baked on both upper and lower surfaces of the inner layer board 20 in which the circuit components are embedded, thereby forming an insulating layer 26 (see FIG. 2c).

【００１６】次に、図１の工程ｄで、前記ＩＣチップ２
２の端子面２２ａとチップ型コデンサチップ２３の端子
面２３ａに対応する絶縁層２６に接続孔２７（スルホー
ル用穴２７）を穿設し、その部分の絶縁層２６を除去す
ることにより各々回路部品２２、２３の端子面２２ａ、
２３ａを露出状態にする（図２ｄ参照）。Next, in step d of FIG.
A connection hole 27 (a hole 27 for a through hole) is formed in the insulating layer 26 corresponding to the terminal surface 22a of the second component 2 and the terminal surface 23a of the chip-type capacitor chip 23, and the insulating layer 26 in that portion is removed, thereby forming each of the circuit components 22. , 23 terminal surfaces 22a,
23a is exposed (see FIG. 2d).

【００１７】上記孔空け加工は、高精度が要求されるも
のにあっては、通常レーザ光を照射して行われるが、薬
品により絶縁層２６を溶解することにより行うことも可
能である。勿論、従来のようにドリルを用いた穿設も可
能である。In the case where high precision is required, the above-described drilling is usually performed by irradiating a laser beam, but it can also be performed by dissolving the insulating layer 26 with a chemical. Of course, drilling using a drill as in the related art is also possible.

【００１８】次に、図１の工程ｅで、部品端子面上の残
留物（プリプレグ残片）を除去し、従来のビルドアップ
工法により接続孔２７の内壁、露出した端子面２２ａ、
２３ａ、および上下絶縁層２６の表面等にメッキを施
す。メッキ処理後、エッチングにより所定の導体パター
ン２８（即ち、内層パターン２８）を形成する。この内
層パターン２８によって各回路部品２２、２３への導通
接続が行われるものである（図２ｅ参照）。Next, in step e of FIG. 1, the residue (prepreg residue) on the component terminal surface is removed, and the inner wall of the connection hole 27, the exposed terminal surface 22a,
23a, the surface of the upper and lower insulating layers 26 and the like are plated. After the plating process, a predetermined conductor pattern 28 (that is, the inner layer pattern 28) is formed by etching. Conductive connection to each of the circuit components 22 and 23 is performed by the inner layer pattern 28 (see FIG. 2E).

【００１９】以降、図１の工程ｆで、外層用の片面銅張
板（又は樹脂付き銅箔）と前記工程ａ〜ｅで形成された
部品内蔵の内層板２０とを、間にプリプレグを介在して
積層・接着し、従来工法により外層パターンを形成した
後、レジスト印刷、シルク印刷等の工程を経て本発明の
第１実施形態による部品内蔵型多層配線基板が完成す
る。尚、この工程の断面図は省略した。Thereafter, in step f of FIG. 1, a prepreg is interposed between the single-sided copper-clad board (or copper foil with resin) for the outer layer and the inner layer board 20 with the built-in components formed in the steps a to e. After laminating and bonding, and forming an outer layer pattern by a conventional method, a component-embedded multilayer wiring board according to the first embodiment of the present invention is completed through steps such as resist printing and silk printing. A cross-sectional view of this step is omitted.

【００２０】次に、図３および図４に基づいて本発明の
第２実施形態を説明する。Next, a second embodiment of the present invention will be described with reference to FIGS.

【００２１】図３は本発明の第２実施形態に係る部品内
蔵型多層配線基板の製造工程図、図４はその製造工程を
示す断面図である。FIG. 3 is a manufacturing process diagram of a multi-layer wiring board with a built-in component according to a second embodiment of the present invention, and FIG. 4 is a sectional view showing the manufacturing process.

【００２２】前記した第１実施形態が内層板２０に内層
パターン２８を形成して内蔵部品への接続を行う構成で
あるのに対し、第２実施形態は内蔵部品への接続を従来
工法にて外層基板上に形成した外層パターンにより行う
ものである。従って、内層板２０には回路部品２２〜２
４が埋め込まれるだけで前記第１実施形態の中で説明し
た内層パターン（２８）の形成は行われない。即ち、本
第２実施形態の場合は図３中の太線枠で示す部分が従来
工法に付加される新たな作業工程である。While the first embodiment has a configuration in which the inner layer pattern 28 is formed on the inner layer plate 20 to connect to the built-in components, the second embodiment connects to the built-in components by a conventional method. This is performed using an outer layer pattern formed on an outer layer substrate. Therefore, the circuit components 22 to 2 are provided on the inner layer plate 20.
4, the formation of the inner layer pattern (28) described in the first embodiment is not performed. That is, in the case of the second embodiment, the portion shown by the thick line frame in FIG. 3 is a new work step added to the conventional method.

【００２３】以下、図３および図４により部品内蔵型多
層配線基板の製造方法を説明する。尚、本実施形態に係
る多層配線基板は、外層用の両面基板１０（１層と２
層）と両面基板３０（３層と４層）、および、内層板２
０（コア材）とによる４層構造とした。Hereinafter, a method for manufacturing a multilayer wiring board with a built-in component will be described with reference to FIGS. It should be noted that the multilayer wiring board according to the present embodiment is a double-sided board 10 (one layer and two
Layer), the double-sided board 30 (three layers and four layers), and the inner layer board 2
0 (core material).

【００２４】先ず、図３の工程ａ、ｂでは、前記第１実
施形態と同様にして内層板２０に部品埋込用穴２１の加
工を行う。そして、この部品埋込用穴２１に、例えば、
ＩＣチップ２２、チップ型コンデンサチ２３、およびチ
ップ型抵抗２４等の小型チップ部品を埋め込み、樹脂に
て接着・固定する。（図４ａ、図４ｂ参照）First, in steps a and b of FIG. 3, a hole 21 for embedding a component is formed in the inner layer plate 20 in the same manner as in the first embodiment. Then, for example, in this component embedding hole 21,
Small chip components such as an IC chip 22, a chip-type capacitor 23 and a chip-type resistor 24 are embedded and bonded and fixed with resin. (See FIGS. 4A and 4B)

【００２５】一方、前記した外層用の両面基板１０およ
び両面基板３０（外層配線板）には、図３中、二重枠で
示す従来工法（両面板パターン形成−孔あけ−両面板エ
ッチング）により、図４ｃに示す外層パターン１１、３
１が形成される。この際、外層パターンの１１，３１に
は回路部品２２〜２４の端子面２２ａ〜２４ａに対応す
る位置にスルホール用ランド１２、３２が形成されてい
る。On the other hand, the double-sided board 10 and the double-sided board 30 (outer layer wiring board) for the outer layer are formed by the conventional method (double-sided board pattern formation-drilling-double-sided board etching) shown by a double frame in FIG. , The outer layer patterns 11, 3 shown in FIG.
1 is formed. At this time, lands 12 and 32 for through holes are formed on the outer layer patterns 11 and 31 at positions corresponding to the terminal surfaces 22a to 24a of the circuit components 22 to 24.

【００２６】次に、図３の工程ｃで、外層パターン１
１、３１が形成された外層配線板１０、３０と前記内層
板２０とを、間にプリプレグ４０（或いは、薄い樹脂フ
ィルム等を使用しても良い）を介在して積層・接着する
（図４ｃ参照）。Next, in step c of FIG.
The outer wiring boards 10 and 30 on which the first and the first wiring 31 are formed and the inner layer board 20 are laminated and bonded with a prepreg 40 (or a thin resin film or the like may be used) interposed therebetween (FIG. 4c). reference).

【００２７】次に、図３の工程ｄで、前記スルホール用
ランド１２、３２に接続用孔１３、３３（即ち、スルホ
ール孔１３、３３）を穿設してプリプレグ４０を除去
し、各回路部品２２〜２４の端子面２２ａ〜２４ａを露
出させる。この際の孔あけ加工は、第１実施形態の場合
と同様であり、レーザ光や薬品、あるいはドリルを使用
して行う。Next, in step d of FIG. 3, connection holes 13 and 33 (that is, through holes 13 and 33) are formed in the through hole lands 12 and 32, and the prepreg 40 is removed. The terminal surfaces 22a to 24a of the terminals 22 to 24 are exposed. The drilling at this time is the same as in the first embodiment, and is performed using laser light, a chemical, or a drill.

【００２８】次いで、図３の工程ｆで接続用孔１３、３
３の内壁と露出した端子面にメッキを施し、前工程で形
成された上外層パターン１１および下外層パターン３１
を介して内蔵部品２２〜２４への接続を完了する（図４
ｄ参照）。尚、図３の工程ｅに示す「孔あけ工程」は、
図４には図示していないが１〜４層間を接続するための
接続用スルホール孔である。Next, in step f of FIG.
3 is plated on the inner wall and the exposed terminal surface to form the upper and lower outer layer patterns 11 and 31 formed in the previous step.
The connection to the built-in components 22 to 24 is completed through
d). The “drilling step” shown in step e of FIG.
Although not shown in FIG. 4, it is a through hole for connection for connecting the first to fourth layers.

【００２９】以降、レジスト印刷、シルク印刷等の工程
を経て本発明の第２実施形態による部品内蔵型多層配線
基板が完成する。図５は完成した部品内蔵型多層基板１
の内部構造を示す断面図であり、図中の符号１０および
３０は外層配線板、符号２０はＩＣチップ２２、チップ
型コンデンサ２３、チップ型抵抗２４等の小型チップ部
品が内蔵された内層板である。また、外層配線板１０の
表面に複数の外付けＩＣ部品２が実装されている。Thereafter, through a process such as resist printing and silk printing, a multi-layer wiring board with a built-in component according to the second embodiment of the present invention is completed. FIG. 5 shows a completed multilayer board 1 with built-in components.
Are cross-sectional views showing the internal structure of the semiconductor device. Reference numerals 10 and 30 in the drawing denote outer layer wiring boards, and reference numeral 20 denotes an inner layer board in which small chip components such as an IC chip 22, a chip capacitor 23, and a chip resistor 24 are built. is there. A plurality of external IC components 2 are mounted on the surface of the outer wiring board 10.

【００３０】このように、本実施形態によれば、多層配
線基板の内層に複数の回路部品を埋め込み、これらの内
蔵部品を従来の多層配線板の製造工程で成されるメッキ
処理にて一括して接続することにより、近年の超高密度
実装傾向に対応可能な部品内蔵型多層配線基板を作製す
ることができる。As described above, according to the present embodiment, a plurality of circuit components are embedded in the inner layer of the multilayer wiring board, and these built-in components are collectively subjected to the plating process performed in the conventional multilayer wiring board manufacturing process. Thus, a multilayer wiring board with a built-in component capable of coping with the recent trend of ultra-high-density mounting can be manufactured.

【００３１】係る工法は、従来の多層配線基板の製造設
備や治工具、或いは製造技術等をそのまま活用すること
ができるため、従来の半田接続による部品内蔵型多層配
線板のような煩雑な製造工程を経ず単純な工程で信頼性
の高い高密度実装を実現できるものである。また、内蔵
部品の接続や層間接続に半田材を使用しないから、製造
工程における環境汚染の問題等も解消できるものであ
る。In this method, since the conventional manufacturing equipment, jigs and tools, or manufacturing technology of the multilayer wiring board can be used as it is, complicated manufacturing steps such as the conventional multi-layer wiring board with built-in parts by solder connection are used. Thus, high-density mounting with high reliability can be realized by a simple process without passing through. Further, since no solder material is used for connection of built-in components and interlayer connection, it is possible to solve the problem of environmental pollution and the like in the manufacturing process.

【００３２】また、本実施形態では４層構造による基本
的な多層配線基板について説明したがこれに限定される
ものではなく、同様な作業の繰り返しにより４層以上の
高多層板も勿論適用可能である。In the present embodiment, a basic multilayer wiring board having a four-layer structure has been described. However, the present invention is not limited to this, and a high multilayer board having four or more layers can be applied by repeating similar operations. is there.

【００３３】[0033]

【発明の効果】以上説明したように、請求項１に記載の
本発明によれば、内層に複数の回路部品が埋め込まれて
成る多層配線基板において、前記回路部品への接続をメ
ッキにて行うようにしたので、高密度実装が可能な部品
内蔵型多層配線基板の製造工程において、各層間や内蔵
部品間の接続に環境負荷物質である半田を使用しなくて
良いから、近年問題の環境汚染や作業者への有害性指摘
に対しても極めて好適である。As described above, according to the first aspect of the present invention, in a multilayer wiring board having a plurality of circuit components embedded in an inner layer, connection to the circuit components is performed by plating. In the process of manufacturing a multi-layer wiring board with built-in components that enables high-density mounting, it is not necessary to use solder, which is an environmentally hazardous substance, for connection between layers and between built-in components. It is also very suitable for indicating hazards to workers and workers.

【００３４】また、請求項２に記載の本発明によれば、
多層配線基板の内層に回路部品を埋め込み、当該回路部
品の端子面上に絶縁層を形成し、当該絶縁層に接続孔を
穿設して前記回路部品の端子面を露出させ、前記接続孔
によるスルーホール形成とエッチング処理により前記回
路部品への接続を一括して行うようにしたので、上記同
様の効果が奏せられる他、本工程は従来の多層配線基板
の製造工程の中で一連の作業として実施することができ
るため、従来技術による部品内蔵型多層配線板のような
煩雑な製造工程を経ずに単純な工程で高密度実装を実現
することができる。According to the present invention described in claim 2,
A circuit component is embedded in an inner layer of the multilayer wiring board, an insulating layer is formed on a terminal surface of the circuit component, a connection hole is formed in the insulating layer to expose a terminal surface of the circuit component, and the terminal hole of the circuit component is exposed. Since the connection to the circuit component is collectively performed by forming a through hole and etching, the same effect as described above can be obtained. In addition, this step is a series of operations in a conventional manufacturing process of a multilayer wiring board. Therefore, high-density mounting can be realized by a simple process without going through a complicated manufacturing process such as a multi-layer wiring board with a built-in component according to the prior art.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の第１実施形態に係る部品内蔵型多層配
線基板の製造工程図である。FIG. 1 is a manufacturing process diagram of a component-embedded multilayer wiring board according to a first embodiment of the present invention.

【図２】同、部品内蔵型多層配線基板の製造工程を示す
内層板の断面図である。FIG. 2 is a cross-sectional view of an inner layer plate showing a manufacturing process of the component-embedded multilayer wiring board.

【図３】本発明の第２実施形態に係る部品内蔵型多層配
線基板の製造工程図である。FIG. 3 is a manufacturing process diagram of a component-embedded multilayer wiring board according to a second embodiment of the present invention.

【図４】同、部品内蔵型多層配線基板の製造工程を示す
断面図である。FIG. 4 is a cross-sectional view showing a step of manufacturing the component-embedded multilayer wiring board.

【図５】本発明に係る部品内蔵型多層配線基板の断面図
である。FIG. 5 is a cross-sectional view of a component-embedded multilayer wiring board according to the present invention.

【図６】従来の多層配線基板の製造工程図である。FIG. 6 is a manufacturing process diagram of a conventional multilayer wiring board.

【符号の説明】[Explanation of symbols]

１ 部品内蔵型多層配線基板 １３，２７，３３ 接続孔（スルホール用孔） ２０ 内層（内層板） ２２〜２４ 回路部品 ２２ａ〜２４ａ 回路部品の端子 ２６ 絶縁層または絶縁膜 ４０ 絶縁層（プリプレグ） DESCRIPTION OF SYMBOLS 1 Component built-in multilayer wiring board 13, 27, 33 Connection hole (hole for through hole) 20 Inner layer (Inner layer board) 22-24 Circuit component 22a-24a Terminal of circuit component 26 Insulating layer or insulating film 40 Insulating layer (prepreg)

───────────────────────────────────────────────────── フロントページの続き Ｆターム(参考） 5E336 AA07 AA08 BB03 BC02 BC25 CC15 CC32 5E346 AA02 AA12 AA15 AA43 BB01 BB16 BB20 EE02 EE06 EE07 EE09 FF45 GG15 GG17 GG22 GG28 HH32 HH40  ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5E336 AA07 AA08 BB03 BC02 BC25 CC15 CC32 5E346 AA02 AA12 AA15 AA43 BB01 BB16 BB20 EE02 EE06 EE07 EE09 FF45 GG15 GG17 GG22 GG28 HH32 HH40

Claims (2)

【特許請求の範囲】[Claims] 【請求項１】 内層に複数の回路部品が埋め込まれて成
る多層配線基板において、 前記回路部品への接続がメッキにて行われて成ることを
特徴とする部品内蔵型多層配線基板。1. A multi-layer wiring board having a plurality of circuit components embedded in an inner layer, wherein the connection to the circuit components is performed by plating. 【請求項２】 内層に複数の回路部品を埋め込み、 当該回路部品の端子面上に絶縁層を形成し、 当該絶縁層に接続孔を穿設して前記回路部品の端子面を
露出させ、 前記接続孔によるスルーホール形成とエッチング処理に
より前記回路部品への接続を一括して行うことを特徴と
する部品内蔵型多層配線基板の製造方法。2. A plurality of circuit components are embedded in an inner layer, an insulating layer is formed on a terminal surface of the circuit component, and a connection hole is formed in the insulating layer to expose a terminal surface of the circuit component. A method of manufacturing a component built-in type multilayer wiring board, wherein connection to the circuit component is collectively performed by forming a through hole by a connection hole and etching.
JP11221976A 1999-08-05 1999-08-05 Multilayer wiring board with built-in part and manufacturing method thereof Pending JP2001053447A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11221976A JP2001053447A (en) 1999-08-05 1999-08-05 Multilayer wiring board with built-in part and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11221976A JP2001053447A (en) 1999-08-05 1999-08-05 Multilayer wiring board with built-in part and manufacturing method thereof

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Publication Number Publication Date
JP2001053447A true JP2001053447A (en) 2001-02-23

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ID=16775131

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Country Link
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