JP2000294518A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JP2000294518A
JP2000294518A JP11053644A JP5364499A JP2000294518A JP 2000294518 A JP2000294518 A JP 2000294518A JP 11053644 A JP11053644 A JP 11053644A JP 5364499 A JP5364499 A JP 5364499A JP 2000294518 A JP2000294518 A JP 2000294518A
Authority
JP
Japan
Prior art keywords
conductive layer
layer
insulating layer
interlayer insulating
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11053644A
Other languages
Japanese (ja)
Inventor
Kazuhiro Hoshino
和弘 星野
Hisanori Komai
尚紀 駒井
Mitsuru Taguchi
充 田口
Yuji Segawa
雄司 瀬川
Hiroshi Yubi
啓 由尾
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP11053644A priority Critical patent/JP2000294518A/en
Priority to SG1999001539A priority patent/SG70677A1/en
Priority to FR9903952A priority patent/FR2782839B1/en
Priority to KR1019990011097A priority patent/KR19990078425A/en
Publication of JP2000294518A publication Critical patent/JP2000294518A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/7681—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving one or more buried masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L21/76873—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by physical means, e.g. sputtering, evaporation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H01L21/2885—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device which can form a contact hole having high reliability and a trench wiring by surely embedding a recess, such as an opening and a trench part with conducting material by using an electrolytic plating method. SOLUTION: This manufacturing method of a semiconductor device comprises (A) a process of forming the recess 14, where a substrate 12 is exposed on the bottom part of an interlayer insulating layer 13 formed on the substrates 11, 12, (B) a process forming a first conducting layer 16 on the interlayer insulating layer 13, containing the recess 14 by using an electroless plating method, and (C) a process forming a second conducting layer 17 on the first conducting layer 16 by using an electrolytic plating method and embedding the recess 14 with the second conducting layer 17.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、半導体装置の製造
方法に関し、特に、開口部及び／又は溝部といった凹部
を導電材料で埋め込み、接続孔及び／又は溝配線を形成
する工程を含む半導体装置の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming a connection hole and / or a trench wiring by filling a recess such as an opening and / or a trench with a conductive material. It relates to a manufacturing method.

【０００２】[0002]

【従来の技術】ＵＬＳＩ（Ultra Large Scale Integrat
ed-Circuit）のような高集積化の進んだ半導体装置で
は、処理速度の高速化、消費電力の増大によって深刻化
する配線等のエレクトロマイグレーションに対する高い
耐性が要求される。2. Description of the Related Art ULSI (Ultra Large Scale Integrat)
2. Description of the Related Art Semiconductor devices with high integration such as ed-Circuit) require high resistance to electromigration of wiring and the like, which becomes more serious due to an increase in processing speed and an increase in power consumption.

【０００３】従来、半導体装置の配線用材料としてアル
ミニウム系合金（例えば、Ａｌ−０．５％Ｃｕ、Ａｌ−
１％Ｓｉ−０．５％Ｃｕ）が専ら用いられているが、半
導体装置の高速化を更に進めるためには、配線用材料と
して、より比抵抗の低い銅（（Ｃｕ）や銀（Ａｇ）等を
用いる必要がある。特に、Ｃｕは、比抵抗が１．８μΩ
・ｃｍと低く、半導体装置の高速化に有利な上に、エレ
クトロマイグレーション耐性がアルミニウム系合金に比
べて一桁程度高いため、アルミニウム系合金に替わる次
世代の配線用材料として期待されている。Conventionally, aluminum alloys (eg, Al-0.5% Cu, Al-
Although 1% Si-0.5% Cu) is mainly used, copper ((Cu) or silver (Ag) having a lower specific resistance is used as a wiring material in order to further increase the speed of a semiconductor device. In particular, Cu has a specific resistance of 1.8 μΩ.
Cm, which is advantageous for increasing the speed of semiconductor devices, and has an electromigration resistance that is about an order of magnitude higher than that of aluminum-based alloys. Therefore, it is expected to be a next-generation wiring material replacing aluminum-based alloys.

【０００４】ところで、半導体装置には、素子間や多層
配線間を電気的に接続するコンタクトホールあるいはビ
アホール（以下、これらを総称して「接続孔」と呼ぶ）
が多数形成されている。通常、接続孔は、層間絶縁層に
開口部（孔部）を形成し、かかる開口部に導電材料を埋
め込むことによって形成される。導電材料としてアルミ
ニウム系合金を用いる場合、開口部の埋め込みは容易で
ある。然るに、銅を用いる場合には、開口部を銅で完全
に埋め込むことは困難である。即ち、アルミニウム系合
金で開口部を埋め込む際に多用されている高温スパッタ
法やリフロー法においてはプロセス温度を４５０゜Ｃ程
度としているが、銅はアルミニウム系合金と異なり融点
が高いため、かかるプロセス温度で開口部を銅によって
確実に埋め込むことはできない。また、たとえ実験的に
開口部を埋め込めたとしても、ＵＬＳＩに存在する１０
０万個レベルの開口部を１００％埋め込むことは極めて
困難である。In a semiconductor device, a contact hole or a via hole for electrically connecting elements or multilayer wiring (hereinafter, these are collectively referred to as "connection holes").
Are formed in large numbers. Usually, the connection hole is formed by forming an opening (hole) in the interlayer insulating layer and embedding a conductive material in the opening. When an aluminum-based alloy is used as the conductive material, it is easy to fill the opening. However, when copper is used, it is difficult to completely fill the opening with copper. That is, the process temperature is set to about 450 ° C. in the high temperature sputtering method and the reflow method which are frequently used when filling the opening with an aluminum alloy. However, unlike the aluminum alloy, copper has a high melting point. Therefore, the opening cannot be reliably filled with copper. Even if the opening can be buried experimentally, the
It is extremely difficult to bury 100,000 level openings 100%.

【０００５】また、近年、層間絶縁層に溝部を形成し、
銅から成る配線用材料で溝部を埋め込むことで溝配線を
形成する、所謂、シングル・ダマシン（Single Damasce
ne）法、あるいは、銅から成る配線用材料で溝部及び溝
部の底部に設けられた開口部（孔部）を埋め込むことで
溝配線とビアホールを一体に形成する、所謂、デュアル
・ダマシン（Dual Damascene）法が実用化されつつあ
る。尚、開口部（孔部）と溝部とを、以下、凹部と総称
する。In recent years, trenches have been formed in interlayer insulating layers,
The so-called single damascene (Single Damasce) in which a trench is formed by filling the trench with a wiring material made of copper.
Ne) method, or a so-called Dual Damascene in which a trench wiring and a via hole are integrally formed by filling a trench and an opening (hole) provided in the bottom of the trench with a wiring material made of copper. ) Method is being put to practical use. The opening (hole) and the groove are hereinafter collectively referred to as a recess.

【０００６】凹部を銅（Ｃｕ）を用いて精度良く埋め込
む方法として、電解めっき法が近年注目されている。電
解めっき法によって形成した銅膜は、膜中の不純物濃度
が低く、抵抗も低いため、銅を導電材料あるいは配線用
材料として用いることは半導体装置の高速化に有利であ
る。しかしながら、銅の凹部への埋め込み性は、電解め
っき法によって銅層を形成する際に必要とされる下地層
（シード層）のステップカバレッジ（段差被覆性）に大
きく依存する。即ち、電解めっき法によって銅で凹部を
埋め込む際には、シード層のステップカバレッジが十分
に良好であることが要求される。[0006] As a method of accurately filling the concave portion with copper (Cu), an electrolytic plating method has recently attracted attention. Since a copper film formed by an electrolytic plating method has a low impurity concentration and a low resistance in a film, using copper as a conductive material or a wiring material is advantageous for increasing the speed of a semiconductor device. However, the embedding property of the copper in the concave portion largely depends on the step coverage (step coverage) of the base layer (seed layer) required when forming the copper layer by the electrolytic plating method. That is, when filling the concave portion with copper by the electrolytic plating method, it is required that the step coverage of the seed layer is sufficiently good.

【０００７】従来、シード層として、スパッタ法によっ
て形成された厚さ１００ｎｍ程度の銅層が用いられてい
る（例えば、月刊 Semiconductor World 1997.12, pp.1
92参照）。Conventionally, a copper layer having a thickness of about 100 nm formed by a sputtering method has been used as a seed layer (for example, Monthly Semiconductor World 1997.12, pp. 1).
92).

【０００８】[0008]

【発明が解決しようとする課題】しかしながら、スパッ
タ法によって形成されるシード層のステップカバレッジ
は余り良くなく、凹部内に均一にシード層を形成するこ
とが困難である場合が多い。その結果、シード層上に電
解めっき法によって銅層を形成する際の銅層の成長速度
が不均一となり、凹部を銅層で確実に埋め込めないとい
った問題や、凹部内で銅層にボイドが発生するといった
問題が生じ易い。However, the step coverage of the seed layer formed by the sputtering method is not very good, and it is often difficult to form the seed layer uniformly in the concave portion. As a result, the growth rate of the copper layer when the copper layer is formed on the seed layer by the electrolytic plating method becomes non-uniform, so that the concave portion cannot be reliably filled with the copper layer, and voids occur in the copper layer in the concave portion. Problems tend to occur.

【０００９】従って、本発明の目的は、開口部（孔部）
及び／又は溝部といった凹部を電解めっき法に基づき導
電材料で確実に埋め込み、高い信頼性を有する接続孔及
び／又は溝配線を形成することを可能とする半導体装置
の製造方法を提供することにある。Accordingly, an object of the present invention is to provide an opening (hole).
It is an object of the present invention to provide a method of manufacturing a semiconductor device that can reliably fill a concave portion such as a groove portion with a conductive material based on an electrolytic plating method and form a highly reliable connection hole and / or groove wiring. .

【００１０】[0010]

【課題を解決するための手段】上記の目的を達成するた
めの本発明の半導体装置の製造方法は、（Ａ）基体上に
形成された層間絶縁層に、基体の一部が底部に露出した
凹部を設ける工程と、（Ｂ）凹部内を含む層間絶縁層上
に、無電解めっき法によって第１の導電層を形成する工
程と、（Ｃ）第１の導電層上に、電解めっき法によって
第２の導電層を形成し、以て、凹部を第２の導電層で埋
め込む工程、から成ることを特徴とする。ここで、凹部
とは、開口部（孔部）、溝部、あるいは、溝部と溝部の
底面に設けられた開口部（孔部）の組合せの総称であ
る。In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention is characterized in that (A) a part of the substrate is exposed at the bottom in the interlayer insulating layer formed on the substrate. Providing a concave portion, (B) forming a first conductive layer on the interlayer insulating layer including the inside of the concave portion by electroless plating, and (C) forming a first conductive layer on the first conductive layer by electrolytic plating. Forming a second conductive layer and filling the recess with the second conductive layer. Here, the concave portion is a general term for an opening (a hole), a groove, or a combination of a groove and an opening (a hole) provided on the bottom surface of the groove.

【００１１】ここで、無電解めっき法とは、めっき液中
の金属イオンを化学薬品によって還元析出させる化学還
元めっきを意味し、化学めっき法とも呼ばれる。Here, the electroless plating means a chemical reduction plating in which metal ions in a plating solution are reduced and precipitated by a chemical, and is also called a chemical plating.

【００１２】第１の導電層は、第２の導電層を電解めっ
き法によって形成する際のシード層としての機能を有す
る。加えて、第１の導電層は、第２の導電層を電解めっ
き法によって形成する際の陰極としての機能をも有す
る。従って、第１の導電層は、少なくとも第２の導電層
を形成すべき層間絶縁層（凹部内を含む）の上に連続的
に形成されていればよい。また、第１の導電層の厚さ
は、第１の導電層を構成する原子の１原子層分の厚さ以
上であればよい。尚、第１の導電層の厚さが厚すぎる
と、第１の導電層の形成の際に凹部の上端部の近傍の部
分（コーナー部）で盛り上がりが生じ、第１の導電層上
に電解めっき法によって第２の導電層を形成したとき、
電解めっきの条件に依っては、凹部内の第２の導電層に
ボイドが発生する虞がある。従って、第１の導電層の厚
さは、１００ｎｍ以下であることが望ましく、更には、
５ｎｍ以上１００ｎｍ以下、一層好ましくは５ｎｍ以上
５０ｎｍ以下であることが望ましい。The first conductive layer has a function as a seed layer when the second conductive layer is formed by an electrolytic plating method. In addition, the first conductive layer also has a function as a cathode when the second conductive layer is formed by an electrolytic plating method. Therefore, the first conductive layer only needs to be continuously formed on at least the interlayer insulating layer (including the inside of the concave portion) where the second conductive layer is to be formed. Further, the thickness of the first conductive layer only needs to be equal to or more than the thickness of one atomic layer of the atoms constituting the first conductive layer. If the thickness of the first conductive layer is too large, a bulge occurs at a portion (corner portion) near the upper end of the concave portion when the first conductive layer is formed, and electrolytic formation occurs on the first conductive layer. When the second conductive layer is formed by plating,
Depending on the conditions of the electrolytic plating, a void may be generated in the second conductive layer in the concave portion. Therefore, it is desirable that the thickness of the first conductive layer is 100 nm or less.
It is desirable that the thickness be 5 nm or more and 100 nm or less, more preferably 5 nm or more and 50 nm or less.

【００１３】第１の導電層及び第２の導電層は、同一の
材料から構成されていてもよいし、電解めっき法によっ
て第２の導電層を支障なく形成することができる限り、
第１の導電層及び第２の導電層は、異なる材料から構成
されていてもよい。第１の導電層を構成する材料とし
て、Ｃｕ、Ｎｉ、Ｎｉ系合金（例えば、Ｎｉ−Ｃｏ、Ｎ
ｉ−Ｃｏ−Ｂ、Ｎｉ−Ｃｏ−Ｐ、Ｎｉ−Ｆｅ−Ｐ、Ｎｉ
−Ｗ−Ｐ）、Ｐｔ、Ｔｉ、Ｃｒ、Ｃｏ、Ｃｏ系合金（例
えば、Ｃｏ−Ｆｅ−Ｐ、Ｃｏ−Ｗ−Ｐ、Ｃｏ−Ｓｎ−
Ｐ、Ｃｏ−Ｚｎ−Ｐ、Ｃｏ−Ｍｎ−Ｐ）、Ｐｄ、Ａｇ、
Ａｕ、Ｚｎ、Ｓｎ、Ｒｈ、ＴｉＮ／Ｔｉ、ＴｉＮ／Ｒ
ｈ、ＴｉＮ／Ｐｔ、Ｚｒ、Ｈｆ、Ｔａ、Ｍｏ、Ｗ、Ｉ
ｎ、Ｇｅ及びＰｂから成る群から選択された材料を挙げ
ることができる。また、第２の導電層を構成する材料と
して、Ｃｕ、Ａｇ及びＰｔから成る群から選択された材
料を挙げることができる。尚、２層構成の場合、「／」
の前に記載した層が第２の導電層側に形成され、「／」
の後ろに記載した層が層間絶縁層側に形成されることを
意味する。以下においても同様である。The first conductive layer and the second conductive layer may be made of the same material, or as long as the second conductive layer can be formed by the electrolytic plating method without any trouble.
The first conductive layer and the second conductive layer may be made of different materials. Cu, Ni, Ni-based alloys (for example, Ni-Co, N
i-Co-B, Ni-Co-P, Ni-Fe-P, Ni
-WP), Pt, Ti, Cr, Co, Co-based alloys (for example, Co-Fe-P, Co-WP, Co-Sn-
P, Co-Zn-P, Co-Mn-P), Pd, Ag,
Au, Zn, Sn, Rh, TiN / Ti, TiN / R
h, TiN / Pt, Zr, Hf, Ta, Mo, W, I
Examples include materials selected from the group consisting of n, Ge, and Pb. In addition, as a material for forming the second conductive layer, a material selected from the group consisting of Cu, Ag, and Pt can be given. In the case of a two-layer structure, "/"
The layer described before is formed on the second conductive layer side, and "/"
Is formed on the side of the interlayer insulating layer. The same applies to the following.

【００１４】第１の導電層を構成する材料に依っては、
第１の導電層は、第２の導電層を構成する原子が層間絶
縁層中に拡散することを防止するための拡散防止層（バ
リア層とも呼ばれる）としての機能も併せて有する場合
もあり、この場合には、拡散防止層を形成する必要はな
い。また、本発明の半導体装置の製造方法において、第
１の導電層を構成する材料に依っては、第１の導電層を
形成する前に、第１の導電層及び／又は第２の導電層を
構成する原子が層間絶縁層中に拡散することを防止する
ための拡散防止層を凹部内を含む層間絶縁層上に形成す
る工程を更に含むことが好ましい。尚、拡散防止層を構
成する材料として、Ｔｉ、ＴｉＮ、ＴｉＷ、ＴｉＳｉ
Ｎ、Ｗ、ＷＮ、ＷＳｉＮ、Ｒｈ、Ｐｔ、Ｔａ、ＴａＮ、
ＴａＳｉＮを挙げることができ、また、拡散防止層を、
ＴｉＮ／Ｔｉ、ＴｉＮ／Ｒｈ、ＴｉＮ／Ｐｔ、ＴａＮ／
Ｔａの２層構成、あるいはＴａ／ＴａＮ／Ｔａの３層構
成とすることもできるが、中でも、ＴｉＮ、ＴｉＮ／Ｔ
ｉ、Ｔａ、ＴａＮ、ＴａＮ／Ｔａ及びＴａ／ＴａＮ／Ｔ
ａから成る群から選択された材料から構成されているこ
とが好ましい。拡散防止層は、例えばスパッタ法やＣＶ
Ｄ法にて形成することができる。尚、これらの材料から
構成された拡散防止層上に、直接、第２の導電層を形成
しようとした場合、拡散防止層上に第２の導電層を形成
できなかったり、拡散防止層と第２の導電層との間に良
好な密着性を得ることができない場合がある。Depending on the material constituting the first conductive layer,
In some cases, the first conductive layer also has a function as a diffusion prevention layer (also referred to as a barrier layer) for preventing atoms constituting the second conductive layer from diffusing into the interlayer insulating layer. In this case, it is not necessary to form a diffusion prevention layer. In the method for manufacturing a semiconductor device according to the present invention, depending on a material constituting the first conductive layer, the first conductive layer and / or the second conductive layer may be formed before the first conductive layer is formed. It is preferable that the method further includes a step of forming a diffusion prevention layer on the interlayer insulating layer including the inside of the concave portion for preventing the atoms constituting the above from diffusing into the interlayer insulating layer. In addition, Ti, TiN, TiW, TiSi
N, W, WN, WSiN, Rh, Pt, Ta, TaN,
TaSiN can be mentioned, and the diffusion preventing layer is
TiN / Ti, TiN / Rh, TiN / Pt, TaN /
A two-layer structure of Ta or a three-layer structure of Ta / TaN / Ta can be used. Among them, TiN, TiN / T
i, Ta, TaN, TaN / Ta and Ta / TaN / T
Preferably, it is made of a material selected from the group consisting of a. The diffusion preventing layer can be formed, for example, by sputtering or CV.
It can be formed by Method D. If the second conductive layer is to be formed directly on the diffusion preventing layer made of these materials, the second conductive layer cannot be formed on the diffusion preventing layer, or the diffusion preventing layer and the second conductive layer cannot be formed. In some cases, good adhesion cannot be obtained with the second conductive layer.

【００１５】基体として、シリコン半導体基板、シリコ
ン半導体基板上に形成された絶縁層（下層絶縁層）、シ
リコン半導体基板上に形成された絶縁層（下層絶縁層）
及びかかる絶縁層に形成された下層配線や接続孔の組合
せを例示することができる。また、層間絶縁層を構成す
る材料として、ＳｉＯ2、ＳｉＮ、ＳｉＯＮ、ＳｉＯ
Ｆ、ＳｉＣ、誘電率ｋ（＝ε／ε0）が例えば３．５以
下の有機ＳＯＧ、ポリイミド系樹脂、フッ素系樹脂とい
った低誘電率絶縁材料（例えば、フルオロカーボン、ア
モルファス・テトラフルオロエチレン、ポリアリールエ
ーテル、フッ化アリールエーテル、フッ化ポリイミド、
パリレン、ベンゾシクロブテン、アモルファス・カーボ
ン、シクロパーフルオロカーボンポリマー、フッ化フラ
ーレン）を挙げることができ、あるいは又、層間絶縁層
をこれらの材料の積層体から構成することもできる。As the base, a silicon semiconductor substrate, an insulating layer formed on the silicon semiconductor substrate (lower insulating layer), and an insulating layer formed on the silicon semiconductor substrate (lower insulating layer)
And combinations of lower wirings and connection holes formed in the insulating layer. Further, as a material constituting the interlayer insulating layer, SiO 2 , SiN, SiON, SiO
F, SiC, low dielectric constant insulating materials such as organic SOG having a dielectric constant k (= ε / ε 0 ) of 3.5 or less, polyimide-based resin, fluorine-based resin (for example, fluorocarbon, amorphous tetrafluoroethylene, polyaryl) Ether, fluorinated aryl ether, fluorinated polyimide,
Parylene, benzocyclobutene, amorphous carbon, cycloperfluorocarbon polymer, and fullerene fluoride), or the interlayer insulating layer can be formed of a laminate of these materials.

【００１６】本発明は、各種の半導体装置の製造方法に
適用することができ、具体的には、例えば、ＣＭＯＳＬ
ＳＩ、ＭＯＳＬＳＩ、バイポーラＬＳＩ、バイポーラＣ
ＭＯＳＬＳＩ等の製造に適用することができ、更には、
固体撮像素子（イメージャー素子）、薄膜トランジスタ
等の製造にも適用することができる。The present invention can be applied to various semiconductor device manufacturing methods. Specifically, for example, CMOSL
SI, MOS LSI, bipolar LSI, bipolar C
It can be applied to the manufacture of MOS LSI and the like.
The present invention can be applied to the manufacture of a solid-state imaging device (imager device), a thin film transistor, and the like.

【００１７】本発明の半導体装置の製造方法によれば、
電解めっき法によって第２の導電層を形成する際のシー
ド層として機能する第１の導電層を無電解めっき法によ
って形成するので、第１の導電層を、従来のスパッタ法
やＣＶＤ法にて形成する場合と比較して、コンフォーマ
ルに、且つ、良好なステップカバレッジにて、均一に凹
部内に形成することができる。According to the method of manufacturing a semiconductor device of the present invention,
Since the first conductive layer functioning as a seed layer when forming the second conductive layer by electrolytic plating is formed by electroless plating, the first conductive layer is formed by a conventional sputtering method or CVD method. Compared to the case of forming, it can be formed in the recess more uniformly and with better step coverage.

【００１８】また、第１の導電層上に電解めっき法によ
って第２の導電層を形成するが、この電解めっきの基本
原理は次の通りである。即ち、電解めっきにおいては、
第１の導電層が形成された基体（例えば、シリコン半導
体基板）をめっき浴中に浸漬し、第１の導電層が陰極、
めっき浴中の電極板が陽極となるような電界を印加す
る。めっき浴中の陽イオンは、電界の作用によって陰極
である基体側に付着する。これによって、第１の導電層
上に第２の導電層が堆積する。このとき、第１の導電層
が、コンフォーマルに、良好なステップカバレッジで均
一に形成されているので、第１の導電層上の第２の導電
層の成長速度も均一になる。その結果、第２の導電層に
よって凹部を確実に埋め込むことができる。A second conductive layer is formed on the first conductive layer by electrolytic plating. The basic principle of the electrolytic plating is as follows. That is, in electrolytic plating,
A substrate (eg, a silicon semiconductor substrate) on which the first conductive layer is formed is immersed in a plating bath, and the first conductive layer is
An electric field is applied so that the electrode plate in the plating bath becomes an anode. The cations in the plating bath adhere to the substrate, which is the cathode, by the action of the electric field. Thereby, a second conductive layer is deposited on the first conductive layer. At this time, since the first conductive layer is conformally and uniformly formed with good step coverage, the growth rate of the second conductive layer on the first conductive layer is also uniform. As a result, the recess can be reliably filled with the second conductive layer.

【００１９】[0019]

【発明の実施の形態】以下、図面を参照して、発明の実
施の形態（以下、実施の形態と略称する）に基づき本発
明の半導体装置の製造方法を説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method for manufacturing a semiconductor device according to the present invention will be described below with reference to the drawings based on an embodiment of the present invention (hereinafter, simply referred to as an embodiment).

【００２０】（実施の形態１）実施の形態１の半導体装
置の製造方法においては、凹部は開口部（孔部）から構
成されており、所謂、ビアホールを層間絶縁層に形成す
る。また、基体は、シリコン半導体基板の上に形成され
た下層絶縁層と、かかる下層絶縁層に形成された下層配
線との組合せから構成されている。更には、層間絶縁層
上（層間絶縁層の表面）に配線がビアホールと一体に形
成される。以下、層間絶縁層等の模式的な一部断面図で
ある図１及び図２を参照して、実施の形態１の半導体装
置の製造方法を説明する。(Embodiment 1) In the method of manufacturing a semiconductor device according to Embodiment 1, the recess is formed by an opening (hole), and a so-called via hole is formed in the interlayer insulating layer. The base is composed of a combination of a lower insulating layer formed on the silicon semiconductor substrate and a lower wiring formed on the lower insulating layer. Further, the wiring is formed integrally with the via hole on the interlayer insulating layer (the surface of the interlayer insulating layer). Hereinafter, a method for manufacturing the semiconductor device of the first embodiment will be described with reference to FIGS. 1 and 2 which are schematic partial cross-sectional views of an interlayer insulating layer and the like.

【００２１】［工程−１００］先ず、通常の半導体装置
の製造工程に基づきトランジスタ等の素子（図示せず）
が形成されたシリコン半導体基板（図示せず）上にＣＶ
Ｄ法に基づきＳｉＯ2から成る下層絶縁層１１を形成し
た後、下層絶縁層１１上に下層配線１２を形成する。下
層配線１２は、例えば、バリア層としてのＴｉＮ／Ｔｉ
層１２Ａ、銅層１２Ｂ、及びリソグラフィ工程で必要と
される反射防止膜として機能するＴｉＮ層１２Ｃが順次
積層された構造を有する。こうして、下層絶縁層１２、
及び下層絶縁層１１に形成された下層配線１２の組合せ
から構成された基体１０（図１の（Ａ）参照）を得るこ
とができる。ここで、下層配線１２は、図面の紙面に対
して垂直方向に延びている。[Step-100] First, an element such as a transistor (not shown) is manufactured based on a normal semiconductor device manufacturing process.
CV on a silicon semiconductor substrate (not shown) on which
After the lower insulating layer 11 made of SiO 2 is formed based on the method D, the lower wiring 12 is formed on the lower insulating layer 11. The lower wiring 12 is made of, for example, TiN / Ti as a barrier layer.
It has a structure in which a layer 12A, a copper layer 12B, and a TiN layer 12C functioning as an anti-reflection film required in a lithography step are sequentially stacked. Thus, the lower insulating layer 12,
A base 10 (see FIG. 1A) composed of a combination of the lower wiring 12 formed on the lower insulating layer 11 can be obtained. Here, the lower wiring 12 extends in a direction perpendicular to the plane of the drawing.

【００２２】［工程−１１０］次いで、基体１０上に、
厚さが例えば０．８μｍのＳｉＯ2から成る層間絶縁層
１３を、テトラエトキシシラン（ＴＥＯＳ）を用いたプ
ラズマＣＶＤ法によって形成する。そして、リソグラフ
ィ技術及びエッチング技術に基づき、下層配線１２の上
方の層間絶縁層１３に開口部（孔部）１４を形成する。
こうして、基体１０上に形成された層間絶縁層１３に、
基体である下層配線１２の一部が底部に露出した凹部で
ある開口部１４を設けることができる（図１の（Ｂ）参
照）。[Step-110] Next, on the substrate 10,
An interlayer insulating layer 13 made of SiO 2 having a thickness of, for example, 0.8 μm is formed by a plasma CVD method using tetraethoxysilane (TEOS). Then, based on the lithography technique and the etching technique, an opening (hole) 14 is formed in the interlayer insulating layer 13 above the lower wiring 12.
Thus, the interlayer insulating layer 13 formed on the base 10
An opening 14 which is a concave portion in which a part of the lower wiring 12 serving as a base is exposed at the bottom can be provided (see FIG. 1B).

【００２３】尚、ＳｉＯ2の代わりに、低誘電率絶縁材
料を用いてもよい。この場合には、基体上に低誘電率絶
縁材料をスピンコート法にて形成した後、例えば４００
゜Ｃ程度で低誘電率絶縁材料をキュアすることによっ
て、層間絶縁層を得ることができる。このとき、ＳｉＯ
2から成る絶縁層を形成し、その上に低誘電率絶縁材料
から成る絶縁層を形成してもよく、この場合には２層の
絶縁層から層間絶縁層が構成される。Note that a low dielectric constant insulating material may be used instead of SiO 2 . In this case, after a low dielectric constant insulating material is formed on the base by spin coating, for example, 400
By curing the low dielectric constant insulating material at about ゜ C, an interlayer insulating layer can be obtained. At this time, SiO
An insulating layer made of 2 may be formed, and an insulating layer made of a low dielectric constant insulating material may be formed thereon. In this case, an interlayer insulating layer is formed from two insulating layers.

【００２４】［工程−１２０］その後、例えばスパッタ
法に基づき、開口部１４内を含む層間絶縁層１３上に、
厚さが例えば５０ｎｍのＴｉＮから成る拡散防止層１５
を形成する。拡散防止層１５の形成条件の一例を、以下
の表１に示す。あるいは又、厚さが例えば３０ｎｍのＴ
ａＮから成る拡散防止層１５を形成してもよい。かかる
拡散防止層１５の形成条件を、以下の表２に例示する。[Step-120] After that, the interlayer insulating layer 13 including the inside of the opening 14 is
Diffusion prevention layer 15 made of TiN having a thickness of, for example, 50 nm
To form Table 1 below shows an example of the conditions for forming the diffusion prevention layer 15. Alternatively, a T having a thickness of, for example, 30 nm
A diffusion prevention layer 15 made of aN may be formed. The conditions for forming the diffusion preventing layer 15 are exemplified in Table 2 below.

【００２５】［表１］ ターゲット ：Ｔｉ プロセスガス：Ａｒ／Ｎ2＝６０／１２０ SCCM 圧力 ：０．６７Ｐａ ＤＣ電力 ：８ｋＷ 形成温度 ：２００゜Ｃ[Table 1] Target: Ti Process gas: Ar / N 2 = 60/120 SCCM Pressure: 0.67 Pa DC power: 8 kW Formation temperature: 200 ° C

【００２６】［表２］ ターゲット ：Ｔａ プロセスガス：Ａｒ／Ｎ2＝２０／７０ SCCM 圧力 ：０．３Ｐａ ＤＣ電力 ：１２ｋＷ 形成温度 ：２００゜Ｃ[Table 2] Target: Ta Process gas: Ar / N 2 = 20/70 SCCM Pressure: 0.3 Pa DC power: 12 kW Forming temperature: 200 ° C.

【００２７】［工程−１３０］次に、キャタリスト処
理、アクセラレーター処理を行った後、凹部である開口
部１４内を含む層間絶縁層１３上に、実施の形態１にお
いては、より具体的には拡散防止層１５上に、無電解め
っき法によってシード層として機能する第１の導電層１
６を形成する（図１の（Ｃ）参照）。第１の導電層１６
は銅（Ｃｕ）から成り、厚さは例えば５０ｎｍである。
第１の導電層１６の形成条件を、以下の表３に例示す
る。尚、めっき液中には微量の安定剤及び湿潤剤が添加
されている。[Step-130] Next, after performing the catalyst processing and the accelerator processing, in the first embodiment, more specifically, on the interlayer insulating layer 13 including the inside of the opening 14 which is a concave portion. Denotes a first conductive layer 1 functioning as a seed layer on the diffusion prevention layer 15 by electroless plating.
6 (see FIG. 1C). First conductive layer 16
Is made of copper (Cu) and has a thickness of, for example, 50 nm.
Table 3 below shows the conditions for forming the first conductive layer 16. Note that trace amounts of a stabilizer and a wetting agent are added to the plating solution.

【００２８】 ［表３］ めっき液 ：硫酸銅（ＣｕＳＯ4・５Ｈ2Ｏ） ７ｇ／リットル ホルマリン（３７％ＨＣＨＯ） ２０ｍｌ／リットル 水酸化ナトリウム（ＮａＯＨ） １０ｇ／リットル 酒石酸ナトリウムカリウム ２０ｇ／リットル めっき浴温度：５０゜Ｃ[Table 3] Plating solution: copper sulfate (CuSO 4 .5H 2 O) 7 g / liter formalin (37% HCHO) 20 ml / liter sodium hydroxide (NaOH) 10 g / liter sodium potassium tartrate 20 g / liter Plating bath temperature ： 50 ℃

【００２９】無電解めっき法によって形成された第１の
導電層１６は、ステップカバレッジが良好であり、厚さ
が均一である。また、無電解めっき法によって形成され
た第１の導電層１６においては、その結晶粒が、通常、
最稠密原子面の（１１１）面配向をしており、エレクト
ロマイグレーション耐性に優れている。The first conductive layer 16 formed by the electroless plating method has a good step coverage and a uniform thickness. In the first conductive layer 16 formed by the electroless plating method, the crystal grains are usually
It has the (111) plane orientation of the closest atomic plane, and has excellent electromigration resistance.

【００３０】［工程−１４０］次に、第１の導電層１６
上に電解めっき法によって第２の導電層１７を形成し
て、以て、凹部である開口部１４を第２の導電層１７で
埋め込み、ビアホール１８を完成させる（図２の（Ａ）
参照）。銅（Ｃｕ）から成る第２の導電層１７の厚さ
は、開口部１４内が完全に埋め込まれるような厚さとす
ればよい。第２の導電層１７の形成条件を、以下の表４
に例示する。[Step-140] Next, the first conductive layer 16
A second conductive layer 17 is formed thereon by an electrolytic plating method, and the opening 14 which is a recess is filled with the second conductive layer 17 to complete a via hole 18 (FIG. 2A).
reference). The thickness of the second conductive layer 17 made of copper (Cu) may be such that the inside of the opening 14 is completely buried. The conditions for forming the second conductive layer 17 are shown in Table 4 below.
An example is shown below.

【００３１】［表４］ めっき液 ：ＣｕＳＯ4・５Ｈ2Ｏ めっき浴温度：３０゜Ｃ 電圧 ：１０Ｖ 電流密度 ：２０Ａ／ｄｍ2 陽極板 ：Ｃｕ板[Table 4] Plating solution: CuSO 4 .5H 2 O Plating bath temperature: 30 ° C. Voltage: 10 V Current density: 20 A / dm 2 Anode plate: Cu plate

【００３２】［工程−１５０］その後、リソグラフィ技
術及びドライエッチング技術に基づき、銅から成る第２
の導電層１７、銅から成る第１の導電層１６、及びＴｉ
Ｎから成る拡散防止層１５を所望の配線形状にパターニ
ングする（図２の（Ｂ）参照）。ドライエッチングの条
件を、以下の表５に例示する。これによって、層間絶縁
層１３上に上層配線１９がビアホール１８と一体に形成
される。[Step-150] Thereafter, a second layer made of copper is formed based on a lithography technique and a dry etching technique.
Conductive layer 17, a first conductive layer 16 made of copper, and Ti
The diffusion preventing layer 15 made of N is patterned into a desired wiring shape (see FIG. 2B). Table 5 shows examples of the dry etching conditions. As a result, the upper wiring 19 is formed integrally with the via hole 18 on the interlayer insulating layer 13.

【００３３】［表５］ エッチングガス：ＳｉＣｌ4／Ｎ2＝１０／１００ SCCM 圧力 ：２６Ｐａ ＲＦ電力 ：５００Ｗ エッチング温度：３００゜Ｃ[Table 5] Etching gas: SiCl 4 / N 2 = 10/100 SCCM Pressure: 26 Pa RF power: 500 W Etching temperature: 300 ° C.

【００３４】その後、通常の半導体装置の製造工程によ
り、上部絶縁層や配線保護層等の形成工程を経て、半導
体装置を完成させる。Thereafter, the semiconductor device is completed through a process of forming an upper insulating layer, a wiring protection layer, and the like in a normal semiconductor device manufacturing process.

【００３５】尚、［工程−１５０］において、以下の表
６に例示する条件のＣＭＰ法に基づき、層間絶縁層１３
上の第２の導電層１７、第１の導電層１６、及び拡散防
止層１５を除去した後、層間絶縁層１３上に配線材料層
を例えばスパッタ法にて形成し、かかる配線材料層をパ
ターニングすることによって上層配線を形成してもよ
い。層間絶縁層１３上の第２の導電層１７、第１の導電
層１６、及び拡散防止層１５の除去はＣＭＰ法に限定さ
れず、例えばエッチバック法に基づき行ってもよい。In [Step-150], the interlayer insulating layer 13 is formed based on the CMP method under the conditions exemplified in Table 6 below.
After removing the upper second conductive layer 17, the first conductive layer 16, and the diffusion preventing layer 15, a wiring material layer is formed on the interlayer insulating layer 13 by, for example, a sputtering method, and the wiring material layer is patterned. By doing so, an upper layer wiring may be formed. The removal of the second conductive layer 17, the first conductive layer 16, and the diffusion prevention layer 15 on the interlayer insulating layer 13 is not limited to the CMP method, but may be performed based on, for example, an etch-back method.

【００３６】 ［表６］ 研磨材 ：過酸化水素水にＦｅＮＯ3を懸濁させたスラリー 研磨材流量 ：２０ SCCM 研磨ヘッド圧力：０．２８ｋｇｆ／ｃｍ2 基板回転数 ：２０ｒｐｍ ヘッド回転数 ：２０ｒｐｍ[Table 6] Abrasive material: slurry in which FeNO 3 is suspended in aqueous hydrogen peroxide Abrasive material flow rate: 20 SCCM Polishing head pressure: 0.28 kgf / cm 2 Substrate rotation speed: 20 rpm Head rotation speed: 20 rpm

【００３７】（実施の形態２）実施の形態２の半導体装
置の製造方法においては、凹部は溝部から構成されてい
る。そして、ビアホールを下層層間絶縁層に形成した
後、ビアホールに接続された溝配線を層間絶縁層に形成
する。即ち、実施の形態２はシングル・ダマシン法に関
する。尚、ビアホールの形成方法は実施の形態１に基づ
いてもよいし、異なる形成方法を採用してもよい。ま
た、基体は、下層絶縁層の上に形成された下層層間絶縁
層と、かかる下層層間絶縁層に形成されたビアホールと
の組合せから構成されている。以下、層間絶縁層等の模
式的な一部断面図である図３及び図４を参照して、実施
の形態２の半導体装置の製造方法を説明する。尚、拡散
防止層及び溝配線が形成される層間絶縁層を、実施の形
態１における拡散防止層及び層間絶縁層と峻別するため
に、実施の形態２においては、第２の拡散防止層及び第
２の層間絶縁層と呼ぶ。また、ビアホールが形成され
た、基体を構成する下層層間絶縁層を、以下、層間絶縁
層１３と呼ぶ。(Second Embodiment) In a method of manufacturing a semiconductor device according to a second embodiment, the recess is formed by a groove. Then, after forming a via hole in the lower interlayer insulating layer, a trench wiring connected to the via hole is formed in the interlayer insulating layer. That is, the second embodiment relates to the single damascene method. The via hole forming method may be based on the first embodiment or a different forming method may be adopted. The base is composed of a combination of a lower interlayer insulating layer formed on the lower insulating layer and a via hole formed in the lower interlayer insulating layer. Hereinafter, a method of manufacturing the semiconductor device according to the second embodiment will be described with reference to FIGS. 3 and 4 which are schematic partial cross-sectional views of an interlayer insulating layer and the like. Note that, in order to distinguish the diffusion preventing layer and the interlayer insulating layer in which the trench wiring is formed from the diffusion preventing layer and the interlayer insulating layer in the first embodiment, the second diffusion preventing layer and the second It is referred to as a second interlayer insulating layer. Further, the lower interlayer insulating layer forming the base and having the via hole formed therein is hereinafter referred to as an interlayer insulating layer 13.

【００３８】［工程−２００］先ず、実施の形態１の
［工程−１００］〜［工程−１４０］を実行した後、表
６に示した条件のＣＭＰ法に基づき、層間絶縁層１３上
の第２の導電層１７、第１の導電層１６、及び拡散防止
層１５を除去する（図３の（Ａ）参照）。こうして、ビ
アホール１８を得ることができる。尚、層間絶縁層１３
上の第２の導電層１７、第１の導電層１６、及び拡散防
止層１５の除去はＣＭＰ法に限定されず、例えばエッチ
バック法に基づき行ってもよい。[Step-200] First, after [Step-100] to [Step-140] of the first embodiment are performed, the first step on the interlayer insulating layer 13 is performed based on the CMP method under the conditions shown in Table 6. The second conductive layer 17, the first conductive layer 16, and the diffusion prevention layer 15 are removed (see FIG. 3A). Thus, the via hole 18 can be obtained. The interlayer insulating layer 13
The removal of the upper second conductive layer 17, the first conductive layer 16, and the diffusion prevention layer 15 is not limited to the CMP method, but may be performed based on, for example, an etch-back method.

【００３９】また、実施の形態２におけるビアホールの
形成方法は、上述の形成方法に限定されず、例えば、所
謂、ブランケットＣＶＤタングステン法を採用してもよ
い。ここでブランケットＣＶＤタングステン法とは、層
間絶縁層１３に形成された開口部１４内を含む層間絶縁
層１３上に、Ｔｉ層及びＴｉＮ層を順次形成し、次い
で、開口部１４内を含む層間絶縁層１３上にＣＶＤ法に
てタングステン層を形成した後、層間絶縁層１３上のタ
ングステン層、ＴｉＮ層、Ｔｉ層を除去する方法であ
る。The method of forming a via hole in the second embodiment is not limited to the above-described method, and for example, a so-called blanket CVD tungsten method may be employed. Here, the blanket CVD tungsten method means that a Ti layer and a TiN layer are sequentially formed on the interlayer insulating layer 13 including the inside of the opening 14 formed in the interlayer insulating layer 13, and then the interlayer insulating layer including the inside of the opening 14 is formed. After a tungsten layer is formed on the layer 13 by a CVD method, the tungsten layer, the TiN layer, and the Ti layer on the interlayer insulating layer 13 are removed.

【００４０】［工程−２１０］その後、厚さが例えば
０．６μｍのＳｉＯ2から成る第２の層間絶縁層２３を
ＣＶＤ法に基づき全面に形成する。そして、ビアホール
１８の上方の第２の層間絶縁層２３に、リソグラフィ技
術及びドライエッチング技術に基づき溝部２４を形成す
る（図３の（Ｂ）参照）。ここで、溝部２４は、図面の
紙面に対して垂直方向に延びている。[Step-210] Thereafter, a second interlayer insulating layer 23 made of SiO 2 having a thickness of, for example, 0.6 μm is formed on the entire surface by the CVD method. Then, a groove 24 is formed in the second interlayer insulating layer 23 above the via hole 18 based on a lithography technique and a dry etching technique (see FIG. 3B). Here, the groove 24 extends in a direction perpendicular to the plane of the drawing.

【００４１】［工程−２２０］次に、表１に示した条件
にて、溝部２４内を含む第２の層間絶縁層２３上に、厚
さが例えば５０ｎｍのＴｉＮから成る第２の拡散防止層
２５を形成する。その後、凹部である溝部２４内を含む
第２の層間絶縁層２３上に、より具体的には第２の拡散
防止層２５上に、無電解めっき法によって第１の導電層
２６を形成する。第１の導電層２６は、シード層として
機能し、厚さ５０ｎｍの銅（Ｃｕ）から成る。第１の導
電層２６は、表３に例示した条件に基づき形成すること
ができる。[Step-220] Next, under the conditions shown in Table 1, a second diffusion preventing layer made of TiN having a thickness of, for example, 50 nm is formed on the second interlayer insulating layer 23 including the inside of the groove 24. 25 are formed. After that, the first conductive layer 26 is formed by electroless plating on the second interlayer insulating layer 23 including the inside of the groove 24 which is a concave portion, more specifically, on the second diffusion prevention layer 25. The first conductive layer 26 functions as a seed layer and is made of 50 nm thick copper (Cu). The first conductive layer 26 can be formed based on the conditions exemplified in Table 3.

【００４２】［工程−２３０］次に、第１の導電層２６
上に、表４に例示した条件の電解めっき法によって第２
の導電層２７を形成して、以て、凹部である溝部２４を
第２の導電層２７で埋め込む（図４の（Ａ）参照）。銅
（Ｃｕ）から成る第２の導電層２７の厚さは、溝部２４
内が完全に埋め込まれるような厚さとすればよい。[Step-230] Next, the first conductive layer 26
Above, the second plating was performed by the electrolytic plating method under the conditions exemplified in Table 4.
Then, the groove 24 as a concave portion is buried with the second conductive layer 27 (see FIG. 4A). The thickness of the second conductive layer 27 made of copper (Cu)
The thickness may be such that the inside is completely embedded.

【００４３】［工程−２４０］その後、表６に示した条
件のＣＭＰ法に基づき、第２の層間絶縁層２３上の第２
の導電層２７、第１の導電層２６、及び第２の拡散防止
層２５を除去する（図４の（Ｂ）参照）。これによっ
て、凹部である溝部２４が第２の導電層２７で埋め込ま
れた溝配線２８が完成する。尚、第２の層間絶縁層２３
上の第２の導電層２７、第１の導電層２６、及び第２の
拡散防止層２５の除去はＣＭＰ法に限定されず、例えば
エッチバック法に基づき行ってもよい。[Step-240] Then, based on the CMP method under the conditions shown in Table 6, the second
Of the conductive layer 27, the first conductive layer 26, and the second diffusion prevention layer 25 are removed (see FIG. 4B). As a result, the groove wiring 28 in which the groove 24 as the concave portion is buried with the second conductive layer 27 is completed. The second interlayer insulating layer 23
The removal of the upper second conductive layer 27, the first conductive layer 26, and the second diffusion prevention layer 25 is not limited to the CMP method, but may be performed based on, for example, an etch-back method.

【００４４】その後、通常の半導体装置の製造工程によ
り、上部絶縁層や配線保護層等の形成工程を経て、半導
体装置を完成させる。Thereafter, the semiconductor device is completed through a process of forming an upper insulating layer, a wiring protection layer, and the like in a normal semiconductor device manufacturing process.

【００４５】（実施の形態３）実施の形態３の半導体装
置の製造方法においては、凹部は開口部及び溝部の組合
せから構成されている。そして、層間絶縁層にビアホー
ルと溝配線とを一体的に形成する。即ち、実施の形態３
はデュアル・ダマシン法に関する。また、基体は、シリ
コン半導体基板の上に形成された下層絶縁層と、かかる
下層絶縁層上に形成された下層配線との組合せから構成
されている。以下、層間絶縁層等の模式的な一部断面図
である図５〜図７を参照して、実施の形態３の半導体装
置の製造方法を説明する。(Embodiment 3) In the method of manufacturing a semiconductor device according to Embodiment 3, the recess is formed by a combination of an opening and a groove. Then, via holes and trench wirings are integrally formed in the interlayer insulating layer. That is, Embodiment 3
Relates to the dual damascene method. The base is composed of a combination of a lower insulating layer formed on the silicon semiconductor substrate and a lower wiring formed on the lower insulating layer. Hereinafter, a method for manufacturing the semiconductor device of the third embodiment will be described with reference to FIGS. 5 to 7 which are schematic partial cross-sectional views of the interlayer insulating layer and the like.

【００４６】［工程−３００］先ず、実施の形態１の
［工程−１００］と同様の工程を実行する。[Step-300] First, the same step as [Step-100] of the first embodiment is performed.

【００４７】［工程−３１０］次いで、基体１０上に、
厚さが例えば０．８μｍのＳｉＯ2から成る第１の絶縁
層３３Ａをテトラエトキシシラン（ＴＥＯＳ）を用いた
プラズマＣＶＤ法に基づき形成する。次いで、第１の絶
縁層３３Ａ上に例えば減圧ＣＶＤ（ＬＰＣＶＤ）法やプ
ラズマＣＶＤ法等により、ＳｉＮから成り、厚さが例え
ば５０ｎｍの第２の絶縁層３３Ｂを形成する。プラズマ
ＣＶＤ法に基づく第２の絶縁層３３Ｂの形成条件を、以
下の表７に例示する。[Step-310] Next, on the substrate 10,
A first insulating layer 33A made of SiO 2 having a thickness of, for example, 0.8 μm is formed by a plasma CVD method using tetraethoxysilane (TEOS). Next, a second insulating layer 33B made of SiN and having a thickness of, for example, 50 nm is formed on the first insulating layer 33A by, for example, a low pressure CVD (LPCVD) method or a plasma CVD method. Table 7 below shows conditions for forming the second insulating layer 33B based on the plasma CVD method.

【００４８】 ［表７］ 反応ガス：ＳｉＨ4／ＮＨ3／Ｎ2＝２６５／１００／４０００ SCCM 圧力 ：５６５Ｐａ 温度 ：４００゜Ｃ[Table 7] Reaction gas: SiH 4 / NH 3 / N 2 = 265/100/4000 SCCM Pressure: 565 Pa Temperature: 400 ° C

【００４９】次に、リソグラフィ技術及びドライエッチ
ング技術に基づき、第２の絶縁層３３Ｂに直径０．３μ
ｍの孔部３３ｂを形成する（図５の（Ａ）参照）。その
後、例えばＣＶＤ法に基づき全面に厚さが例えば０．５
μｍの第３の絶縁層３３Ｃを形成する。第３の絶縁層を
構成する材料は、第１の絶縁層３３Ａと同様とすればよ
い。こうして、３層構成の層間絶縁層３３を得ることが
できる。次に、層間絶縁層３３の表面を例えばＣＭＰ法
に基づき研磨して平坦化する。Next, based on the lithography technique and the dry etching technique, the second insulating layer 33B has a diameter of 0.3 μm.
An m-shaped hole 33b is formed (see FIG. 5A). Thereafter, for example, a thickness of 0.5
A third insulating layer 33C of μm is formed. The material forming the third insulating layer may be the same as that of the first insulating layer 33A. Thus, a three-layered interlayer insulating layer 33 can be obtained. Next, the surface of the interlayer insulating layer 33 is polished and flattened based on, for example, a CMP method.

【００５０】次に、層間絶縁層３３上にリソグラフィ技
術に基づきレジスト材料から成るエッチング用マスクを
形成した後、このエッチング用マスクを用いて第３の絶
縁層３３Ｃを例えばＲＩＥ法にてエッチングする。これ
によって、第３の絶縁層３３Ｃに溝部３４Ａが形成され
る（図５の（Ｂ）参照）。ここで、溝部３４Ａは、図面
の紙面に対して垂直方向に延びている。第３の絶縁層３
３Ｃのエッチングの際には、ＳｉＮから成る第２の絶縁
層３３Ｂがエッチングストッパーとして働く。更に、第
２の絶縁層３３Ｂが露出してからは、第２の絶縁層３３
Ｂをエッチング用マスクとして第１の絶縁層３３Ａをエ
ッチングすることによって、開口部（孔部）３４Ｂを溝
部３４Ａの底面に形成する（図６の（Ａ）参照）。こう
して、基体１０上に形成された層間絶縁層３３に、基体
である下層配線１２の一部が底部に露出した凹部である
開口部３４Ｂ及び溝部３４Ａを設けることができる。第
１及び第３の絶縁層３３Ａ，３３ＣをＳｉＯ2から構成
する場合のエッチング条件を、以下の表８に例示する。
また、第１及び第３の絶縁層３３Ａ，３３Ｃを有機系の
低誘電率絶縁材料から構成する場合のエッチング条件
を、以下の表９に例示する。Next, after forming an etching mask made of a resist material on the interlayer insulating layer 33 based on the lithography technique, the third insulating layer 33C is etched using the etching mask by, for example, RIE. Thus, a groove 34A is formed in the third insulating layer 33C (see FIG. 5B). Here, the groove 34A extends in a direction perpendicular to the plane of the drawing. Third insulating layer 3
During the 3C etching, the second insulating layer 33B made of SiN functions as an etching stopper. Further, after the second insulating layer 33B is exposed, the second insulating layer 33B is exposed.
An opening (hole) 34B is formed on the bottom surface of the groove 34A by etching the first insulating layer 33A using B as an etching mask (see FIG. 6A). Thus, in the interlayer insulating layer 33 formed on the base 10, the openings 34B and the grooves 34A, which are recesses in which a part of the lower wiring 12 as the base is exposed at the bottom, can be provided. The etching conditions when the first and third insulating layers 33A and 33C are made of SiO 2 are shown in Table 8 below.
Table 9 below shows examples of etching conditions when the first and third insulating layers 33A and 33C are made of an organic low dielectric constant insulating material.

【００５１】［表８］ エッチングガス：Ｃ4Ｆ8＝５０ SCCM 圧力 ：２Ｐａ ＲＦパワー ：１．２ｋＷ[Table 8] Etching gas: C 4 F 8 = 50 SCCM Pressure: 2 Pa RF power: 1.2 kW

【００５２】 ［表９］ エッチングガス：ＣＨＦ3／Ｏ2／Ｈｅ＝５／５０／２００ SCCM 温度 ：−１０゜Ｃ ＲＦパワー ：０．５ｋＷ[Table 9] Etching gas: CHF 3 / O 2 / He = 5/50/200 SCCM Temperature: -10 ° C RF power: 0.5 kW

【００５３】尚、リソグラフィ技術及びドライエッチン
グ技術に基づき、先ず、第３の絶縁層３３Ｃ、第２の絶
縁層３３Ｂ及び第１の絶縁層３３Ａを貫通する開口部を
形成した後、再び、リソグラフィ技術及びドライエッチ
ング技術に基づき、第３の絶縁層３３Ｃに溝部を形成し
てもよい。この場合、第３の絶縁層３３Ｃに溝部を形成
する際、ＳｉＮから成る第２の絶縁層３３Ｂがエッチン
グストッパーとして働く。Incidentally, based on the lithography technique and the dry etching technique, first, an opening penetrating through the third insulating layer 33C, the second insulating layer 33B and the first insulating layer 33A is formed, and then the lithography technique is again performed. A groove may be formed in the third insulating layer 33C based on a dry etching technique. In this case, when forming a groove in the third insulating layer 33C, the second insulating layer 33B made of SiN functions as an etching stopper.

【００５４】［工程−３２０］その後、例えばスパッタ
法に基づき、溝部３４Ａ及び開口部３４Ｂ内を含む層間
絶縁層３３上に、厚さが例えば５０ｎｍのＴｉＮから成
る拡散防止層３５を形成する。拡散防止層３５の形成条
件は、例えば表１と同様とすればよい。[Step-320] Thereafter, a diffusion prevention layer 35 made of TiN having a thickness of, for example, 50 nm is formed on the interlayer insulating layer 33 including the inside of the groove 34A and the opening 34B by, for example, a sputtering method. The conditions for forming the diffusion prevention layer 35 may be the same as those in Table 1, for example.

【００５５】［工程−３３０］次に、凹部である溝部３
４Ａ及び開口部３４Ｂ内を含む層間絶縁層３３上に、実
施の形態３においては、より具体的には拡散防止層３５
上に、無電解めっき法によって第１の導電層３６を形成
する（図６の（Ｂ）参照）。第１の導電層３６は、シー
ド層として機能し、厚さ５０ｎｍの銅（Ｃｕ）から成
る。第１の導電層３６は、表３に例示した条件に基づき
形成することができる。[Step-330] Next, the groove 3 which is a concave portion
In the third embodiment, more specifically, the diffusion prevention layer 35 is formed on the interlayer insulating layer 33 including the inside of the opening 4A and the opening 34B.
A first conductive layer 36 is formed thereon by an electroless plating method (see FIG. 6B). The first conductive layer 36 functions as a seed layer and is made of copper (Cu) with a thickness of 50 nm. The first conductive layer 36 can be formed based on the conditions exemplified in Table 3.

【００５６】［工程−３４０］次に、第１の導電層３６
上に電解めっき法によって第２の導電層３７を形成し
て、以て、凹部である溝部３４Ａ及び開口部３４Ｂを第
２の導電層３７で埋め込み、ビアホール３８Ｂを完成さ
せる（図７の（Ａ）参照）。銅（Ｃｕ）から成る第２の
導電層３７の厚さは、溝部３４Ａ及び開口部３４Ｂ内が
完全に埋め込まれるような厚さ、例えば１．０μｍとす
ればよい。第２の導電層３７の形成条件は、例えば表４
と同様とすればよい。[Step-340] Next, the first conductive layer 36
The second conductive layer 37 is formed thereon by electrolytic plating, and the groove 34A and the opening 34B, which are concave portions, are filled with the second conductive layer 37 to complete the via hole 38B ((A in FIG. 7). )reference). The thickness of the second conductive layer 37 made of copper (Cu) may be a thickness such that the inside of the groove 34A and the opening 34B is completely buried, for example, 1.0 μm. The conditions for forming the second conductive layer 37 are described in, for example, Table 4 below.
The same may be applied.

【００５７】［工程−３５０］その後、表６に例示した
条件のＣＭＰ法に基づき、層間絶縁層３３上の第２の導
電層３７、第１の導電層３６及び拡散防止層３５を除去
する。これによって、凹部である溝部３４Ａが第２の導
電層３７で埋め込まれた溝配線３８Ａが完成する（図７
の（Ｂ）参照）。尚、かかる溝配線３８Ａとビアホール
３８Ｂとは一体に形成されている。[Step-350] After that, the second conductive layer 37, the first conductive layer 36, and the diffusion prevention layer 35 on the interlayer insulating layer 33 are removed based on the CMP method under the conditions exemplified in Table 6. As a result, a groove wiring 38A in which the groove 34A, which is a concave portion, is embedded in the second conductive layer 37 is completed.
(B)). The groove wiring 38A and the via hole 38B are formed integrally.

【００５８】その後、通常の半導体装置の製造工程によ
り、上部絶縁層や配線保護層等の形成工程を経て、半導
体装置を完成させる。Thereafter, the semiconductor device is completed through a process of forming an upper insulating layer, a wiring protection layer, and the like in a normal semiconductor device manufacturing process.

【００５９】（実施の形態４）以上に説明した各実施の
形態においては、第１の導電層を銅（Ｃｕ）から構成し
た。これに対して、実施の形態４においては、第１の導
電層をニッケル（Ｎｉ）から構成する。(Embodiment 4) In each of the embodiments described above, the first conductive layer is made of copper (Cu). On the other hand, in the fourth embodiment, the first conductive layer is made of nickel (Ni).

【００６０】無電解銅めっき法によって形成される銅層
における銅の結晶粒径は比較的大きくなり易い。それ
故、第１の導電層の厚さを薄く設定した場合、均一な厚
さの第１の導電層を形成することが困難となる場合があ
る。従って、均一な厚さの銅から成る第１の導電層を形
成しようとする場合、数十ｎｍの厚さが必要とされる。
ところで、無電解めっき法にて形成される層は、原理的
に等方的に成長するので、第１の導電層の厚さが厚くな
ると、開口部が縮径され、あるいは又、溝部の幅が狭く
なる。その結果、第２の導電層を形成する際の凹部の実
質的なアスペクト比が大きくなり、凹部内に新鮮な電解
めっき液が供給され難くなり、凹部内の第２の導電層に
ボイドが発生し易くなる場合がある。The crystal grain size of copper in the copper layer formed by the electroless copper plating method tends to be relatively large. Therefore, when the thickness of the first conductive layer is set to be small, it may be difficult to form the first conductive layer having a uniform thickness. Therefore, when a first conductive layer made of copper having a uniform thickness is to be formed, a thickness of several tens of nm is required.
By the way, the layer formed by the electroless plating grows isotropically in principle. Therefore, when the thickness of the first conductive layer is increased, the diameter of the opening is reduced or the width of the groove is reduced. Becomes narrower. As a result, the substantial aspect ratio of the concave portion when forming the second conductive layer increases, making it difficult to supply a fresh electrolytic plating solution into the concave portion, and generating a void in the second conductive layer in the concave portion. In some cases.

【００６１】このような場合には、薄い第１の導電層を
形成するために、例えば、無電解ニッケルめっき法を採
用すればよい。無電解ニッケルめっき法によって得られ
るニッケル結晶粒は柱状であり、薄い第１の導電層を、
ステップカバレッジ良く、均一に形成することができる
結果、第２の導電層を形成する際の凹部の実質的なアス
ペクト比の増加を抑制することができる。それ故、凹部
内の第２の導電層にボイドが発生し易くなるといった問
題の発生を回避することができる。また、無電解ニッケ
ルめっき浴の温度や組成の制御は無電解銅めっき浴より
も行い易く、第１の導電層の形成の自動化に一層適して
いるといった利点もある。また、ニッケルから成る第１
の導電層を形成すれば、第２の導電層を構成する例えば
銅原子が層間絶縁層中に拡散することを抑制し得るの
で、場合によっては、拡散防止層の形成を省略すること
ができる。言い換えれば、無電解ニッケルめっき法にて
ニッケルから成る第１の導電層を凹部内を含む層間絶縁
層上に直接形成することが可能である。In such a case, in order to form a thin first conductive layer, for example, an electroless nickel plating method may be employed. The nickel crystal grains obtained by the electroless nickel plating method are columnar, and the thin first conductive layer is formed by:
As a result, uniform formation can be performed with good step coverage, so that a substantial increase in the aspect ratio of the concave portion when the second conductive layer is formed can be suppressed. Therefore, it is possible to avoid a problem that a void is easily generated in the second conductive layer in the concave portion. Further, there is an advantage that the control of the temperature and composition of the electroless nickel plating bath is easier than the electroless copper plating bath, and is more suitable for automation of forming the first conductive layer. In addition, the first made of nickel
When the conductive layer is formed, the diffusion of, for example, copper atoms constituting the second conductive layer into the interlayer insulating layer can be suppressed, and in some cases, the formation of the diffusion preventing layer can be omitted. In other words, it is possible to form the first conductive layer made of nickel directly on the interlayer insulating layer including the inside of the recess by electroless nickel plating.

【００６２】ニッケルから成る厚さ１０ｎｍの第１の導
電層は、シプレー社の商品名キャタリスト９Ｆを用いた
キャタリスト処理、シプレー社の商品名アクセレレータ
２４０を用いたアクセラレーター処理を行った後、例え
ば、ソニー株式会社社製の無電解ニッケルめっき液（商
品名ＣＰ１、ＣＰ２、ＣＰ３、ＣＰ４及びＣＰ５の混合
液）を使用し、めっき浴の温度を５０゜Ｃとして、超音
波を併用して１分間基体を無電解ニッケルめっき浴に浸
漬することによって形成することができる。The first conductive layer made of nickel and having a thickness of 10 nm is subjected to a catalyst treatment using a trade name Catalyst 9F of Shipley and an accelerator treatment using an accelerator 240 of trade name of Shipley. For example, an electroless nickel plating solution (trade name of CP1, CP2, CP3, CP4, and CP5) manufactured by Sony Corporation is used, the temperature of the plating bath is set to 50 ° C., and ultrasonic waves are used in combination. It can be formed by immersing the substrate in an electroless nickel plating bath for minutes.

【００６３】以上、本発明を、発明の実施の形態に基づ
き説明したが、本発明はこれらに限定されるものではな
い。発明の実施の形態にて説明した各種の材料や条件は
例示であり、適宜変更することができるし、半導体装置
の構造も例示である。Although the present invention has been described based on the embodiments, the present invention is not limited to these embodiments. The various materials and conditions described in the embodiments of the invention are examples, can be changed as appropriate, and the structure of the semiconductor device is also an example.

【００６４】例えば、第１の導電層を、無電解めっき法
によって形成されたＴｉ層から構成することもできる。
この場合、めっき液として、硫酸チタンに触媒反応物質
としてＰｄＳを添加したものや、硫酸チタンにＨＣＨＯ
及びＨ2Ｏを添加したものを例示することができる。更
には、第１の導電層を、無電解めっき法によって形成さ
れたＴｉＮ層から構成することもできる。この場合、め
っき液として、ＮＨ4ＯＨ又はＨＮＯ3を含む硫酸チタン
に触媒反応物質としてＰｄＳを添加したものや、硫酸チ
タンにＨＣＨＯ及びＮＨ4ＯＨを添加したものを例示す
ることができる。For example, the first conductive layer may be constituted by a Ti layer formed by an electroless plating method.
In this case, as a plating solution, a solution obtained by adding PdS as a catalytic reactant to titanium sulfate or HCHO to titanium sulfate is used.
And H 2 O added. Further, the first conductive layer may be composed of a TiN layer formed by an electroless plating method. In this case, examples of the plating solution include those obtained by adding PdS as a catalytic reactant to titanium sulfate containing NH 4 OH or HNO 3 and those obtained by adding HCHO and NH 4 OH to titanium sulfate.

【００６５】第２の導電層を銀（Ａｇ）から構成するこ
ともできる。電解めっき法による銀から成る第２の導電
層の形成条件の一例を、表１０に挙げる。あるいは又、
第２の導電層を白金（Ｐｔ）から構成することもでき
る。電解めっき法による白金から成る第２の導電層の形
成条件の一例を、以下の表１１に挙げる。The second conductive layer can be made of silver (Ag). Table 10 shows an example of conditions for forming the second conductive layer made of silver by the electrolytic plating method. Alternatively,
The second conductive layer may be made of platinum (Pt). Table 11 below shows an example of conditions for forming the second conductive layer made of platinum by the electrolytic plating method.

【００６６】 [0066]

【００６７】 ［表１１］ めっき液 ：塩化白金酸 ４ｇ／リットル リン酸アンモニウム ２０ｇ／リットル リン酸ナトリウム １００ｇ／リットル めっき浴温度：８０゜Ｃ 電圧 ：４Ｖ 電流密度 ：１ｍＡ／ｄｍ2 [Table 11] Plating solution: chloroplatinic acid 4 g / l Ammonium phosphate 20 g / l sodium phosphate 100 g / l Plating bath temperature: 80 ° C Voltage: 4 V Current density: 1 mA / dm 2

【００６８】銅（Ｃｕ）から成る溝配線の酸化防止膜と
して、例えばＴｉＮから成るキャッピング層を溝配線の
表面に形成してもよい。キャッピング層は、以下の表１
２に例示するスパッタ条件にて全面に厚さ３０ｎｍのＴ
ｉＮ層を形成した後、リソグラフィ技術及びドライエッ
チング技術に基づきＴｉＮ層をパターニングすることに
よって形成することができる。ドライエッチング条件
を、以下の表１３に例示する。A capping layer made of, for example, TiN may be formed on the surface of the groove wiring as an oxidation preventing film for the groove wiring made of copper (Cu). The capping layer is shown in Table 1 below.
Under the sputtering conditions exemplified in FIG.
After forming the iN layer, the iN layer can be formed by patterning the TiN layer based on a lithography technique and a dry etching technique. Table 13 below shows examples of the dry etching conditions.

【００６９】［表１２］ ターゲット ：Ｔｉ プロセスガス：Ａｒ／Ｎ2＝３０／１００ SCCM 圧力 ：０．６７Ｐａ 温度 ：１５０゜Ｃ[Table 12] Target: Ti Process gas: Ar / N 2 = 30/100 SCCM Pressure: 0.67 Pa Temperature: 150 ° C.

【００７０】［表１３］ エッチングガス：ＢＣｌ3／Ｃｌ2＝６０／９０ SCCM 圧力 ：２Ｐａ ＲＦパワー ：１．２ｋＷ[Table 13] Etching gas: BCl 3 / Cl 2 = 60/90 SCCM Pressure: 2 Pa RF power: 1.2 kW

【００７１】[0071]

【発明の効果】本発明の半導体装置の製造方法によれ
ば、凹部内にシード層となる第１の導電層を無電解めっ
き法によって形成するので、第１の導電層を良好なステ
ップカバレッジで均一に形成することができる。そし
て、シード層として機能する第１の導電層上に電解めっ
き法によって第２の導電層を十分な厚さに形成すること
ができるので、高アスペクト比を凹部が有する場合であ
っても、良好な埋め込み性にて、しかも、高精度にて凹
部の埋め込みを行うことができ、凹部の埋め込み不良を
防止することができる。これによって、凹部内が第２の
導電層で完全に埋め込まれた接続孔、溝配線、あるいは
溝配線と接続孔の組合せを得ることができる。しかも、
第２の導電層を例えば銅（Ｃｕ）から構成すれば、低比
抵抗、且つ、優れたエレクトロマイグレーション耐性を
有することと相まって、信頼性の高い、高速動作可能な
高性能の半導体装置を高い歩留まりで製造することがで
きる。According to the method of manufacturing a semiconductor device of the present invention, since the first conductive layer serving as the seed layer is formed in the recess by the electroless plating method, the first conductive layer can be formed with good step coverage. It can be formed uniformly. Further, since the second conductive layer can be formed to a sufficient thickness by the electrolytic plating method on the first conductive layer functioning as a seed layer, even if the concave portion has a high aspect ratio, it is preferable. The recess can be filled with high embedding properties and with high accuracy, and defective embedding of the recess can be prevented. Thereby, it is possible to obtain a connection hole, a groove wiring, or a combination of the groove wiring and the connection hole in which the inside of the concave portion is completely filled with the second conductive layer. Moreover,
When the second conductive layer is made of, for example, copper (Cu), a high-performance semiconductor device with high reliability and high-speed operation can be obtained at a high yield, in addition to having low specific resistance and excellent electromigration resistance. Can be manufactured.

【図面の簡単な説明】[Brief description of the drawings]

【図１】発明の実施の形態１の半導体装置の製造方法を
説明するための層間絶縁層等の模式的な一部断面図であ
る。FIG. 1 is a schematic partial cross-sectional view of an interlayer insulating layer and the like for describing a method for manufacturing a semiconductor device according to a first embodiment of the present invention;

【図２】図１に引き続き、発明の実施の形態１の半導体
装置の製造方法を説明するための層間絶縁層等の模式的
な一部断面図である。FIG. 2 is a schematic partial cross-sectional view of an interlayer insulating layer and the like for explaining the method for manufacturing the semiconductor device of the first embodiment of the invention, following FIG. 1;

【図３】発明の実施の形態２の半導体装置の製造方法を
説明するための層間絶縁層等の模式的な一部断面図であ
る。FIG. 3 is a schematic partial cross-sectional view of an interlayer insulating layer and the like for describing a method of manufacturing a semiconductor device according to a second embodiment of the present invention;

【図４】図３に引き続き、発明の実施の形態２の半導体
装置の製造方法を説明するための層間絶縁層等の模式的
な一部断面図である。FIG. 4 is a schematic partial cross-sectional view of an interlayer insulating layer and the like for explaining the method for manufacturing the semiconductor device according to the second embodiment of the present invention, following FIG. 3;

【図５】発明の実施の形態３の半導体装置の製造方法を
説明するための層間絶縁層等の模式的な一部断面図であ
る。FIG. 5 is a schematic partial cross-sectional view of an interlayer insulating layer and the like for describing a method of manufacturing a semiconductor device according to a third embodiment of the present invention;

【図６】図５に引き続き、発明の実施の形態３の半導体
装置の製造方法を説明するための層間絶縁層等の模式的
な一部断面図である。FIG. 6 is a schematic partial cross-sectional view of an interlayer insulating layer and the like for describing the method for manufacturing the semiconductor device according to the third embodiment of the present invention, following FIG. 5;

【図７】図６に引き続き、発明の実施の形態３の半導体
装置の製造方法を説明するための層間絶縁層等の模式的
な一部断面図である。FIG. 7 is a schematic partial cross-sectional view of an interlayer insulating layer and the like for describing the method for manufacturing the semiconductor device according to the third embodiment of the present invention, following FIG. 6;

【符号の説明】[Explanation of symbols]

１０・・・基体、１１・・・下層絶縁層、１２・・・下
層配線、１３，２３，３３・・・層間絶縁層、１４，３
４Ｂ・・・開口部、１５，２５，３５・・・拡散防止
層、１６，２６，３６・・・第１の導電層、１７，２
７，３７・・・第２の導電層、１８，３８Ｂ・・・ビア
ホール、１９・・・上層配線、２４，３４Ａ・・・溝
部、２８，３８Ａ・・・溝配線、３３Ａ・・・第１の絶
縁層、３３Ｂ・・・第２の絶縁層、３３Ｃ・・・第３の
絶縁層、３３ｂ・・・孔部DESCRIPTION OF SYMBOLS 10 ... Base, 11 ... Lower insulating layer, 12 ... Lower wiring, 13, 23, 33 ... Interlayer insulating layer, 14, 3
4B: opening, 15, 25, 35: diffusion preventing layer, 16, 26, 36: first conductive layer, 17, 2
7, 37: second conductive layer, 18, 38B: via hole, 19: upper layer wiring, 24, 34A: groove, 28, 38A: groove wiring, 33A: first Insulating layer, 33B... Second insulating layer, 33C... Third insulating layer, 33b.

───────────────────────────────────────────────────── フロントページの続き (72)発明者 田口 充 東京都品川区北品川６丁目７番35号 ソニ ー株式会社内 (72)発明者 瀬川 雄司 東京都品川区北品川６丁目７番35号 ソニ ー株式会社内 (72)発明者 由尾 啓 東京都品川区北品川６丁目７番35号 ソニ ー株式会社内 Ｆターム(参考） 4M104 AA01 BB17 BB30 BB32 BB36 DD16 DD37 DD43 DD52 DD53 FF16 FF22 GG10 GG14 GG15 5F033 HH07 HH11 HH13 HH14 HH15 HH17 HH18 HH19 HH32 HH33 JJ01 JJ07 JJ11 JJ13 JJ14 JJ15 JJ17 JJ18 JJ19 JJ32 JJ33 KK11 KK18 KK21 KK33 MM02 MM05 MM08 MM13 NN06 NN07 PP09 PP15 PP16 PP27 PP28 PP33 QQ09 QQ11 QQ25 QQ28 QQ30 QQ48 RR04 RR06 SS04 SS15 SS22 WW02 XX02 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Mitsuru Taguchi 6-7-35 Kita-Shinagawa, Shinagawa-ku, Tokyo Inside Sony Corporation (72) Inventor Yuji Segawa 6-35, Kita-Shinagawa, Shinagawa-ku, Tokyo Inside Sony Corporation (72) Inventor Hiroshi Yuo 6-35 Kita Shinagawa, Shinagawa-ku, Tokyo Sony Corporation F-term (reference) 4M104 AA01 BB17 BB30 BB32 BB36 DD16 DD37 DD43 DD52 DD53 FF16 FF22 GG10 GG14 GG15 5F033 HH07 HH11 HH13 HH14 HH15 HH17 HH18 HH19 HH32 HH33 JJ01 JJ07 JJ11 JJ13 JJ14 JJ15 JJ17 JJ18 JJ19 JJ32 JJ33 KK11 KK18 SS18 KK03 MM02 MM05 Q28 Q15 Q15 PP15 WW02 XX02

Claims (11)

【特許請求の範囲】[Claims] 【請求項１】（Ａ）基体上に形成された層間絶縁層に、
基体の一部が底部に露出した凹部を設ける工程と、 （Ｂ）凹部内を含む層間絶縁層上に、無電解めっき法に
よって第１の導電層を形成する工程と、 （Ｃ）第１の導電層上に、電解めっき法によって第２の
導電層を形成し、以て、凹部を第２の導電層で埋め込む
工程、から成ることを特徴とする半導体装置の製造方
法。(A) an interlayer insulating layer formed on a substrate,
(B) forming a first conductive layer on the interlayer insulating layer including the inside of the concave portion by electroless plating, and (C) forming a first conductive layer on the interlayer insulating layer including the inside of the concave portion. Forming a second conductive layer on the conductive layer by electroplating, and filling the recess with the second conductive layer. 【請求項２】第１の導電層の厚さは、第１の導電層を構
成する原子の１原子層分の厚さ以上であることを特徴と
する請求項１に記載の半導体装置の製造方法。2. The semiconductor device according to claim 1, wherein the thickness of the first conductive layer is equal to or greater than the thickness of one atomic layer of the atoms constituting the first conductive layer. Method. 【請求項３】第１の導電層の厚さは１００ｎｍ以下であ
ることを特徴とする請求項２に記載の半導体装置の製造
方法。3. The method according to claim 2, wherein the thickness of the first conductive layer is 100 nm or less. 【請求項４】第１の導電層の厚さは５ｎｍ以上１００ｎ
ｍ以下であることを特徴とする請求項３に記載の半導体
装置の製造方法。4. The thickness of the first conductive layer is 5 nm or more and 100 n.
4. The method for manufacturing a semiconductor device according to claim 3, wherein m is equal to or less than m. 【請求項５】第１の導電層の厚さは５ｎｍ以上５０ｎｍ
以下であることを特徴とする請求項４に記載の半導体装
置の製造方法。5. The thickness of the first conductive layer is 5 nm or more and 50 nm.
The method for manufacturing a semiconductor device according to claim 4, wherein: 【請求項６】第１の導電層及び第２の導電層は、同一の
材料から構成されていることを特徴とする請求項１に記
載の半導体装置の製造方法。6. The method according to claim 1, wherein the first conductive layer and the second conductive layer are made of the same material. 【請求項７】第１の導電層及び第２の導電層は、異なる
材料から構成されていることを特徴とする請求項１に記
載の半導体装置の製造方法。7. The method according to claim 1, wherein the first conductive layer and the second conductive layer are made of different materials. 【請求項８】第１の導電層は、Ｃｕ、Ｎｉ、Ｎｉ系合
金、Ｐｔ、Ｔｉ、Ｃｒ、Ｃｏ、Ｃｏ系合金、Ｐｄ、Ａ
ｇ、Ａｕ、Ｚｎ、Ｓｎ、Ｒｈ、ＴｉＮ／Ｔｉ、ＴｉＮ／
Ｒｈ及びＴｉＮ／Ｐｔから成る群から選択された材料か
ら構成されていることを特徴とする請求項１に記載の半
導体装置の製造方法。8. The first conductive layer is made of Cu, Ni, Ni-based alloy, Pt, Ti, Cr, Co, Co-based alloy, Pd, A
g, Au, Zn, Sn, Rh, TiN / Ti, TiN /
2. The method according to claim 1, wherein the semiconductor device is made of a material selected from the group consisting of Rh and TiN / Pt. 【請求項９】第２の導電層は、Ｃｕ、Ａｇ及びＰｔから
成る群から選択された材料から構成されていることを特
徴とする請求項１に記載の半導体装置の製造方法。9. The method according to claim 1, wherein the second conductive layer is made of a material selected from the group consisting of Cu, Ag, and Pt. 【請求項１０】第１の導電層を形成する前に、第１の導
電層及び／又は第２の導電層を構成する原子が層間絶縁
層中に拡散することを防止するための拡散防止層を凹部
内を含む層間絶縁層上に形成する工程を更に含むことを
特徴とする請求項１に記載の半導体装置の製造方法。10. A diffusion preventing layer for preventing atoms constituting a first conductive layer and / or a second conductive layer from diffusing into an interlayer insulating layer before forming the first conductive layer. 2. The method according to claim 1, further comprising the step of: forming on the interlayer insulating layer including the inside of the concave portion. 【請求項１１】拡散防止層は、ＴｉＮ、ＴｉＮ／Ｔｉ、
Ｔａ、ＴａＮ、ＴａＮ／Ｔａ及びＴａ／ＴａＮ／Ｔａか
ら成る群から選択された材料から構成されていることを
特徴とする請求項１０に記載の半導体装置の製造方法。11. The anti-diffusion layer comprises TiN, TiN / Ti,
11. The method according to claim 10, wherein the semiconductor device is made of a material selected from the group consisting of Ta, TaN, TaN / Ta, and Ta / TaN / Ta.
JP11053644A 1998-03-30 1999-03-02 Manufacture of semiconductor device Pending JP2000294518A (en)

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Publication number Priority date Publication date Assignee Title
JP2007165881A (en) * 2005-12-09 2007-06-28 Dongbu Electronics Co Ltd Method for manufacturing semiconductor device
JP2007251164A (en) * 2006-03-15 2007-09-27 Internatl Business Mach Corp <Ibm> Interconnect structure, semiconductor structure and method of forming interconnect structure (formation of oxidation-resistant seed layer for interconnect usage)
JP2008199059A (en) * 2008-05-01 2008-08-28 Sony Corp Solid-state image pickup device and manufacturing method therefor
US9048295B2 (en) 2012-10-30 2015-06-02 Mitsubishi Electric Corporation Method of manufacturing semiconductor device

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