IT8820357A0 - Procedimento per la formazione di un circuito integrato su un substrato di tipo n, comprendente transistori pnp e npn verticali e isolati fra loro. - Google Patents

Procedimento per la formazione di un circuito integrato su un substrato di tipo n, comprendente transistori pnp e npn verticali e isolati fra loro.

Info

Publication number
IT8820357A0
IT8820357A0 IT8820357A IT2035788A IT8820357A0 IT 8820357 A0 IT8820357 A0 IT 8820357A0 IT 8820357 A IT8820357 A IT 8820357A IT 2035788 A IT2035788 A IT 2035788A IT 8820357 A0 IT8820357 A0 IT 8820357A0
Authority
IT
Italy
Prior art keywords
procedure
formation
integrated circuit
type substrate
npn transistors
Prior art date
Application number
IT8820357A
Other languages
English (en)
Other versions
IT1218230B (it
Inventor
Raffaele Zambrano
Salvatore Musumeci
Original Assignee
Sgs Thomson Microelectronics
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sgs Thomson Microelectronics filed Critical Sgs Thomson Microelectronics
Priority to IT20357/88A priority Critical patent/IT1218230B/it
Publication of IT8820357A0 publication Critical patent/IT8820357A0/it
Priority to US07/341,540 priority patent/US4898836A/en
Priority to EP89201041A priority patent/EP0339732B1/en
Priority to DE89201041T priority patent/DE68910169T2/de
Priority to JP1106088A priority patent/JP2703798B2/ja
Application granted granted Critical
Publication of IT1218230B publication Critical patent/IT1218230B/it

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8222Bipolar technology
    • H01L21/8228Complementary devices, e.g. complementary transistors
    • H01L21/82285Complementary vertical transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/761PN junctions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/082Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only
    • H01L27/0823Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only including vertical bipolar transistors only
    • H01L27/0826Combination of vertical complementary transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Bipolar Integrated Circuits (AREA)
  • Bipolar Transistors (AREA)
IT20357/88A 1988-04-28 1988-04-28 Procedimento per la formazione di un circuito integrato su un substrato di tipo n,comprendente transistori pnp e npn verticali e isolati fra loro IT1218230B (it)

Priority Applications (5)

Application Number Priority Date Filing Date Title
IT20357/88A IT1218230B (it) 1988-04-28 1988-04-28 Procedimento per la formazione di un circuito integrato su un substrato di tipo n,comprendente transistori pnp e npn verticali e isolati fra loro
US07/341,540 US4898836A (en) 1988-04-28 1989-04-21 Process for forming an integrated circuit on an N type substrate comprising PNP and NPN transistors placed vertically and insulated one from another
EP89201041A EP0339732B1 (en) 1988-04-28 1989-04-24 Process for forming an integrated circuit on an N type substrate comprising PNP and NPN transistors placed vertically and insulated one from another
DE89201041T DE68910169T2 (de) 1988-04-28 1989-04-24 Verfahren zur Herstellung einer auf einem N-Typ-Substrat integrierten Schaltung, umfassend vertikale PNP- und NPN-Transistoren, die voneinander isoliert sind.
JP1106088A JP2703798B2 (ja) 1988-04-28 1989-04-27 N形半導体材料の基板上に互に絶縁され且つ垂直方向の電流の流れを有するpnpおよびnpnトランジスタを有する集積回路を形成する方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT20357/88A IT1218230B (it) 1988-04-28 1988-04-28 Procedimento per la formazione di un circuito integrato su un substrato di tipo n,comprendente transistori pnp e npn verticali e isolati fra loro

Publications (2)

Publication Number Publication Date
IT8820357A0 true IT8820357A0 (it) 1988-04-28
IT1218230B IT1218230B (it) 1990-04-12

Family

ID=11166004

Family Applications (1)

Application Number Title Priority Date Filing Date
IT20357/88A IT1218230B (it) 1988-04-28 1988-04-28 Procedimento per la formazione di un circuito integrato su un substrato di tipo n,comprendente transistori pnp e npn verticali e isolati fra loro

Country Status (5)

Country Link
US (1) US4898836A (it)
EP (1) EP0339732B1 (it)
JP (1) JP2703798B2 (it)
DE (1) DE68910169T2 (it)
IT (1) IT1218230B (it)

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* Cited by examiner, † Cited by third party
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US5529939A (en) * 1986-09-26 1996-06-25 Analog Devices, Incorporated Method of making an integrated circuit with complementary isolated bipolar transistors
IT1215024B (it) * 1986-10-01 1990-01-31 Sgs Microelettronica Spa Processo per la formazione di un dispositivo monolitico a semiconduttore di alta tensione
IT1217323B (it) * 1987-12-22 1990-03-22 Sgs Microelettronica Spa Struttura integrata di transistor bipolare di potenza di alta tensione e di transistor mos di potenza di bassa tensione nella configurazione"emitter switching"e relativo processo di fabbricazione
USRE35642E (en) * 1987-12-22 1997-10-28 Sgs-Thomson Microelectronics, S.R.L. Integrated high-voltage bipolar power transistor and low voltage MOS power transistor structure in the emitter switching configuration and relative manufacturing process
US5156989A (en) * 1988-11-08 1992-10-20 Siliconix, Incorporated Complementary, isolated DMOS IC technology
US5286986A (en) * 1989-04-13 1994-02-15 Kabushiki Kaisha Toshiba Semiconductor device having CCD and its peripheral bipolar transistors
JPH07105458B2 (ja) * 1989-11-21 1995-11-13 株式会社東芝 複合型集積回路素子
EP0439899A3 (en) * 1990-01-25 1991-11-06 Precision Monolithics Inc. Complementary bipolar transistors compatible with cmos process
GB2248142A (en) * 1990-09-19 1992-03-25 Koninkl Philips Electronics Nv A method of manufacturing a semiconductor device
JP2748988B2 (ja) * 1991-03-13 1998-05-13 三菱電機株式会社 半導体装置とその製造方法
US5597742A (en) * 1991-04-17 1997-01-28 Consorzio Per La Ricerca Sulla Microelettronica Nel Mezzogiorno Semiconductor device and method
DE69125390T2 (de) * 1991-07-03 1997-08-28 Cons Ric Microelettronica Laterale Bipolartransistorstruktur mit integriertem Kontrollschaltkreis und integriertem Leistungstransistor und deren Herstellungsprozess
US5702959A (en) * 1995-05-31 1997-12-30 Texas Instruments Incorporated Method for making an isolated vertical transistor
EP0756329B1 (en) 1995-07-27 2002-01-16 Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno - CoRiMMe Vertical PNP transistor and relative fabrication method
JP3409548B2 (ja) * 1995-12-12 2003-05-26 ソニー株式会社 半導体装置の製造方法
EP0809294B1 (en) * 1996-05-21 2002-01-02 Co.Ri.M.Me. Consorzio Per La Ricerca Sulla Microelettronica Nel Mezzogiorno Power semiconductor device structure with vertical PNP transistor
JP3529549B2 (ja) 1996-05-23 2004-05-24 東芝マイクロエレクトロニクス株式会社 半導体装置の製造方法
JPH104142A (ja) * 1996-06-18 1998-01-06 Sony Corp 半導体装置の製造方法
EP0915508A1 (en) * 1997-10-10 1999-05-12 STMicroelectronics S.r.l. Integrated circuit with highly efficient junction insulation
US6815801B2 (en) * 2003-02-28 2004-11-09 Texas Instrument Incorporated Vertical bipolar transistor and a method of manufacture therefor including two epitaxial layers and a buried layer

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3079287A (en) * 1959-09-01 1963-02-26 Texas Instruments Inc Improved grown junction transistor and method of making same
NL145396B (nl) * 1966-10-21 1975-03-17 Philips Nv Werkwijze ter vervaardiging van een geintegreerde halfgeleiderinrichting en geintegreerde halfgeleiderinrichting, vervaardigd volgens de werkwijze.
US3930909A (en) * 1966-10-21 1976-01-06 U.S. Philips Corporation Method of manufacturing a semiconductor device utilizing simultaneous outdiffusion during epitaxial growth
US3474308A (en) * 1966-12-13 1969-10-21 Texas Instruments Inc Monolithic circuits having matched complementary transistors,sub-epitaxial and surface resistors,and n and p channel field effect transistors
NL7009090A (it) * 1970-06-20 1971-12-22
US4054899A (en) * 1970-09-03 1977-10-18 Texas Instruments Incorporated Process for fabricating monolithic circuits having matched complementary transistors and product
US3793088A (en) * 1972-11-15 1974-02-19 Bell Telephone Labor Inc Compatible pnp and npn devices in an integrated circuit
US4038680A (en) * 1972-12-29 1977-07-26 Sony Corporation Semiconductor integrated circuit device
DE2351985A1 (de) * 1973-10-17 1975-04-30 Itt Ind Gmbh Deutsche Planardiffusionsverfahren zum herstellen einer monolithisch integrierten festkoerperschaltung
US3971059A (en) * 1974-09-23 1976-07-20 National Semiconductor Corporation Complementary bipolar transistors having collector diffused isolation
JPS54136281A (en) * 1978-04-14 1979-10-23 Toko Inc Semiconductor device and method of fabricating same
EP0093304B1 (en) * 1982-04-19 1986-01-15 Matsushita Electric Industrial Co., Ltd. Semiconductor ic and method of making the same
JPS59194465A (ja) * 1983-04-19 1984-11-05 Sanken Electric Co Ltd 半導体集積回路の製造方法

Also Published As

Publication number Publication date
EP0339732A1 (en) 1989-11-02
DE68910169T2 (de) 1994-04-07
US4898836A (en) 1990-02-06
JPH0212926A (ja) 1990-01-17
IT1218230B (it) 1990-04-12
JP2703798B2 (ja) 1998-01-26
EP0339732B1 (en) 1993-10-27
DE68910169D1 (de) 1993-12-02

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TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19970429