DE3382727D1 - Integrierte Halbleiterschaltungsanordnung. - Google Patents

Integrierte Halbleiterschaltungsanordnung.

Info

Publication number
DE3382727D1
DE3382727D1 DE89202020T DE3382727T DE3382727D1 DE 3382727 D1 DE3382727 D1 DE 3382727D1 DE 89202020 T DE89202020 T DE 89202020T DE 3382727 T DE3382727 T DE 3382727T DE 3382727 D1 DE3382727 D1 DE 3382727D1
Authority
DE
Germany
Prior art keywords
circuit arrangement
semiconductor circuit
integrated semiconductor
integrated
arrangement
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE89202020T
Other languages
English (en)
Inventor
Eiji Sugiyama
Toshiharu C O Fujitsu Li Saito
Mitsuaki Natsume
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP57112778A external-priority patent/JPS594065A/ja
Priority claimed from JP11424182A external-priority patent/JPS595657A/ja
Priority claimed from JP57230288A external-priority patent/JPS59124151A/ja
Priority claimed from JP57233774A external-priority patent/JP2568165B2/ja
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of DE3382727D1 publication Critical patent/DE3382727D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17736—Structural details of routing resources
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits
    • H01L27/11801—Masterslice integrated circuits using bipolar technology
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00307—Modifications for increasing the reliability for protection in bipolar transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/082—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using bipolar transistors
    • H03K19/086—Emitter coupled logic
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/1778—Structural details for adapting physical parameters
    • H03K19/17784—Structural details for adapting physical parameters for supply voltage
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/1778—Structural details for adapting physical parameters
    • H03K19/17796—Structural details for adapting physical parameters for physical disposition of blocks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Bipolar Integrated Circuits (AREA)
  • Logic Circuits (AREA)
DE89202020T 1982-06-30 1983-06-30 Integrierte Halbleiterschaltungsanordnung. Expired - Lifetime DE3382727D1 (de)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP57112778A JPS594065A (ja) 1982-06-30 1982-06-30 集積回路
JP11424182A JPS595657A (ja) 1982-07-01 1982-07-01 マスタ−スライス方式の半導体集積回路
JP57230288A JPS59124151A (ja) 1982-12-29 1982-12-29 半導体集積回路装置
JP57233774A JP2568165B2 (ja) 1982-12-29 1982-12-29 半導体装置

Publications (1)

Publication Number Publication Date
DE3382727D1 true DE3382727D1 (de) 1994-01-27

Family

ID=27470026

Family Applications (3)

Application Number Title Priority Date Filing Date
DE8383303805T Expired - Fee Related DE3381460D1 (de) 1982-06-30 1983-06-30 Integrierte halbleiterschaltungsanordnung.
DE89202020T Expired - Lifetime DE3382727D1 (de) 1982-06-30 1983-06-30 Integrierte Halbleiterschaltungsanordnung.
DE89202021T Expired - Lifetime DE3382726D1 (de) 1982-06-30 1983-06-30 Integrierte Halbleiterschaltungsanordnung.

Family Applications Before (1)

Application Number Title Priority Date Filing Date
DE8383303805T Expired - Fee Related DE3381460D1 (de) 1982-06-30 1983-06-30 Integrierte halbleiterschaltungsanordnung.

Family Applications After (1)

Application Number Title Priority Date Filing Date
DE89202021T Expired - Lifetime DE3382726D1 (de) 1982-06-30 1983-06-30 Integrierte Halbleiterschaltungsanordnung.

Country Status (3)

Country Link
US (3) US4904887A (de)
EP (3) EP0344873B1 (de)
DE (3) DE3381460D1 (de)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6065557A (ja) * 1983-09-21 1985-04-15 Fujitsu Ltd 集積回路装置
JP2509696B2 (ja) * 1989-04-26 1996-06-26 株式会社東芝 ゲ―トアレ―半導体集積回路装置
JPH0364735A (ja) * 1989-08-03 1991-03-20 Sharp Corp アクティブマトリクス表示装置
US4990797A (en) * 1989-09-26 1991-02-05 Analog Devices, Inc. Reference voltage distribution system
EP0454998B1 (de) * 1990-03-28 1995-11-08 Nec Corporation Halbleiterspeichereinrichtung
JP2683948B2 (ja) * 1990-06-19 1997-12-03 三菱電機株式会社 半導体集積回路
US5206778A (en) * 1991-05-16 1993-04-27 International Business Machines Corporation Sense circuit for on-chip thermal shutdown
US5359211A (en) * 1991-07-18 1994-10-25 Harris Corporation High voltage protection using SCRs
US5341018A (en) * 1991-09-18 1994-08-23 Nec Corporation Semiconductor integrated circuit device having a plurality of input circuits each including differently sized transistors
US5663860A (en) * 1996-06-28 1997-09-02 Harris Corporation High voltage protection circuits
US7602039B2 (en) 2002-08-29 2009-10-13 Micron Technology, Inc. Programmable capacitor associated with an input/output pad
ITMI20030202A1 (it) * 2003-02-06 2004-08-07 Cuna Laura Della Detergenti e coadiuvanti del lavaggio ad alto effetto antiodorante sui capi in uso per effetto del lavaggio
JP5051105B2 (ja) * 2008-11-21 2012-10-17 三菱電機株式会社 リファレンス電圧発生回路及びバイアス回路

Family Cites Families (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3404285A (en) * 1965-05-03 1968-10-01 Control Data Corp Bias supply and line termination system for differential logic
US3570115A (en) * 1968-05-06 1971-03-16 Honeywell Inc Method for mounting electronic chips
US3558992A (en) * 1968-06-17 1971-01-26 Rca Corp Integrated circuit having bonding pads over unused active area components
GB1221914A (en) * 1969-06-13 1971-02-10 Standard Telephones Cables Ltd Manufacture of integrated circuits
US3793064A (en) * 1971-11-15 1974-02-19 Du Pont Product and process for cavity metallization of semiconductor packages
US3942245A (en) * 1971-11-20 1976-03-09 Ferranti Limited Related to the manufacture of lead frames and the mounting of semiconductor devices thereon
US3872583A (en) * 1972-07-10 1975-03-25 Amdahl Corp LSI chip package and method
US3808475A (en) * 1972-07-10 1974-04-30 Amdahl Corp Lsi chip construction and method
JPS5435474B2 (de) * 1973-03-26 1979-11-02
US3981070A (en) * 1973-04-05 1976-09-21 Amdahl Corporation LSI chip construction and method
US3866066A (en) * 1973-07-16 1975-02-11 Bell Telephone Labor Inc Power supply distribution for integrated circuits
JPS60953B2 (ja) * 1977-12-30 1985-01-11 富士通株式会社 半導体集積回路装置
JPS54107267A (en) * 1978-02-10 1979-08-22 Nec Corp Vessel for semiconductor integrated circuit unit
US4278897A (en) * 1978-12-28 1981-07-14 Fujitsu Limited Large scale semiconductor integrated circuit device
US4518874A (en) * 1979-03-21 1985-05-21 International Business Machines Corporation Cascoded PLA array
JPS5631730U (de) * 1979-07-19 1981-03-27
JPS577151A (en) * 1980-06-17 1982-01-14 Nec Corp Monolithic ic circuit
JPS5710946A (en) * 1980-06-25 1982-01-20 Nec Corp Integrated circuit
JPS57207356A (en) * 1981-06-15 1982-12-20 Fujitsu Ltd Semiconductor device
IT1211141B (it) * 1981-12-04 1989-09-29 Ates Componenti Elettron Circuito limitatore-trasduttore disegnali in alternata codificati in forma binaria, come stadio d'ingresso di un circuito integrato a igfet.
JPS57202774A (en) * 1982-03-29 1982-12-11 Nec Corp Semiconductor device
DE3215518C1 (de) * 1982-04-26 1983-08-11 Siemens AG, 1000 Berlin und 8000 München Verknuepfungsglied mit einem Emitterfolger als Eingangsschaltung
US4649415A (en) * 1985-01-15 1987-03-10 National Semiconductor Corporation Semiconductor package with tape mounted die
US4763184A (en) * 1985-04-30 1988-08-09 Waferscale Integration, Inc. Input circuit for protecting against damage caused by electrostatic discharge
US4689504A (en) * 1985-12-20 1987-08-25 Motorola, Inc. High voltage decoder
JPH0821632B2 (ja) * 1987-01-10 1996-03-04 三菱電機株式会社 半導体集積回路
US4791521A (en) * 1987-04-07 1988-12-13 Western Digital Corporation Method and apparatus for reducing transient noise by premagnetization of parasitic inductance

Also Published As

Publication number Publication date
EP0348017A2 (de) 1989-12-27
US4891729A (en) 1990-01-02
US4904887A (en) 1990-02-27
EP0344873B1 (de) 1993-12-15
US4952997A (en) 1990-08-28
EP0344873A2 (de) 1989-12-06
EP0098173A2 (de) 1984-01-11
DE3382726D1 (de) 1994-01-27
DE3381460D1 (de) 1990-05-17
EP0344873A3 (en) 1990-12-05
EP0098173B1 (de) 1990-04-11
EP0348017A3 (en) 1990-11-28
EP0348017B1 (de) 1993-12-15
EP0098173A3 (en) 1986-04-16

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Legal Events

Date Code Title Description
8332 No legal effect for de