IT1275668B1 - Circuito di ridondanza di riga e procedimento per un dispositivo di memoria a semiconduttore con un decodificatore doppio di riga - Google Patents

Circuito di ridondanza di riga e procedimento per un dispositivo di memoria a semiconduttore con un decodificatore doppio di riga

Info

Publication number
IT1275668B1
IT1275668B1 IT94MI002333A ITMI942333A IT1275668B1 IT 1275668 B1 IT1275668 B1 IT 1275668B1 IT 94MI002333 A IT94MI002333 A IT 94MI002333A IT MI942333 A ITMI942333 A IT MI942333A IT 1275668 B1 IT1275668 B1 IT 1275668B1
Authority
IT
Italy
Prior art keywords
procedure
memory device
semiconductor memory
redundancy circuit
line
Prior art date
Application number
IT94MI002333A
Other languages
English (en)
Inventor
Seung-Cheol Oh
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of ITMI942333A0 publication Critical patent/ITMI942333A0/it
Publication of ITMI942333A1 publication Critical patent/ITMI942333A1/it
Application granted granted Critical
Publication of IT1275668B1 publication Critical patent/IT1275668B1/it

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/702—Masking faults in memories by using spares or by reconfiguring by replacing auxiliary circuits, e.g. spare voltage generators, decoders or sense amplifiers, to be used instead of defective ones
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
    • G11C29/808—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout using a flexible replacement scheme
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/24—Accessing extra cells, e.g. dummy cells or redundant cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/785—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes
    • G11C29/787—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes using a fuse hierarchy
IT94MI002333A 1993-11-18 1994-11-17 Circuito di ridondanza di riga e procedimento per un dispositivo di memoria a semiconduttore con un decodificatore doppio di riga IT1275668B1 (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR93024667A KR960008825B1 (en) 1993-11-18 1993-11-18 Row redundancy circuit and method of semiconductor memory device with double row decoder

Publications (3)

Publication Number Publication Date
ITMI942333A0 ITMI942333A0 (it) 1994-11-17
ITMI942333A1 ITMI942333A1 (it) 1996-05-17
IT1275668B1 true IT1275668B1 (it) 1997-10-17

Family

ID=19368451

Family Applications (1)

Application Number Title Priority Date Filing Date
IT94MI002333A IT1275668B1 (it) 1993-11-18 1994-11-17 Circuito di ridondanza di riga e procedimento per un dispositivo di memoria a semiconduttore con un decodificatore doppio di riga

Country Status (7)

Country Link
US (1) US5461587A (it)
JP (1) JPH07192491A (it)
KR (1) KR960008825B1 (it)
CN (1) CN1045345C (it)
DE (1) DE4441183C2 (it)
FR (1) FR2712721B1 (it)
IT (1) IT1275668B1 (it)

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JPH0877776A (ja) * 1994-09-06 1996-03-22 Mitsubishi Electric Corp 半導体記憶装置
DE19507312C1 (de) * 1995-03-02 1996-07-25 Siemens Ag Halbleiterspeicher, dessen Speicherzellen zu einzeln adressierbaren Einheiten zusammengefaßt sind und Verfahren zum Betrieb solcher Speicher
JPH09180495A (ja) * 1995-12-27 1997-07-11 Nec Corp 半導体記憶装置
KR0179550B1 (ko) * 1995-12-29 1999-04-15 김주용 반도체 메모리 장치의 리던던시 회로
US5781483A (en) * 1996-12-31 1998-07-14 Micron Technology, Inc. Device and method for repairing a memory array by storing each bit in multiple memory cells in the array
US5831914A (en) * 1997-03-31 1998-11-03 International Business Machines Corporation Variable size redundancy replacement architecture to make a memory fault-tolerant
US5978931A (en) * 1997-07-16 1999-11-02 International Business Machines Corporation Variable domain redundancy replacement configuration for a memory device
US5881003A (en) * 1997-07-16 1999-03-09 International Business Machines Corporation Method of making a memory device fault tolerant using a variable domain redundancy replacement configuration
US5970000A (en) * 1998-02-02 1999-10-19 International Business Machines Corporation Repairable semiconductor integrated circuit memory by selective assignment of groups of redundancy elements to domains
US6072735A (en) * 1998-06-22 2000-06-06 Lucent Technologies, Inc. Built-in redundancy architecture for computer memories
US6407944B1 (en) 1998-12-29 2002-06-18 Samsung Electronics Co., Ltd. Method for protecting an over-erasure of redundant memory cells during test for high-density nonvolatile memory semiconductor devices
KR100375599B1 (ko) * 1999-06-30 2003-03-15 주식회사 하이닉스반도체 로오 리던던시 회로
JP2001101892A (ja) 1999-09-30 2001-04-13 Mitsubishi Electric Corp 半導体記憶装置
KR100586068B1 (ko) * 1999-12-20 2006-06-07 매그나칩 반도체 유한회사 메모리장치의 리페어 회로
KR100498610B1 (ko) * 1999-12-22 2005-07-01 주식회사 하이닉스반도체 뱅크 구분없이 휴즈 박스를 사용하는 로우 리던던시 회로
KR20030028827A (ko) * 2000-08-31 2003-04-10 닛뽄덴끼 가부시끼가이샤 반도체 기억장치 및 그 리프레싱 방법
US6549476B2 (en) 2001-04-09 2003-04-15 Micron Technology, Inc. Device and method for using complementary bits in a memory array
US6442099B1 (en) * 2001-04-18 2002-08-27 Sun Microsystems, Inc. Low power read scheme for memory array structures
KR100481857B1 (ko) 2002-08-14 2005-04-11 삼성전자주식회사 레이아웃 면적을 줄이고 뱅크 마다 독립적인 동작을수행할 수 있는 디코더를 갖는 플레쉬 메모리 장치
JP3884374B2 (ja) * 2002-12-06 2007-02-21 株式会社東芝 半導体装置
US7509543B2 (en) * 2003-06-17 2009-03-24 Micron Technology, Inc. Circuit and method for error test, recordation, and repair
KR101165027B1 (ko) * 2004-06-30 2012-07-13 삼성전자주식회사 반도체 메모리 장치에서의 리던던시 프로그램 회로
US7110319B2 (en) * 2004-08-27 2006-09-19 Micron Technology, Inc. Memory devices having reduced coupling noise between wordlines
KR20170055222A (ko) 2015-11-11 2017-05-19 삼성전자주식회사 리페어 단위 변경 기능을 가지는 메모리 장치 및 메모리 시스템
US11557369B2 (en) * 2021-04-02 2023-01-17 Micron Technology, Inc. Systems and methods to reduce the impact of short bits in phase change memory arrays
CN113178216B (zh) * 2021-05-28 2022-05-20 长鑫存储技术有限公司 半导体存储装置

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4837747A (en) * 1986-11-29 1989-06-06 Mitsubishi Denki Kabushiki Kaisha Redundary circuit with a spare main decoder responsive to an address of a defective cell in a selected cell block
JPH01184796A (ja) * 1988-01-19 1989-07-24 Nec Corp 半導体メモリ装置
EP0333207B1 (en) * 1988-03-18 1997-06-11 Kabushiki Kaisha Toshiba Mask rom with spare memory cells
JP2547615B2 (ja) * 1988-06-16 1996-10-23 三菱電機株式会社 読出専用半導体記憶装置および半導体記憶装置
JP2632089B2 (ja) * 1990-06-07 1997-07-16 三菱電機株式会社 半導体回路装置
JPH04255998A (ja) * 1991-02-08 1992-09-10 Nec Ic Microcomput Syst Ltd 半導体記憶装置
JP2501993B2 (ja) * 1992-02-24 1996-05-29 株式会社東芝 半導体記憶装置
KR950004623B1 (ko) * 1992-12-07 1995-05-03 삼성전자주식회사 리던던시 효율이 향상되는 반도체 메모리 장치
US5377146A (en) * 1993-07-23 1994-12-27 Alliance Semiconductor Corporation Hierarchical redundancy scheme for high density monolithic memories

Also Published As

Publication number Publication date
ITMI942333A1 (it) 1996-05-17
ITMI942333A0 (it) 1994-11-17
DE4441183A1 (de) 1995-05-24
DE4441183C2 (de) 2000-01-05
FR2712721B1 (fr) 1997-06-20
CN1045345C (zh) 1999-09-29
FR2712721A1 (fr) 1995-05-24
US5461587A (en) 1995-10-24
KR950015398A (ko) 1995-06-16
JPH07192491A (ja) 1995-07-28
KR960008825B1 (en) 1996-07-05
CN1115104A (zh) 1996-01-17

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Legal Events

Date Code Title Description
0001 Granted
TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19971126