IT1109432B - Perfezionamento nelle celle di memoria per memorie ad accesso casuale - Google Patents

Perfezionamento nelle celle di memoria per memorie ad accesso casuale

Info

Publication number
IT1109432B
IT1109432B IT50565/78A IT5056578A IT1109432B IT 1109432 B IT1109432 B IT 1109432B IT 50565/78 A IT50565/78 A IT 50565/78A IT 5056578 A IT5056578 A IT 5056578A IT 1109432 B IT1109432 B IT 1109432B
Authority
IT
Italy
Prior art keywords
improvement
random access
memory cells
access memories
memories
Prior art date
Application number
IT50565/78A
Other languages
English (en)
Other versions
IT7850565A0 (it
Inventor
Wilson Hewlett Frank
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Publication of IT7850565A0 publication Critical patent/IT7850565A0/it
Application granted granted Critical
Publication of IT1109432B publication Critical patent/IT1109432B/it

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/411Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using bipolar transistors only
    • G11C11/4113Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using bipolar transistors only with at least one cell access to base or collector of at least one of said transistors, e.g. via access diodes, access transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203Particular design considerations for integrated circuits
    • H01L27/0214Particular design considerations for integrated circuits for internal polarisation, e.g. I2L
    • H01L27/0229Particular design considerations for integrated circuits for internal polarisation, e.g. I2L of bipolar structures
    • H01L27/0233Integrated injection logic structures [I2L]
    • H01L27/0237Integrated injection logic structures [I2L] using vertical injector structures
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B99/00Subject matter not provided for in other groups of this subclass

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Memories (AREA)
  • Static Random-Access Memory (AREA)
  • Bipolar Transistors (AREA)
IT50565/78A 1977-08-02 1978-08-01 Perfezionamento nelle celle di memoria per memorie ad accesso casuale IT1109432B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/821,068 US4104732A (en) 1977-08-02 1977-08-02 Static RAM cell

Publications (2)

Publication Number Publication Date
IT7850565A0 IT7850565A0 (it) 1978-08-01
IT1109432B true IT1109432B (it) 1985-12-16

Family

ID=25232418

Family Applications (1)

Application Number Title Priority Date Filing Date
IT50565/78A IT1109432B (it) 1977-08-02 1978-08-01 Perfezionamento nelle celle di memoria per memorie ad accesso casuale

Country Status (7)

Country Link
US (1) US4104732A (it)
JP (1) JPS5811106B2 (it)
DE (1) DE2833594A1 (it)
FR (1) FR2399711A1 (it)
GB (1) GB2001819B (it)
IT (1) IT1109432B (it)
NL (1) NL7808151A (it)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4274891A (en) * 1979-06-29 1981-06-23 International Business Machines Corporation Method of fabricating buried injector memory cell formed from vertical complementary bipolar transistor circuits utilizing mono-poly deposition
EP0028354A1 (en) * 1979-11-05 1981-05-13 Texas Instruments Incorporated Vertical Schottky logic
US4400712A (en) * 1981-02-13 1983-08-23 Bell Telephone Laboratories, Incorporated Static bipolar random access memory
US4543595A (en) * 1982-05-20 1985-09-24 Fairchild Camera And Instrument Corporation Bipolar memory cell
US4503521A (en) * 1982-06-25 1985-03-05 International Business Machines Corporation Non-volatile memory and switching device
JPS6048090A (ja) * 1983-08-26 1985-03-15 伊勢電子工業株式会社 螢光表示装置
TW335503B (en) 1996-02-23 1998-07-01 Semiconductor Energy Lab Kk Semiconductor thin film and manufacturing method and semiconductor device and its manufacturing method
US7528459B2 (en) * 2003-05-27 2009-05-05 Nxp B.V. Punch-through diode and method of processing the same

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3427598A (en) * 1965-12-09 1969-02-11 Fairchild Camera Instr Co Emitter gated memory cell
DE2418079B2 (de) * 1974-04-13 1977-12-01 Deutsche Itt Industries Gmbh, 7800 Freiburg Binaere frequenzteilerstufe
DE2442773C3 (de) * 1974-09-06 1978-12-14 Deutsche Itt Industries Gmbh, 7800 Freiburg Integrierte Master-Slave-Flipflopschaltung
DE2455125C2 (de) * 1974-11-21 1982-05-19 Deutsche Itt Industries Gmbh, 7800 Freiburg Frequenzteilerstufe

Also Published As

Publication number Publication date
JPS5811106B2 (ja) 1983-03-01
DE2833594A1 (de) 1979-02-15
FR2399711B1 (it) 1983-05-27
US4104732A (en) 1978-08-01
JPS5427383A (en) 1979-03-01
GB2001819B (en) 1982-02-10
FR2399711A1 (fr) 1979-03-02
GB2001819A (en) 1979-02-07
IT7850565A0 (it) 1978-08-01
NL7808151A (nl) 1979-02-06

Similar Documents

Publication Publication Date Title
IT1074790B (it) Perfezionamento nelle memorie mosfet ad accesso casuale
JPS5644190A (en) Nonvolatile random access memory unit
JPS5453929A (en) Random access semiconductor memory array
JPS5396737A (en) Random access memory
FR2381354B1 (fr) Capacite perfectionnee d'ecriture en anti-memoire
IT8319986A0 (it) Memoria ad accesso casuale mosdinamica.
DE3277748D1 (en) Nonvolatile random access memory cell
DE3170944D1 (de) Non-volatile dynamic random access memory cell
AU509811B2 (en) Random access junction field-effect floating-gate transistor memory
GB2128403B (en) Random access memory
IT8067197A0 (it) Dispositivo di memoria dinamica ad accesso casuale
GB2005914B (en) Nonvolatile punch through memory cell
GB1558205A (en) Random access memory
IT1109432B (it) Perfezionamento nelle celle di memoria per memorie ad accesso casuale
JPS5473530A (en) Superconductive random access memory
IT1166699B (it) Apparecchiatura per l'indirizzamento di memorie ad alta densita' di celle
GB2010037B (en) Memory cell
JPS5642215A (en) Durable memory cell
IT8049575A0 (it) Perfezionamento nei sistemi di memoria statici ad accesso casuale nonvolatili
JPS5426671A (en) Memory cell
IT1149263B (it) Memoria ad accesso multiplo
JPS5323529A (en) Twooport random access memory cell
IT1117553B (it) Circuito rivelatore particolarmente per memorie ad accesso casuale
GB2038085B (en) Random access memory cell with polysilicon bit line
DE2861220D1 (en) Bipolar dynamic memory cell

Legal Events

Date Code Title Description
TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19950713