HUT58931A - Method and system technic arrangement for implementing dynamic bus acces through universal bus to distributed dma cycles - Google Patents

Method and system technic arrangement for implementing dynamic bus acces through universal bus to distributed dma cycles

Info

Publication number
HUT58931A
HUT58931A HU913024A HU302491A HUT58931A HU T58931 A HUT58931 A HU T58931A HU 913024 A HU913024 A HU 913024A HU 302491 A HU302491 A HU 302491A HU T58931 A HUT58931 A HU T58931A
Authority
HU
Hungary
Prior art keywords
bus
acces
arrangement
implementing dynamic
dma cycles
Prior art date
Application number
HU913024A
Other languages
English (en)
Other versions
HU913024D0 (en
HU215867B (hu
Inventor
George Bohoslaw Marenin
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of HU913024D0 publication Critical patent/HU913024D0/hu
Publication of HUT58931A publication Critical patent/HUT58931A/hu
Publication of HU215867B publication Critical patent/HU215867B/hu

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G06F13/30—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal with priority control
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
HU913024A 1990-09-21 1991-09-20 Eljárás és elrendezés sínkiosztás optimalizálására HU215867B (hu)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US58634990A 1990-09-21 1990-09-21

Publications (3)

Publication Number Publication Date
HU913024D0 HU913024D0 (en) 1992-01-28
HUT58931A true HUT58931A (en) 1992-03-30
HU215867B HU215867B (hu) 1999-03-29

Family

ID=24345380

Family Applications (1)

Application Number Title Priority Date Filing Date
HU913024A HU215867B (hu) 1990-09-21 1991-09-20 Eljárás és elrendezés sínkiosztás optimalizálására

Country Status (18)

Country Link
US (1) US5195185A (hu)
EP (1) EP0476990B1 (hu)
JP (1) JPH0810445B2 (hu)
KR (1) KR950014505B1 (hu)
CN (1) CN1037553C (hu)
AU (1) AU639589B2 (hu)
BR (1) BR9103929A (hu)
CA (1) CA2050129C (hu)
CZ (1) CZ282214B6 (hu)
DE (1) DE69132344T2 (hu)
FI (1) FI914429A (hu)
HU (1) HU215867B (hu)
MX (1) MX173460B (hu)
NO (1) NO913707L (hu)
PL (1) PL167608B1 (hu)
PT (1) PT99006A (hu)
RU (1) RU2110838C1 (hu)
SG (1) SG42853A1 (hu)

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US5598542A (en) * 1994-08-08 1997-01-28 International Business Machines Corporation Method and apparatus for bus arbitration in a multiple bus information handling system using time slot assignment values
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CN111478840A (zh) * 2020-04-15 2020-07-31 联合华芯电子有限公司 用于总线***的双速率仲裁中继设备
CN113821470A (zh) * 2020-06-19 2021-12-21 平头哥(上海)半导体技术有限公司 总线设备、嵌入式***和片上***
RU2749911C1 (ru) * 2020-12-25 2021-06-21 Акционерное Общество "Крафтвэй Корпорэйшн Плс" Аппаратная реализация механизма использования одной памяти несколькими устройствами

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Also Published As

Publication number Publication date
CN1060166A (zh) 1992-04-08
PL291778A1 (en) 1992-06-01
AU639589B2 (en) 1993-07-29
NO913707L (no) 1992-03-23
FI914429A0 (fi) 1991-09-20
EP0476990B1 (en) 2000-08-02
CA2050129A1 (en) 1992-03-22
CA2050129C (en) 1996-05-14
US5195185A (en) 1993-03-16
HU913024D0 (en) 1992-01-28
KR920006858A (ko) 1992-04-28
PT99006A (pt) 1993-10-29
DE69132344T2 (de) 2001-02-15
RU2110838C1 (ru) 1998-05-10
KR950014505B1 (ko) 1995-12-02
PL167608B1 (pl) 1995-09-30
AU8261291A (en) 1992-03-26
NO913707D0 (no) 1991-09-20
MX173460B (es) 1994-03-04
EP0476990A3 (en) 1993-08-04
CS287491A3 (en) 1992-04-15
CZ282214B6 (cs) 1997-06-11
CN1037553C (zh) 1998-02-25
FI914429A (fi) 1992-03-22
SG42853A1 (en) 1997-10-17
JPH04246758A (ja) 1992-09-02
BR9103929A (pt) 1992-05-26
JPH0810445B2 (ja) 1996-01-31
HU215867B (hu) 1999-03-29
DE69132344D1 (de) 2000-09-07
EP0476990A2 (en) 1992-03-25

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