HK1160982A1 - Memory architecture with a current controller and reduced power requirements - Google Patents
Memory architecture with a current controller and reduced power requirementsInfo
- Publication number
- HK1160982A1 HK1160982A1 HK12101250.9A HK12101250A HK1160982A1 HK 1160982 A1 HK1160982 A1 HK 1160982A1 HK 12101250 A HK12101250 A HK 12101250A HK 1160982 A1 HK1160982 A1 HK 1160982A1
- Authority
- HK
- Hong Kong
- Prior art keywords
- current controller
- power requirements
- reduced power
- memory architecture
- architecture
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
- G11C11/404—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
- G11C11/405—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with three charge-transfer gates, e.g. MOS transistors, per cell
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4076—Timing circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4094—Bit-line management or control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4099—Dummy cell treatment; Reference voltage generators
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/565—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using capacitive charge storage elements
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
- G11C7/08—Control thereof
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Dram (AREA)
- Read Only Memory (AREA)
- Semiconductor Memories (AREA)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US15424109P | 2009-02-20 | 2009-02-20 | |
PCT/US2010/024332 WO2010096393A1 (en) | 2009-02-20 | 2010-02-16 | Memory architecture with a current controller and reduced power requirements |
US12/706,374 US8169812B2 (en) | 2009-02-20 | 2010-02-16 | Memory architecture with a current controller and reduced power requirements |
Publications (1)
Publication Number | Publication Date |
---|---|
HK1160982A1 true HK1160982A1 (en) | 2012-08-17 |
Family
ID=42634185
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
HK12101250.9A HK1160982A1 (en) | 2009-02-20 | 2012-02-08 | Memory architecture with a current controller and reduced power requirements |
Country Status (11)
Country | Link |
---|---|
US (1) | US8169812B2 (ja) |
EP (2) | EP2631914A1 (ja) |
JP (2) | JP5242814B2 (ja) |
KR (1) | KR101197379B1 (ja) |
CN (2) | CN102318008B (ja) |
AU (1) | AU2010216223B2 (ja) |
CA (1) | CA2749971C (ja) |
HK (1) | HK1160982A1 (ja) |
MY (1) | MY149776A (ja) |
SG (1) | SG173684A1 (ja) |
WO (1) | WO2010096393A1 (ja) |
Families Citing this family (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8477550B2 (en) * | 2010-05-05 | 2013-07-02 | Stmicroelectronics International N.V. | Pass-gated bump sense amplifier for embedded drams |
US8576649B1 (en) * | 2010-07-02 | 2013-11-05 | Farid Nemati | Sense amplifiers and operations thereof |
CN102157193B (zh) * | 2011-03-28 | 2013-04-17 | 钰创科技股份有限公司 | 存储器的电压调整器 |
JP6013682B2 (ja) * | 2011-05-20 | 2016-10-25 | 株式会社半導体エネルギー研究所 | 半導体装置の駆動方法 |
US8624632B2 (en) | 2012-03-29 | 2014-01-07 | International Business Machines Corporation | Sense amplifier-type latch circuits with static bias current for enhanced operating frequency |
KR101939234B1 (ko) * | 2012-07-23 | 2019-01-16 | 삼성전자 주식회사 | 메모리 장치, 메모리 시스템 및 상기 메모리 장치의 독출 전압의 제어 방법 |
US9704572B2 (en) * | 2015-03-20 | 2017-07-11 | Sandisk Technologies Llc | Sense amplifier with integrating capacitor and methods of operation |
US10096348B2 (en) | 2015-05-15 | 2018-10-09 | Purdue Research Foundation | Memory array with reduced read power requirements and increased capacity |
US9449969B1 (en) * | 2015-06-03 | 2016-09-20 | Futurewei Technologies, Inc. | Device and method for a high isolation switch |
US9543004B1 (en) * | 2015-06-17 | 2017-01-10 | Intel Corporation | Provision of holding current in non-volatile random access memory |
US10250139B2 (en) * | 2016-03-31 | 2019-04-02 | Micron Technology, Inc. | Apparatuses and methods for a load current control circuit for a source follower voltage regulator |
TWI694729B (zh) * | 2018-06-19 | 2020-05-21 | 瑞昱半導體股份有限公司 | 開關電路 |
CN110797062B (zh) * | 2019-09-17 | 2021-07-06 | 华中科技大学 | 忆阻器的读写电路及读写方法 |
KR20210105187A (ko) | 2020-02-18 | 2021-08-26 | 에스케이하이닉스 주식회사 | 전압 생성 회로 및 이를 이용하는 비휘발성 메모리 장치 |
US11074956B1 (en) * | 2020-03-02 | 2021-07-27 | Micron Technology, Inc. | Arbitrated sense amplifier |
US11929112B2 (en) | 2020-07-27 | 2024-03-12 | Anhui University | Sense amplifier, memory, and method for controlling sense amplifier |
CN111863051B (zh) * | 2020-07-27 | 2022-11-22 | 安徽大学 | 灵敏放大器、存储器和灵敏放大器的控制方法 |
Family Cites Families (24)
Publication number | Priority date | Publication date | Assignee | Title |
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JP3169819B2 (ja) * | 1996-02-28 | 2001-05-28 | 日本電気アイシーマイコンシステム株式会社 | 半導体記憶装置 |
JP3532725B2 (ja) * | 1997-02-27 | 2004-05-31 | 株式会社東芝 | 半導体集積回路 |
US5841695A (en) * | 1997-05-29 | 1998-11-24 | Lsi Logic Corporation | Memory system using multiple storage mechanisms to enable storage and retrieval of more than two states in a memory cell |
JPH11110991A (ja) * | 1997-10-03 | 1999-04-23 | Sony Corp | 半導体記憶装置及びその読み出し方法 |
JP2000011642A (ja) * | 1998-06-24 | 2000-01-14 | Sony Corp | 3トランジスタ型dram |
JP3823550B2 (ja) * | 1998-07-17 | 2006-09-20 | ヤマハ株式会社 | メモリーセルの読出・書込回路 |
JP3957560B2 (ja) | 2002-05-23 | 2007-08-15 | 松下電器産業株式会社 | 半導体装置 |
US6778431B2 (en) * | 2002-12-13 | 2004-08-17 | International Business Machines Corporation | Architecture for high-speed magnetic memories |
JP2004265944A (ja) * | 2003-02-21 | 2004-09-24 | Handotai Rikougaku Kenkyu Center:Kk | 半導体記憶装置 |
KR100505707B1 (ko) * | 2003-08-26 | 2005-08-03 | 삼성전자주식회사 | 프로그램 동작시 가변되는 비트 라인의 전압 레벨을조절하는 플래쉬 메모리 장치의 프로그램 제어회로 및 그제어방법 |
US20050117424A1 (en) * | 2003-12-01 | 2005-06-02 | Chih-Ta Star Sung | Low power sensing scheme for the semiconductor memory |
US7023755B2 (en) | 2003-12-02 | 2006-04-04 | Micron Technology, Inc. | Low power control circuit and method for a memory device |
KR100528341B1 (ko) * | 2003-12-30 | 2005-11-15 | 삼성전자주식회사 | 자기 램 및 그 읽기방법 |
US7133311B2 (en) * | 2004-08-16 | 2006-11-07 | Bo Liu | Low power, high speed read method for a multi-level cell DRAM |
KR100798764B1 (ko) | 2004-10-30 | 2008-01-29 | 주식회사 하이닉스반도체 | 반도체 메모리 소자 및 그 내부 전압 생성 방법 |
JP4647313B2 (ja) * | 2005-01-06 | 2011-03-09 | 富士通セミコンダクター株式会社 | 半導体メモリ |
JP2006285116A (ja) * | 2005-04-05 | 2006-10-19 | Eastman Kodak Co | 駆動回路 |
DE102005029872A1 (de) * | 2005-06-27 | 2007-04-19 | Infineon Technologies Ag | Speicherzelle, Lesevorrichtung für die Speicherzelle sowie Speicheranordnungen mit einer derartigen Speicherzelle und Lesevorrichtung |
JP4262227B2 (ja) * | 2005-07-22 | 2009-05-13 | シャープ株式会社 | 半導体記憶装置の読み出し回路 |
JP2007122758A (ja) * | 2005-10-24 | 2007-05-17 | Sony Corp | 半導体メモリ装置およびその読み出し方法 |
KR100866623B1 (ko) * | 2006-10-16 | 2008-11-03 | 삼성전자주식회사 | 저전압에서 동작할 수 있는 비휘발성 메모리 장치의 센스앰프 회로 및 이를 포함하는 비휘발성 메모리 장치 |
US7400521B1 (en) * | 2007-01-12 | 2008-07-15 | Qimoda Ag | Integrated circuit, memory chip and method of evaluating a memory state of a resistive memory cell |
JP2008217844A (ja) * | 2007-02-28 | 2008-09-18 | Matsushita Electric Ind Co Ltd | 不揮発性半導体記憶装置 |
US7593284B2 (en) * | 2007-10-17 | 2009-09-22 | Unity Semiconductor Corporation | Memory emulation using resistivity-sensitive memory |
-
2010
- 2010-02-16 MY MYPI2011003353A patent/MY149776A/en unknown
- 2010-02-16 CN CN2010800081329A patent/CN102318008B/zh not_active Expired - Fee Related
- 2010-02-16 EP EP13169032.3A patent/EP2631914A1/en not_active Withdrawn
- 2010-02-16 KR KR1020117021477A patent/KR101197379B1/ko active IP Right Grant
- 2010-02-16 CA CA2749971A patent/CA2749971C/en not_active Expired - Fee Related
- 2010-02-16 JP JP2011551167A patent/JP5242814B2/ja not_active Expired - Fee Related
- 2010-02-16 SG SG2011058435A patent/SG173684A1/en unknown
- 2010-02-16 EP EP10744195.8A patent/EP2399261B1/en not_active Not-in-force
- 2010-02-16 US US12/706,374 patent/US8169812B2/en active Active
- 2010-02-16 AU AU2010216223A patent/AU2010216223B2/en not_active Ceased
- 2010-02-16 WO PCT/US2010/024332 patent/WO2010096393A1/en active Application Filing
- 2010-02-16 CN CN201310526964.5A patent/CN103531227B/zh not_active Expired - Fee Related
-
2012
- 2012-02-08 HK HK12101250.9A patent/HK1160982A1/xx not_active IP Right Cessation
-
2013
- 2013-04-03 JP JP2013077994A patent/JP5647288B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JP2013175275A (ja) | 2013-09-05 |
CN103531227A (zh) | 2014-01-22 |
EP2399261A1 (en) | 2011-12-28 |
JP5647288B2 (ja) | 2014-12-24 |
JP2012518865A (ja) | 2012-08-16 |
MY149776A (en) | 2013-10-14 |
KR20110128867A (ko) | 2011-11-30 |
EP2631914A1 (en) | 2013-08-28 |
CN103531227B (zh) | 2016-12-07 |
AU2010216223A1 (en) | 2011-08-04 |
EP2399261A4 (en) | 2012-10-31 |
US20100315858A1 (en) | 2010-12-16 |
CN102318008B (zh) | 2013-10-23 |
CN102318008A (zh) | 2012-01-11 |
AU2010216223B2 (en) | 2012-07-12 |
CA2749971A1 (en) | 2010-08-26 |
KR101197379B1 (ko) | 2012-11-05 |
WO2010096393A1 (en) | 2010-08-26 |
EP2399261B1 (en) | 2013-11-20 |
US8169812B2 (en) | 2012-05-01 |
JP5242814B2 (ja) | 2013-07-24 |
SG173684A1 (en) | 2011-09-29 |
CA2749971C (en) | 2013-04-16 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PC | Patent ceased (i.e. patent has lapsed due to the failure to pay the renewal fee) |
Effective date: 20190211 |