FR2912258B1 - "procede de fabrication d'un substrat du type silicium sur isolant" - Google Patents
"procede de fabrication d'un substrat du type silicium sur isolant"Info
- Publication number
- FR2912258B1 FR2912258B1 FR0700718A FR0700718A FR2912258B1 FR 2912258 B1 FR2912258 B1 FR 2912258B1 FR 0700718 A FR0700718 A FR 0700718A FR 0700718 A FR0700718 A FR 0700718A FR 2912258 B1 FR2912258 B1 FR 2912258B1
- Authority
- FR
- France
- Prior art keywords
- insulation
- substrate
- manufacturing
- silicon type
- silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title 1
- 238000009413 insulation Methods 0.000 title 1
- 238000004519 manufacturing process Methods 0.000 title 1
- 229910052710 silicon Inorganic materials 0.000 title 1
- 239000010703 silicon Substances 0.000 title 1
- 239000000758 substrate Substances 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76259—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along a porous layer
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
- Recrystallisation Techniques (AREA)
- Formation Of Insulating Films (AREA)
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR0700718A FR2912258B1 (fr) | 2007-02-01 | 2007-02-01 | "procede de fabrication d'un substrat du type silicium sur isolant" |
| US11/848,964 US7666758B2 (en) | 2007-02-01 | 2007-08-31 | Process for fabricating a substrate of the silicon-on-insulator type with thin surface layer |
| PCT/IB2008/000132 WO2008093187A1 (fr) | 2007-02-01 | 2008-01-16 | Procédé de production d'un substrat du type silicium sur isolant |
| DE112008000226.6T DE112008000226B4 (de) | 2007-02-01 | 2008-01-16 | Verfahren zum Herstellen eines Substrats vom Typ Silizium auf Isolator (SOI) |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR0700718A FR2912258B1 (fr) | 2007-02-01 | 2007-02-01 | "procede de fabrication d'un substrat du type silicium sur isolant" |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| FR2912258A1 FR2912258A1 (fr) | 2008-08-08 |
| FR2912258B1 true FR2912258B1 (fr) | 2009-05-08 |
Family
ID=38157863
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| FR0700718A Active FR2912258B1 (fr) | 2007-02-01 | 2007-02-01 | "procede de fabrication d'un substrat du type silicium sur isolant" |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US7666758B2 (fr) |
| DE (1) | DE112008000226B4 (fr) |
| FR (1) | FR2912258B1 (fr) |
| WO (1) | WO2008093187A1 (fr) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5527956B2 (ja) * | 2007-10-10 | 2014-06-25 | 株式会社半導体エネルギー研究所 | 半導体基板の製造方法 |
| JP5490393B2 (ja) * | 2007-10-10 | 2014-05-14 | 株式会社半導体エネルギー研究所 | 半導体基板の製造方法 |
| US7820527B2 (en) * | 2008-02-20 | 2010-10-26 | Varian Semiconductor Equipment Associates, Inc. | Cleave initiation using varying ion implant dose |
| FR2965396B1 (fr) * | 2010-09-29 | 2013-02-22 | S O I Tec Silicon On Insulator Tech | Substrat démontable, procédés de fabrication et de démontage d'un tel substrat |
| JP6086031B2 (ja) | 2013-05-29 | 2017-03-01 | 信越半導体株式会社 | 貼り合わせウェーハの製造方法 |
| FR3036200B1 (fr) * | 2015-05-13 | 2017-05-05 | Soitec Silicon On Insulator | Methode de calibration pour equipements de traitement thermique |
| US20210389183A1 (en) * | 2018-11-09 | 2021-12-16 | Yale University | High-speed ultrathin silicon-on-insulator infrared bolometers and imagers |
| FR3103055A1 (fr) * | 2019-11-08 | 2021-05-14 | Soitec | Procédé de finition d’une couche semi-conductrice monocristalline transférée sur un substrat receveur |
Family Cites Families (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| SG65697A1 (en) | 1996-11-15 | 1999-06-22 | Canon Kk | Process for producing semiconductor article |
| JP2000124092A (ja) | 1998-10-16 | 2000-04-28 | Shin Etsu Handotai Co Ltd | 水素イオン注入剥離法によってｓｏｉウエーハを製造する方法およびこの方法で製造されたｓｏｉウエーハ |
| FR2797713B1 (fr) * | 1999-08-20 | 2002-08-02 | Soitec Silicon On Insulator | Procede de traitement de substrats pour la microelectronique et substrats obtenus par ce procede |
| JP3943782B2 (ja) | 1999-11-29 | 2007-07-11 | 信越半導体株式会社 | 剥離ウエーハの再生処理方法及び再生処理された剥離ウエーハ |
| FR2827423B1 (fr) | 2001-07-16 | 2005-05-20 | Soitec Silicon On Insulator | Procede d'amelioration d'etat de surface |
| KR100874724B1 (ko) | 2001-07-17 | 2008-12-19 | 신에쯔 한도타이 가부시키가이샤 | 접합 웨이퍼의 제조방법 |
| CN100403543C (zh) * | 2001-12-04 | 2008-07-16 | 信越半导体株式会社 | 贴合晶片及贴合晶片的制造方法 |
| JP2004063730A (ja) | 2002-07-29 | 2004-02-26 | Shin Etsu Handotai Co Ltd | Ｓｏｉウェーハの製造方法 |
| FR2858462B1 (fr) * | 2003-07-29 | 2005-12-09 | Soitec Silicon On Insulator | Procede d'obtention d'une couche mince de qualite accrue par co-implantation et recuit thermique |
| JPWO2005022610A1 (ja) * | 2003-09-01 | 2007-11-01 | 株式会社Sumco | 貼り合わせウェーハの製造方法 |
| EP1662555B1 (fr) * | 2003-09-05 | 2011-04-13 | SUMCO Corporation | Procede de production d'une plaquette soi |
| FR2861497B1 (fr) | 2003-10-28 | 2006-02-10 | Soitec Silicon On Insulator | Procede de transfert catastrophique d'une couche fine apres co-implantation |
| CN101027768B (zh) * | 2004-09-21 | 2010-11-03 | S.O.I.Tec绝缘体上硅技术公司 | 根据避免气泡形成和限制粗糙度的条件来进行共注入步骤的薄层转移方法 |
| FR2880988B1 (fr) | 2005-01-19 | 2007-03-30 | Soitec Silicon On Insulator | TRAITEMENT D'UNE COUCHE EN SI1-yGEy PRELEVEE |
| JP4934966B2 (ja) * | 2005-02-04 | 2012-05-23 | 株式会社Ｓｕｍｃｏ | Ｓｏｉ基板の製造方法 |
| JP2006216826A (ja) | 2005-02-04 | 2006-08-17 | Sumco Corp | Ｓｏｉウェーハの製造方法 |
-
2007
- 2007-02-01 FR FR0700718A patent/FR2912258B1/fr active Active
- 2007-08-31 US US11/848,964 patent/US7666758B2/en active Active
-
2008
- 2008-01-16 WO PCT/IB2008/000132 patent/WO2008093187A1/fr active Application Filing
- 2008-01-16 DE DE112008000226.6T patent/DE112008000226B4/de active Active
Also Published As
| Publication number | Publication date |
|---|---|
| US20080188060A1 (en) | 2008-08-07 |
| DE112008000226B4 (de) | 2024-02-01 |
| US7666758B2 (en) | 2010-02-23 |
| WO2008093187A1 (fr) | 2008-08-07 |
| FR2912258A1 (fr) | 2008-08-08 |
| DE112008000226T5 (de) | 2010-01-21 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| CD | Change of name or company name |
Owner name: SOITEC, FR Effective date: 20120423 |
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| PLFP | Fee payment |
Year of fee payment: 10 |
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