FR2933534B1 - Procede de fabrication d'une structure comprenant une couche de germanium sur un substrat - Google Patents

Procede de fabrication d'une structure comprenant une couche de germanium sur un substrat

Info

Publication number
FR2933534B1
FR2933534B1 FR0854510A FR0854510A FR2933534B1 FR 2933534 B1 FR2933534 B1 FR 2933534B1 FR 0854510 A FR0854510 A FR 0854510A FR 0854510 A FR0854510 A FR 0854510A FR 2933534 B1 FR2933534 B1 FR 2933534B1
Authority
FR
France
Prior art keywords
substrate
manufacturing
germanium layer
germanium
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR0854510A
Other languages
English (en)
Other versions
FR2933534A1 (fr
Inventor
Nicolas Daval
Oleg Kononchuk
Eric Guiot
Cecile Aulnette
Fabrice Lallement
Christophe Figuet
Didier Landru
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Original Assignee
Soitec SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to FR0854510A priority Critical patent/FR2933534B1/fr
Application filed by Soitec SA filed Critical Soitec SA
Priority to KR1020107024928A priority patent/KR20110003522A/ko
Priority to EP09772296A priority patent/EP2294611A1/fr
Priority to CN2009801145931A priority patent/CN102017124A/zh
Priority to US12/937,920 priority patent/US20110183493A1/en
Priority to PCT/EP2009/057293 priority patent/WO2010000596A1/fr
Priority to JP2011512155A priority patent/JP2011522432A/ja
Publication of FR2933534A1 publication Critical patent/FR2933534A1/fr
Application granted granted Critical
Publication of FR2933534B1 publication Critical patent/FR2933534B1/fr
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76256—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques using silicon etch back techniques, e.g. BESOI, ELTRAN

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Recrystallisation Techniques (AREA)
FR0854510A 2008-07-03 2008-07-03 Procede de fabrication d'une structure comprenant une couche de germanium sur un substrat Expired - Fee Related FR2933534B1 (fr)

Priority Applications (7)

Application Number Priority Date Filing Date Title
FR0854510A FR2933534B1 (fr) 2008-07-03 2008-07-03 Procede de fabrication d'une structure comprenant une couche de germanium sur un substrat
EP09772296A EP2294611A1 (fr) 2008-07-03 2009-06-12 Procédé de fabrication d'une structure pourvue d une couche de germanium sur un substrat
CN2009801145931A CN102017124A (zh) 2008-07-03 2009-06-12 包括基片上覆锗层的结构体的制造方法
US12/937,920 US20110183493A1 (en) 2008-07-03 2009-06-12 Process for manufacturing a structure comprising a germanium layer on a substrate
KR1020107024928A KR20110003522A (ko) 2008-07-03 2009-06-12 기판상에 게르마늄층을 포함하는 구조를 제조하기 위한 프로세스
PCT/EP2009/057293 WO2010000596A1 (fr) 2008-07-03 2009-06-12 Procédé de fabrication d'une structure pourvue d’une couche de germanium sur un substrat
JP2011512155A JP2011522432A (ja) 2008-07-03 2009-06-12 基板上にゲルマニウム層を含む構造の製造プロセス

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0854510A FR2933534B1 (fr) 2008-07-03 2008-07-03 Procede de fabrication d'une structure comprenant une couche de germanium sur un substrat

Publications (2)

Publication Number Publication Date
FR2933534A1 FR2933534A1 (fr) 2010-01-08
FR2933534B1 true FR2933534B1 (fr) 2011-04-01

Family

ID=40032913

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0854510A Expired - Fee Related FR2933534B1 (fr) 2008-07-03 2008-07-03 Procede de fabrication d'une structure comprenant une couche de germanium sur un substrat

Country Status (7)

Country Link
US (1) US20110183493A1 (fr)
EP (1) EP2294611A1 (fr)
JP (1) JP2011522432A (fr)
KR (1) KR20110003522A (fr)
CN (1) CN102017124A (fr)
FR (1) FR2933534B1 (fr)
WO (1) WO2010000596A1 (fr)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102184953B (zh) * 2011-03-10 2013-03-27 清华大学 应变GeOI结构及其形成方法
CN102184954B (zh) * 2011-03-10 2013-03-27 清华大学 应变Ge沟道器件及其形成方法
FR2977069B1 (fr) 2011-06-23 2014-02-07 Soitec Silicon On Insulator Procede de fabrication d'une structure semi-conductrice mettant en oeuvre un collage temporaire
CN102420167A (zh) * 2011-12-05 2012-04-18 中国科学院微电子研究所 一种绝缘体上锗衬底的减薄方法
FR2995447B1 (fr) 2012-09-07 2014-09-05 Soitec Silicon On Insulator Procede de separation d'au moins deux substrats selon une interface choisie
KR102150252B1 (ko) * 2013-11-12 2020-09-02 삼성전자주식회사 반도체 장치 제조방법
US9384964B1 (en) 2014-08-01 2016-07-05 Samsung Electronics Co., Ltd. Method of manufacturing semiconductor device
CN104701425A (zh) * 2015-04-08 2015-06-10 常州时创能源科技有限公司 晶体硅太阳能电池的扩散后处理工艺
KR102342850B1 (ko) * 2015-04-17 2021-12-23 삼성전자주식회사 반도체 소자의 제조를 위한 유전체층의 큐어링 방법
KR101889352B1 (ko) * 2016-09-13 2018-08-20 한국과학기술연구원 변형된 저마늄을 포함하는 반도체 소자의 제조 방법 및 이에 의해 제조된 반도체 소자
CN113675218A (zh) * 2020-05-14 2021-11-19 上海功成半导体科技有限公司 Fd-soi衬底结构及器件结构

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7084460B2 (en) * 2003-11-03 2006-08-01 International Business Machines Corporation Method for fabricating SiGe-on-insulator (SGOI) and Ge-on-insulator (GOI) substrates
US6958286B2 (en) * 2004-01-02 2005-10-25 International Business Machines Corporation Method of preventing surface roughening during hydrogen prebake of SiGe substrates
WO2006012544A2 (fr) * 2004-07-22 2006-02-02 The Board Of Trustees Of The Leland Stanford Junior University Materiaux de type substrat de germanium et approche associee
EP1659623B1 (fr) * 2004-11-19 2008-04-16 S.O.I. Tec Silicon on Insulator Technologies S.A. Méthode de fabrication d'une plaquette de type germanium sur isolant (GeOI)
JP2006270000A (ja) * 2005-03-25 2006-10-05 Sumco Corp 歪Ｓｉ−ＳＯＩ基板の製造方法および該方法により製造された歪Ｓｉ−ＳＯＩ基板
FR2892230B1 (fr) * 2005-10-19 2008-07-04 Soitec Silicon On Insulator Traitement d'une couche de germamium
US7767541B2 (en) * 2005-10-26 2010-08-03 International Business Machines Corporation Methods for forming germanium-on-insulator semiconductor structures using a porous layer and semiconductor structures formed by these methods
EP2095415B1 (fr) * 2006-12-26 2010-10-27 S.O.I.Tec Silicon on Insulator Technologies Procédé de production d'une structure semiconducteur sur isolant
FR2911430B1 (fr) * 2007-01-15 2009-04-17 Soitec Silicon On Insulator "procede de fabrication d'un substrat hybride"

Also Published As

Publication number Publication date
JP2011522432A (ja) 2011-07-28
US20110183493A1 (en) 2011-07-28
EP2294611A1 (fr) 2011-03-16
WO2010000596A1 (fr) 2010-01-07
CN102017124A (zh) 2011-04-13
KR20110003522A (ko) 2011-01-12
FR2933534A1 (fr) 2010-01-08

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Legal Events

Date Code Title Description
CD Change of name or company name

Owner name: SOITEC, FR

Effective date: 20120423

ST Notification of lapse

Effective date: 20140331