FR2406251A1 - IMPROVEMENTS TO A DATA TRANSFER CONTROL SYSTEM - Google Patents

IMPROVEMENTS TO A DATA TRANSFER CONTROL SYSTEM

Info

Publication number
FR2406251A1
FR2406251A1 FR7822752A FR7822752A FR2406251A1 FR 2406251 A1 FR2406251 A1 FR 2406251A1 FR 7822752 A FR7822752 A FR 7822752A FR 7822752 A FR7822752 A FR 7822752A FR 2406251 A1 FR2406251 A1 FR 2406251A1
Authority
FR
France
Prior art keywords
fifo
data
processing system
input register
buffers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7822752A
Other languages
French (fr)
Other versions
FR2406251B1 (en
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Bull HN Information Systems Italia SpA
Bull HN Information Systems Inc
Original Assignee
Honeywell Information Systems Italia SpA
Honeywell Information Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US05/821,900 external-priority patent/US4204250A/en
Priority claimed from US05/821,931 external-priority patent/US4159532A/en
Application filed by Honeywell Information Systems Italia SpA, Honeywell Information Systems Inc filed Critical Honeywell Information Systems Italia SpA
Publication of FR2406251A1 publication Critical patent/FR2406251A1/en
Application granted granted Critical
Publication of FR2406251B1 publication Critical patent/FR2406251B1/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/10—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory
    • G06F5/12—Means for monitoring the fill level; Means for resolving contention, i.e. conflicts between simultaneous enqueue and dequeue operations
    • G06F5/14—Means for monitoring the fill level; Means for resolving contention, i.e. conflicts between simultaneous enqueue and dequeue operations for overflow or underflow handling, e.g. full or empty flags
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Bus Control (AREA)
  • Debugging And Monitoring (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Communication Control (AREA)
  • Information Transfer Systems (AREA)

Abstract

L'invention concerne un système de commande de transfert de données pour maintenir un débit de transfert de données sans perte dans un système de traitement de données. Le système comprend un ensemble de tampons de données premier entré-premier sorti FIFO, un tampon prédiseur FIFO contenant un registre d'entrée et fonctionnant en parallèle avec ledit ensemble, des moyens pour engendrer une demande de données d'un contrôleur de périphériques à une mémoire principale du système de traitement de données par un bus commun de communication, des moyens pour charger un multiplet indicateur dans le tampon prédiseur FIFO, des moyens pour détecter le contenu du registre d'entrée pendant le chargement de données, mot par mot, de la mémoire principale dans l'ensemble des tampons FIFO, et des moyens pour décharger l'ensemble des tampons FIFO et le tampon prédiseur FIFO quand le registre d'entrée est rempli. Application au transfert de données entre des unités de disques et un bus commun de communication d'un système de traitement de données à chaîne de micro-instructions.A data transfer control system for maintaining a lossless data transfer rate in a data processing system is provided. The system comprises a set of FIFO first-in-first-out data buffers, a FIFO predator buffer containing an input register and operating in parallel with said set, means for generating a request for data from a peripheral controller to a device controller. main memory of the data processing system by a common communication bus, means for loading an indicator byte into the FIFO predator buffer, means for detecting the contents of the input register during the loading of data, word by word, of main memory in the set of FIFO buffers, and means for unloading the set of FIFO buffers and the FIFO predictor buffer when the input register is full. Application to the transfer of data between disk units and a common communication bus of a micro-instruction chain data processing system.

FR7822752A 1977-08-04 1978-08-01 IMPROVEMENTS TO A DATA TRANSFER CONTROL SYSTEM Expired FR2406251B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US05/821,900 US4204250A (en) 1977-08-04 1977-08-04 Range count and main memory address accounting system
US05/821,931 US4159532A (en) 1977-08-04 1977-08-04 FIFO look-ahead system

Publications (2)

Publication Number Publication Date
FR2406251A1 true FR2406251A1 (en) 1979-05-11
FR2406251B1 FR2406251B1 (en) 1986-01-10

Family

ID=27124602

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7822752A Expired FR2406251B1 (en) 1977-08-04 1978-08-01 IMPROVEMENTS TO A DATA TRANSFER CONTROL SYSTEM

Country Status (3)

Country Link
DE (2) DE2831709A1 (en)
FR (1) FR2406251B1 (en)
GB (2) GB2002936B (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3241356A1 (en) * 1982-11-09 1984-05-10 Siemens AG, 1000 Berlin und 8000 München DEVICE FOR MICROPROGRAM CONTROL OF AN INFORMATION TRANSFER AND METHOD FOR THEIR OPERATION
JP2004070570A (en) * 2002-08-05 2004-03-04 Seiko Epson Corp Data transfer control system, electronic equipment, program and data transfer control method
GB2500255B (en) 2012-03-16 2020-04-15 Oxsensis Ltd Optical sensor

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3351917A (en) * 1965-02-05 1967-11-07 Burroughs Corp Information storage and retrieval system having a dynamic memory device
GB1264096A (en) * 1970-06-27 1972-02-16
FR2209979A1 (en) * 1972-12-11 1974-07-05 Cable & Wireless Ltd
FR2260141A1 (en) * 1974-02-01 1975-08-29 Honeywell Bull Soc Ind Data transfer control for data processor - is used between periodic and non-periodic units employing buffer memory

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3993981A (en) * 1975-06-30 1976-11-23 Honeywell Information Systems, Inc. Apparatus for processing data transfer requests in a data processing system

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3351917A (en) * 1965-02-05 1967-11-07 Burroughs Corp Information storage and retrieval system having a dynamic memory device
GB1264096A (en) * 1970-06-27 1972-02-16
FR2209979A1 (en) * 1972-12-11 1974-07-05 Cable & Wireless Ltd
FR2260141A1 (en) * 1974-02-01 1975-08-29 Honeywell Bull Soc Ind Data transfer control for data processor - is used between periodic and non-periodic units employing buffer memory

Also Published As

Publication number Publication date
DE2858284A1 (en) 1985-07-04
GB2002936A (en) 1979-02-28
DE2858284C2 (en) 1987-05-21
DE2831709C2 (en) 1990-10-04
FR2406251B1 (en) 1986-01-10
GB2061577A (en) 1981-05-13
GB2061577B (en) 1982-10-20
DE2831709A1 (en) 1979-02-22
GB2002936B (en) 1982-04-28

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Legal Events

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