KR960038643A - Dual Processor Interface Device - Google Patents

Dual Processor Interface Device Download PDF

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Publication number
KR960038643A
KR960038643A KR1019950008701A KR19950008701A KR960038643A KR 960038643 A KR960038643 A KR 960038643A KR 1019950008701 A KR1019950008701 A KR 1019950008701A KR 19950008701 A KR19950008701 A KR 19950008701A KR 960038643 A KR960038643 A KR 960038643A
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KR
South Korea
Prior art keywords
data
main processor
subprocessor
fifo
indicating
Prior art date
Application number
KR1019950008701A
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Korean (ko)
Other versions
KR100326156B1 (en
Inventor
이재성
Original Assignee
김광호
삼성전자 주식회사
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Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019950008701A priority Critical patent/KR100326156B1/en
Publication of KR960038643A publication Critical patent/KR960038643A/en
Application granted granted Critical
Publication of KR100326156B1 publication Critical patent/KR100326156B1/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2205/00—Indexing scheme relating to group G06F5/00; Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F2205/06—Indexing scheme relating to groups G06F5/06 - G06F5/16
    • G06F2205/067—Bidirectional FIFO, i.e. system allowing data transfer in two directions

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Hardware Redundancy (AREA)
  • Information Transfer Systems (AREA)

Abstract

1. 청구범위에 기재된 발명이 속하는 기술분야; 본 발명은 듀얼 프로세서간의 데이타 전송을 위한 듀얼 프로세서간 인터페이스 장치에 관한 것이다.1. the technical field to which the invention described in the claims belongs; The present invention relates to a dual interprocessor interface device for data transfer between dual processors.

2. 발명이 해결하고자하는 기술적 과제; 본 발명은 구성을 단순화하고, 듀얼 프로세서간 명령 데이타 전송을 인터페이싱 할 수 있는 듀얼 프로세서간 인터페이스장치를 제공함에 있다.2. The technical problem to be solved by the invention; The present invention provides a dual interprocessor interface device that simplifies configuration and can interface command data transfer between dual processors.

3. 발명의 해결방법의 요지; 본 발명은 듀얼 프로세서간의 데이타전송에 있어서, 각 프로세서의 데이타 전송을 위한 FIFO를 구비하여 구성을 단순화하고 병렬 데이타 전송을 이룬다.3. Summary of the Solution of the Invention; In the present invention, data transfer between dual processors includes a FIFO for data transfer of each processor, thereby simplifying configuration and achieving parallel data transfer.

4. 발명의 중요한 용도; 본 발명은 디스크구동 기록장치의 전반적인 동작을 제어하는 듀얼프로세서간에 특히 중요히 사용될 수 있다.4. Significant use of the invention; The present invention can be particularly important among dual processors which control the overall operation of the disc drive recording apparatus.

Description

듀얼프로세서간 인터페이스 장치Dual Processor Interface Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 본 발명의 바람직한 일 실시예에 따른 디스크구동기록장치의 프로세서간 인터페이스 장치의 블록구성도, 제2도는 제1도의 구성에 따른 타이밍도1 is a block diagram of an interprocessor interface device of a disk drive recording apparatus according to an embodiment of the present invention, and FIG. 2 is a timing diagram according to the configuration of FIG.

Claims (1)

주프로세서 및 부프로세서를 구비하는 듀얼 프로세서간 통신장치에 있어서; 상기 주프로세서로부터 상기 부프로세서로의 처리명령 및 데이타를 전송하기 위한 제1 및 제2 FIFO 와; 상기 부프로세서로부터 상기 주프로세서로의 명령에 대한 결과 또는 데이타를 전송하기 위한 제3FIFO 와; 상기 부프로세서로부터 상기 주프로세서에 대한 현재 동작상태를 알리는 상태 데이타와, 사이 부프로세서가 상기 주프로세서의 명령에 대한 동작 수행중의 상태를 알리는 결과데이타를 입력받아 상기 주프로세서로 출력하는 레지스터와; 상기 주프로세서로부터 입력되는 데이타를 입력받으며, 상기 주프로세서로부터의 소정 선택제어신호의 입력에 대응하여 상기 입력 데이타를 상기 제1FIFO 또는 상기 FIFO로 선택적출하는 선택수단과; 상기 부프로세서로부터 프로세서간 통신을 위한 준비상태를 알리는 제1신호를 상기 주프로세서로 래치출력하는 제1래치수단과; 상기 제FIFO의 데이타 엠프티 상태를 감지하여 상기 주프로세서로 래치출력하는 제2래치수단과; 상기 주프로세서로부터 상기 제1 및 제2 FIFO에 데이타가 채워졌으며 데이타리드 인에이블상태임을 알리는 제3신호를 입력받아 상기 부프로세서로 래치출력하는 제3래치수단과; 상기 제2FIFO의 데이타 엠프티 상태를 알리는 제4신호를 상기 부프로세서로부터 입력받아 래치출력하는 제4래치수단과; 상기 부프로세서로부터 상기 제3FIFO에 데이타가 채워졌으며 데이타리드인에이블 상태임을 알리는 제5신호를 입력받아 상기 주프로세서로 래치출력하는 제5래치수단으로 구성함을 특징으로 하는 듀얼 프로세서간 인터페이스장치.A dual interprocessor communication device having a main processor and a subprocessor; First and second FIFOs for transferring processing instructions and data from the main processor to the subprocessor; A third FIFO for transferring results or data for instructions from the subprocessor to the main processor; A register configured to receive status data indicating a current operation state of the main processor from the subprocessor and result data indicating a state in which a subprocessor performs an operation on an instruction of the main processor, and output the result data to the main processor; Selection means for receiving data input from the main processor and selectively outputting the input data to the first FIFO or the FIFO in response to an input of a predetermined selection control signal from the main processor; First latch means for latching a first signal from the subprocessor to the main processor, the first signal informing of a ready state for inter-processor communication; Second latch means for latching and outputting a data empty state of the FIFO to the main processor; Third latch means for latching and outputting a third signal from the main processor to the first and second FIFOs indicating that data is filled and data lead enabled; Fourth latch means for latching and receiving a fourth signal indicating the data empty state of the second FIFO from the subprocessor; And a fifth latch means for latching and outputting the fifth signal indicating that the data is filled in the third FIFO from the subprocessor and indicating that the data lead is enabled.
KR1019950008701A 1995-04-13 1995-04-13 Interface device between dual processors KR100326156B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950008701A KR100326156B1 (en) 1995-04-13 1995-04-13 Interface device between dual processors

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950008701A KR100326156B1 (en) 1995-04-13 1995-04-13 Interface device between dual processors

Publications (2)

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KR960038643A true KR960038643A (en) 1996-11-21
KR100326156B1 KR100326156B1 (en) 2002-06-29

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010061541A (en) * 1999-12-28 2001-07-07 송재인 3 line handshaking interface
KR100663384B1 (en) * 2005-12-30 2007-01-02 엠텍비젼 주식회사 Device and method for memory interface
KR100708952B1 (en) * 2003-05-27 2007-04-18 닛본 덴끼 가부시끼가이샤 Parallel processing system, computer readable recording medium for recording parallel processing program, and parallel processing method

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100879567B1 (en) 2007-04-27 2009-01-22 엠텍비젼 주식회사 Dual Port Memory for directly transferring data between processors using first-in first-out and memory system thereof

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010061541A (en) * 1999-12-28 2001-07-07 송재인 3 line handshaking interface
KR100708952B1 (en) * 2003-05-27 2007-04-18 닛본 덴끼 가부시끼가이샤 Parallel processing system, computer readable recording medium for recording parallel processing program, and parallel processing method
KR100663384B1 (en) * 2005-12-30 2007-01-02 엠텍비젼 주식회사 Device and method for memory interface

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