JPS54103649A - Data transmission control system between arithmetic control elements - Google Patents
Data transmission control system between arithmetic control elementsInfo
- Publication number
- JPS54103649A JPS54103649A JP1098478A JP1098478A JPS54103649A JP S54103649 A JPS54103649 A JP S54103649A JP 1098478 A JP1098478 A JP 1098478A JP 1098478 A JP1098478 A JP 1098478A JP S54103649 A JPS54103649 A JP S54103649A
- Authority
- JP
- Japan
- Prior art keywords
- data
- register
- fifo
- data transmission
- cpu
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Multi Processors (AREA)
Abstract
PURPOSE: To ensure the highly reliable data transfer via the simple hardware constitution by performing the data transfer between two CPU's through the FiFo register.
CONSTITUTION: When the data is supplied to FiFo (first-IN and first-Out) register 7 and 8, READ and READY signals 7a and 8a are supplied to CPU5 and 6. Then each CPU draws in the data within the FiFo registers and can transmit the data to the FiFo register since the data is idle within FiFo an when WRITE and READy signals 7b and 8b exist. Therefore, the existence of signal 8b is first checked to transmit the data to register 8 in case the data is sent to CPU6 from 5. On the other hand, CPU6 draws in the data of register 8 after checking signal 8a. In the same way, the data can be sent to CPU5 from 6. Thus, the data transmission is possible between CPU's through the simple constitution.
COPYRIGHT: (C)1979,JPO&Japio
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1098478A JPS597987B2 (en) | 1978-02-01 | 1978-02-01 | Data transmission control method between arithmetic control elements |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1098478A JPS597987B2 (en) | 1978-02-01 | 1978-02-01 | Data transmission control method between arithmetic control elements |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS54103649A true JPS54103649A (en) | 1979-08-15 |
| JPS597987B2 JPS597987B2 (en) | 1984-02-22 |
Family
ID=11765405
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1098478A Expired JPS597987B2 (en) | 1978-02-01 | 1978-02-01 | Data transmission control method between arithmetic control elements |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS597987B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56110169A (en) * | 1980-02-06 | 1981-09-01 | Fujitsu Ltd | Multiprocessor processing system |
| JPS58501740A (en) * | 1981-10-05 | 1983-10-13 | デイジタル イクイプメント コーポレーシヨン | An interface mechanism for paired processors such as host and peripheral control processors in a data processing system. |
| JPH05205005A (en) * | 1990-03-30 | 1993-08-13 | Internatl Business Mach Corp <Ibm> | Host-interface for logic-simulation-machine |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6157284A (en) * | 1984-08-28 | 1986-03-24 | 東京瓦斯株式会社 | Method of inserting wire into pipe |
| JPH02125195A (en) * | 1988-11-02 | 1990-05-14 | Kanpai:Kk | Parachute body for removing intra-pipe gas |
-
1978
- 1978-02-01 JP JP1098478A patent/JPS597987B2/en not_active Expired
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56110169A (en) * | 1980-02-06 | 1981-09-01 | Fujitsu Ltd | Multiprocessor processing system |
| JPS5835294B2 (en) * | 1980-02-06 | 1983-08-02 | 富士通株式会社 | Multiprocessor processing method |
| JPS58501740A (en) * | 1981-10-05 | 1983-10-13 | デイジタル イクイプメント コーポレーシヨン | An interface mechanism for paired processors such as host and peripheral control processors in a data processing system. |
| JPH05205005A (en) * | 1990-03-30 | 1993-08-13 | Internatl Business Mach Corp <Ibm> | Host-interface for logic-simulation-machine |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS597987B2 (en) | 1984-02-22 |
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