FR2358750A1 - Dispositifs semi-conducteurs comportant a leurs faces superieures une zone polycristalline et leur procede de fabrication - Google Patents

Dispositifs semi-conducteurs comportant a leurs faces superieures une zone polycristalline et leur procede de fabrication

Info

Publication number
FR2358750A1
FR2358750A1 FR7721776A FR7721776A FR2358750A1 FR 2358750 A1 FR2358750 A1 FR 2358750A1 FR 7721776 A FR7721776 A FR 7721776A FR 7721776 A FR7721776 A FR 7721776A FR 2358750 A1 FR2358750 A1 FR 2358750A1
Authority
FR
France
Prior art keywords
polycrystalline silicon
manufacturing process
semiconductor devices
devices including
upper faces
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7721776A
Other languages
English (en)
Other versions
FR2358750B1 (fr
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Publication of FR2358750A1 publication Critical patent/FR2358750A1/fr
Application granted granted Critical
Publication of FR2358750B1 publication Critical patent/FR2358750B1/fr
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53271—Conductive materials containing semiconductor material, e.g. polysilicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H01L29/456—Ohmic electrodes on silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/018—Compensation doping
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/02—Contacts, special
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/124—Polycrystalline emitter

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Bipolar Transistors (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

L'invention concerne un dispositif semi-conducteur comprenant un substrat semi-conducteur, un corps semi-conducteur en silicium polycristallin s'étendant vers le haut d'une partie de la surface du substrat semi-conducteur, et une électrode en métal disposée sur la surface supérieure du corps semi-conducteur en silicium polycristallin. Selon l'invention, le corps semi-conducteur en silicium polycristallin 33 ou 40 a une concentration sensiblement uniforme en impureté, et l'électrode en métal 36 ou 43 s'étend en direction latérale au-delà du pourtour de la surface supérieure du corps semi-conducteur en silicium polycristallin. L'invention s'applique à la formation des transistors bipolaires, transistors MOS et analogues.
FR7721776A 1976-07-15 1977-07-13 Dispositifs semi-conducteurs comportant a leurs faces superieures une zone polycristalline et leur procede de fabrication Granted FR2358750A1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8349376A JPS539469A (en) 1976-07-15 1976-07-15 Semiconductor device having electrode of stepped structure and its production

Publications (2)

Publication Number Publication Date
FR2358750A1 true FR2358750A1 (fr) 1978-02-10
FR2358750B1 FR2358750B1 (fr) 1983-03-25

Family

ID=13803997

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7721776A Granted FR2358750A1 (fr) 1976-07-15 1977-07-13 Dispositifs semi-conducteurs comportant a leurs faces superieures une zone polycristalline et leur procede de fabrication

Country Status (7)

Country Link
US (1) US4188707A (fr)
JP (1) JPS539469A (fr)
CA (1) CA1085969A (fr)
DE (1) DE2732184C2 (fr)
FR (1) FR2358750A1 (fr)
GB (1) GB1567808A (fr)
NL (1) NL190255C (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0054259A2 (fr) * 1980-12-12 1982-06-23 Kabushiki Kaisha Toshiba Procédé de fabrication d'un dispositif semiconducteur du type MIS
EP0199061A2 (fr) * 1985-03-23 1986-10-29 Itt Industries, Inc. Dispositif semi-conducteur
US4622735A (en) * 1980-12-12 1986-11-18 Tokyo Shibaura Denki Kabushiki Kaisha Method for manufacturing a semiconductor device utilizing self-aligned silicide regions

Families Citing this family (39)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4277883A (en) * 1977-12-27 1981-07-14 Raytheon Company Integrated circuit manufacturing method
NL190710C (nl) * 1978-02-10 1994-07-01 Nec Corp Geintegreerde halfgeleiderketen.
CA1129118A (fr) * 1978-07-19 1982-08-03 Tetsushi Sakai Dispositifs a semi-conducteurs et methode de fabrication
CA1136773A (fr) * 1978-08-14 1982-11-30 Norikazu Ohuchi Dispositif semiconducteur
JPS5951743B2 (ja) * 1978-11-08 1984-12-15 株式会社日立製作所 半導体集積装置
US4319932A (en) * 1980-03-24 1982-03-16 International Business Machines Corporation Method of making high performance bipolar transistor with polysilicon base contacts
US4259680A (en) * 1980-04-17 1981-03-31 Bell Telephone Laboratories, Incorporated High speed lateral bipolar transistor
US4411708A (en) * 1980-08-25 1983-10-25 Trw Inc. Method of making precision doped polysilicon vertical ballast resistors by multiple implantations
US4888297A (en) * 1982-09-20 1989-12-19 International Business Machines Corporation Process for making a contact structure including polysilicon and metal alloys
US4547959A (en) * 1983-02-22 1985-10-22 General Motors Corporation Uses for buried contacts in integrated circuits
US4738936A (en) * 1983-07-01 1988-04-19 Acrian, Inc. Method of fabrication lateral FET structure having a substrate to source contact
US5098854A (en) * 1984-07-09 1992-03-24 National Semiconductor Corporation Process for forming self-aligned silicide base contact for bipolar transistor
JPH0611053B2 (ja) * 1984-12-20 1994-02-09 三菱電機株式会社 半導体装置の製造方法
US5227316A (en) * 1985-01-22 1993-07-13 National Semiconductor Corporation Method of forming self aligned extended base contact for a bipolar transistor having reduced cell size
GB8507624D0 (en) * 1985-03-23 1985-05-01 Standard Telephones Cables Ltd Semiconductor devices
EP0216945B1 (fr) * 1985-09-21 1989-07-05 Deutsche ITT Industries GmbH Procédé pour appliquer un contact sur une plage de contact d'un substrat semi-conducteur
US4898838A (en) * 1985-10-16 1990-02-06 Texas Instruments Incorporated Method for fabricating a poly emitter logic array
US4755476A (en) * 1985-12-17 1988-07-05 Siemens Aktiengesellschaft Process for the production of self-adjusted bipolar transistor structures having a reduced extrinsic base resistance
GB2188479B (en) * 1986-03-26 1990-05-23 Stc Plc Semiconductor devices
US5063168A (en) * 1986-07-02 1991-11-05 National Semiconductor Corporation Process for making bipolar transistor with polysilicon stringer base contact
US4974046A (en) * 1986-07-02 1990-11-27 National Seimconductor Corporation Bipolar transistor with polysilicon stringer base contact
US4883772A (en) * 1986-09-11 1989-11-28 National Semiconductor Corporation Process for making a self-aligned silicide shunt
US5437940A (en) * 1986-10-14 1995-08-01 Westinghouse Electric Corporation High power energy compression device
US4933295A (en) * 1987-05-08 1990-06-12 Raytheon Company Method of forming a bipolar transistor having closely spaced device regions
US4803175A (en) * 1987-09-14 1989-02-07 Motorola Inc. Method of fabricating a bipolar semiconductor device with silicide contacts
JPH01123417A (ja) * 1987-11-07 1989-05-16 Mitsubishi Electric Corp 半導体装置の製造方法
US5064773A (en) * 1988-12-27 1991-11-12 Raytheon Company Method of forming bipolar transistor having closely spaced device regions
US5066616A (en) * 1989-06-14 1991-11-19 Hewlett-Packard Company Method for improving photoresist on wafers by applying fluid layer of liquid solvent
US5089429A (en) * 1989-06-22 1992-02-18 David Sarnoff Research Center, Inc. Self-aligned emitter bicmos process
JPH0362568A (ja) * 1989-07-31 1991-03-18 Hitachi Ltd 半導体装置の製造方法
US5226232A (en) * 1990-05-18 1993-07-13 Hewlett-Packard Company Method for forming a conductive pattern on an integrated circuit
GB2244176B (en) * 1990-05-18 1994-10-05 Hewlett Packard Co Method and apparatus for forming a conductive pattern on an integrated circuit
DE4032411A1 (de) * 1990-10-12 1992-04-16 Daimler Benz Ag Verfahren zur herstellung von t-gate-elektroden
US5451532A (en) * 1994-03-15 1995-09-19 National Semiconductor Corp. Process for making self-aligned polysilicon base contact in a bipolar junction transistor
US5397722A (en) * 1994-03-15 1995-03-14 National Semiconductor Corporation Process for making self-aligned source/drain polysilicon or polysilicide contacts in field effect transistors
US6471878B1 (en) * 1994-08-30 2002-10-29 Gordion Holding Corporation Method for forming a radio frequency responsive target and apparatus for verifying the authenticity of same
GB2320134A (en) * 1996-12-04 1998-06-10 United Microelectronics Corp Salicide electrodes for semiconductor devices
JPH10270451A (ja) * 1997-03-25 1998-10-09 Rohm Co Ltd 半導体装置およびその製造方法
JP3886712B2 (ja) * 2000-09-08 2007-02-28 シャープ株式会社 半導体装置の製造方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL149638B (nl) * 1966-04-14 1976-05-17 Philips Nv Werkwijze voor het vervaardigen van een halfgeleiderinrichting bevattende ten minste een veldeffecttransistor, en halfgeleiderinrichting, vervaardigd volgens deze werkwijze.
DE2149705A1 (de) * 1970-10-06 1972-04-13 Motorola Inc Halbleiteranordnung und Verfahren zu ihrer Herstellung
JPS5329989B2 (fr) * 1971-10-22 1978-08-24
JPS5116312A (ja) * 1974-07-10 1976-02-09 Takahama Industry Wagawaraseikeikiheno sojikyokyusochi
US4016587A (en) * 1974-12-03 1977-04-05 International Business Machines Corporation Raised source and drain IGFET device and method
US4057820A (en) * 1976-06-29 1977-11-08 Westinghouse Electric Corporation Dual gate MNOS transistor

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0054259A2 (fr) * 1980-12-12 1982-06-23 Kabushiki Kaisha Toshiba Procédé de fabrication d'un dispositif semiconducteur du type MIS
EP0054259A3 (en) * 1980-12-12 1983-08-17 Tokyo Shibaura Denki Kabushiki Kaisha Method of manufacturing a semiconductor device of the mis type
US4622735A (en) * 1980-12-12 1986-11-18 Tokyo Shibaura Denki Kabushiki Kaisha Method for manufacturing a semiconductor device utilizing self-aligned silicide regions
US4830971A (en) * 1980-12-12 1989-05-16 Tokyo Shibaura Denki Kabushiki Kaisha Method for manufacturing a semiconductor device utilizing self-aligned contact regions
EP0199061A2 (fr) * 1985-03-23 1986-10-29 Itt Industries, Inc. Dispositif semi-conducteur
EP0202727A2 (fr) * 1985-03-23 1986-11-26 Northern Telecom Europe Limited Dispositif semi-conducteur
EP0202727A3 (en) * 1985-03-23 1988-03-23 Stc Plc Semiconductor devices
EP0199061A3 (fr) * 1985-03-23 1988-03-30 Itt Industries, Inc. Dispositif semi-conducteur
US4916517A (en) * 1985-03-23 1990-04-10 Stc, Plc Semiconductor devices

Also Published As

Publication number Publication date
NL190255B (nl) 1993-07-16
FR2358750B1 (fr) 1983-03-25
NL7707919A (nl) 1978-01-17
JPS5515868B2 (fr) 1980-04-26
NL190255C (nl) 1993-12-16
GB1567808A (en) 1980-05-21
CA1085969A (fr) 1980-09-16
DE2732184C2 (de) 1986-11-27
US4188707A (en) 1980-02-19
DE2732184A1 (de) 1978-01-26
JPS539469A (en) 1978-01-27

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