FR2358725A1 - Circuit de memoire a cellules a un transistor par bit - Google Patents
Circuit de memoire a cellules a un transistor par bitInfo
- Publication number
- FR2358725A1 FR2358725A1 FR7721355A FR7721355A FR2358725A1 FR 2358725 A1 FR2358725 A1 FR 2358725A1 FR 7721355 A FR7721355 A FR 7721355A FR 7721355 A FR7721355 A FR 7721355A FR 2358725 A1 FR2358725 A1 FR 2358725A1
- Authority
- FR
- France
- Prior art keywords
- memory circuit
- per bit
- group
- memory
- transistor per
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
- G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
- G11C11/404—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Dram (AREA)
- Semiconductor Memories (AREA)
- Read Only Memory (AREA)
- Static Random-Access Memory (AREA)
Abstract
La présente invention concerne un circuit de mémoire à cellules à un transistor par bit. Dans un tel circuit de mémoire comprenant des cellules de mémoire 10 utilisées en deux groupes de rangées 30 et 40, il est classiquement prévu des amplificateurs différentiels 12 ayant une première entrée 1 connectée aux cellules de mémoire du groupe 30 et une seconde entrée 2 connectée aux cellules de mémoire du groupe 40. Un tel circuit comprend un amplificateur de sortie 14, dont classiquement l'une des entrées 3 était connectée à un potentiel de reférence. Selon la présente invention, cette borne d'entrée 3 est connectée aux cellules du second groupe par l'intermédiaire de moyens de connexion 20' commandés par les mêmes signaux de commande que ceux qui commandaient les moyens de connexion 20 classiques. Application à l'augmentation de vitesse des circuits de mémoire.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8269376A JPS538528A (en) | 1976-07-12 | 1976-07-12 | Memory circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2358725A1 true FR2358725A1 (fr) | 1978-02-10 |
FR2358725B1 FR2358725B1 (fr) | 1984-05-18 |
Family
ID=13781482
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR7721355A Granted FR2358725A1 (fr) | 1976-07-12 | 1977-07-11 | Circuit de memoire a cellules a un transistor par bit |
Country Status (5)
Country | Link |
---|---|
US (1) | US4125878A (fr) |
JP (1) | JPS538528A (fr) |
DE (2) | DE2760030C2 (fr) |
FR (1) | FR2358725A1 (fr) |
GB (1) | GB1555043A (fr) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0222396A1 (fr) * | 1985-11-15 | 1987-05-20 | Kabushiki Kaisha Toshiba | Dispositif de transistors à effet de champ |
Families Citing this family (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4239993A (en) * | 1978-09-22 | 1980-12-16 | Texas Instruments Incorporated | High performance dynamic sense amplifier with active loads |
US4370575A (en) * | 1978-09-22 | 1983-01-25 | Texas Instruments Incorporated | High performance dynamic sense amplifier with active loads |
FR2442488A1 (fr) * | 1978-11-22 | 1980-06-20 | Cii Honeywell Bull | Dispositif d'extraction et re-ecriture de l'information pour une memoire a rafraichissement |
DE2855118C2 (de) * | 1978-12-20 | 1981-03-26 | IBM Deutschland GmbH, 70569 Stuttgart | Dynamischer FET-Speicher |
JPS59915B2 (ja) * | 1979-11-29 | 1984-01-09 | 富士通株式会社 | メモリ回路 |
JPS56101694A (en) * | 1980-01-18 | 1981-08-14 | Nec Corp | Semiconductor circuit |
JPS57164491A (en) * | 1981-04-02 | 1982-10-09 | Nec Corp | Semiconductor device |
USRE34060E (en) * | 1981-06-01 | 1992-09-08 | Hitachi, Ltd. | High speed semiconductor memory device having a high gain sense amplifier |
JPS57198594A (en) * | 1981-06-01 | 1982-12-06 | Hitachi Ltd | Semiconductor storage device |
JPS57172588A (en) * | 1981-07-24 | 1982-10-23 | Nec Corp | Memory circuit |
US4555776A (en) * | 1982-04-19 | 1985-11-26 | International Business Machines Corporation | Voltage balancing circuit for memory systems |
US4493056A (en) * | 1982-06-30 | 1985-01-08 | International Business Machines Corporation | RAM Utilizing offset contact regions for increased storage capacitance |
US4723228B1 (en) * | 1983-08-31 | 1998-04-21 | Texas Instruments Inc | Memory decoding circuitry |
JPH0795395B2 (ja) * | 1984-02-13 | 1995-10-11 | 株式会社日立製作所 | 半導体集積回路 |
JPS61110394A (ja) * | 1984-10-31 | 1986-05-28 | Mitsubishi Electric Corp | 半導体記憶装置 |
US5197033A (en) * | 1986-07-18 | 1993-03-23 | Hitachi, Ltd. | Semiconductor device incorporating internal power supply for compensating for deviation in operating condition and fabrication process conditions |
US4740921A (en) * | 1985-10-04 | 1988-04-26 | Motorola, Inc. | Precharge of a dram data line to an intermediate voltage |
US4710902A (en) * | 1985-10-04 | 1987-12-01 | Motorola, Inc. | Technique restore for a dynamic random access memory |
KR890003373B1 (ko) * | 1986-11-30 | 1989-09-19 | 삼성전자 주식회사 | 씨모오스 반도체 메모리 장치의 입출력 회로 |
GB8917835D0 (en) * | 1989-08-04 | 1989-09-20 | Inmos Ltd | Current sensing amplifier for a memory |
JPH02236893A (ja) * | 1990-02-23 | 1990-09-19 | Hitachi Ltd | 半導体メモリ装置 |
EP0496406B1 (fr) * | 1991-01-25 | 1999-05-06 | Nec Corporation | Dispositif de mémoire à semi-conducteurs |
JP3085803B2 (ja) * | 1992-11-26 | 2000-09-11 | 株式会社東芝 | 差動電流源回路 |
DE4343852C1 (de) * | 1993-12-22 | 1995-05-24 | Itt Ind Gmbh Deutsche | Verfahren zum Betrieb eines Leseverstärkers und Leseverstärker zur Durchführung des Verfahrens |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3678473A (en) * | 1970-06-04 | 1972-07-18 | Shell Oil Co | Read-write circuit for capacitive memory arrays |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3760381A (en) * | 1972-06-30 | 1973-09-18 | Ibm | Stored charge memory detection circuit |
US3838295A (en) * | 1973-02-05 | 1974-09-24 | Lockheed Electronics Co | Ratioless mos sense amplifier |
JPS5079224A (fr) * | 1973-11-12 | 1975-06-27 | ||
JPS5539073B2 (fr) * | 1974-12-25 | 1980-10-08 | ||
US4061999A (en) * | 1975-12-29 | 1977-12-06 | Mostek Corporation | Dynamic random access memory system |
-
1976
- 1976-07-12 JP JP8269376A patent/JPS538528A/ja active Pending
-
1977
- 1977-07-11 US US05/814,849 patent/US4125878A/en not_active Expired - Lifetime
- 1977-07-11 FR FR7721355A patent/FR2358725A1/fr active Granted
- 1977-07-12 DE DE2760030A patent/DE2760030C2/de not_active Expired
- 1977-07-12 GB GB29266/77A patent/GB1555043A/en not_active Expired
- 1977-07-12 DE DE2731442A patent/DE2731442C2/de not_active Expired
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3678473A (en) * | 1970-06-04 | 1972-07-18 | Shell Oil Co | Read-write circuit for capacitive memory arrays |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0222396A1 (fr) * | 1985-11-15 | 1987-05-20 | Kabushiki Kaisha Toshiba | Dispositif de transistors à effet de champ |
US5175604A (en) * | 1985-11-15 | 1992-12-29 | Kabushiki Kaisha Toshiba | Field-effect transistor device |
Also Published As
Publication number | Publication date |
---|---|
DE2760030C2 (de) | 1986-04-03 |
US4125878A (en) | 1978-11-14 |
GB1555043A (en) | 1979-11-07 |
DE2731442A1 (de) | 1978-01-19 |
DE2731442C2 (de) | 1990-05-10 |
JPS538528A (en) | 1978-01-26 |
FR2358725B1 (fr) | 1984-05-18 |
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