FR2275880A1 - Procede perfectionne pour la fabrication d'une structure a transistors a effet de champ a porte isolee - Google Patents
Procede perfectionne pour la fabrication d'une structure a transistors a effet de champ a porte isoleeInfo
- Publication number
- FR2275880A1 FR2275880A1 FR7516973A FR7516973A FR2275880A1 FR 2275880 A1 FR2275880 A1 FR 2275880A1 FR 7516973 A FR7516973 A FR 7516973A FR 7516973 A FR7516973 A FR 7516973A FR 2275880 A1 FR2275880 A1 FR 2275880A1
- Authority
- FR
- France
- Prior art keywords
- manufacture
- field
- effect transistor
- transistor structure
- insulated door
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000005669 field effect Effects 0.000 title 1
- 238000004519 manufacturing process Methods 0.000 title 1
- 238000000034 method Methods 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
- H01L21/76216—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers
- H01L21/76218—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers introducing both types of electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers, e.g. for isolation of complementary doped regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/113—Nitrides of boron or aluminum or gallium
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/114—Nitrides of silicon
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/141—Self-alignment coat gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Local Oxidation Of Silicon (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US475357A US3920481A (en) | 1974-06-03 | 1974-06-03 | Process for fabricating insulated gate field effect transistor structure |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2275880A1 true FR2275880A1 (fr) | 1976-01-16 |
FR2275880B1 FR2275880B1 (fr) | 1981-08-21 |
Family
ID=23887217
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR7516973A Granted FR2275880A1 (fr) | 1974-06-03 | 1975-05-30 | Procede perfectionne pour la fabrication d'une structure a transistors a effet de champ a porte isolee |
Country Status (9)
Country | Link |
---|---|
US (1) | US3920481A (fr) |
JP (1) | JPS515970A (fr) |
CA (1) | CA1013866A (fr) |
DE (1) | DE2524263C2 (fr) |
FR (1) | FR2275880A1 (fr) |
GB (1) | GB1502668A (fr) |
HK (1) | HK28081A (fr) |
IT (1) | IT1032952B (fr) |
NL (1) | NL185882C (fr) |
Families Citing this family (27)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4203126A (en) * | 1975-11-13 | 1980-05-13 | Siliconix, Inc. | CMOS structure and method utilizing retarded electric field for minimum latch-up |
JPS5284981A (en) * | 1976-01-06 | 1977-07-14 | Mitsubishi Electric Corp | Production of insulated gate type semiconductor device |
JPS5286083A (en) * | 1976-01-12 | 1977-07-16 | Hitachi Ltd | Production of complimentary isolation gate field effect transistor |
GB1521955A (en) * | 1976-03-16 | 1978-08-23 | Tokyo Shibaura Electric Co | Semiconductor memory device |
US4072868A (en) * | 1976-09-16 | 1978-02-07 | International Business Machines Corporation | FET inverter with isolated substrate load |
US4205330A (en) * | 1977-04-01 | 1980-05-27 | National Semiconductor Corporation | Method of manufacturing a low voltage n-channel MOSFET device |
JPS5626471A (en) * | 1979-08-10 | 1981-03-14 | Matsushita Electric Ind Co Ltd | Mos type semiconductor device |
DE3133841A1 (de) * | 1981-08-27 | 1983-03-17 | Siemens AG, 1000 Berlin und 8000 München | Verfahren zum herstellen von hochintegrierten komplementaeren mos-feldeffekttransistorschaltungen |
US4406710A (en) * | 1981-10-15 | 1983-09-27 | Davies Roderick D | Mask-saving technique for forming CMOS source/drain regions |
US4420344A (en) * | 1981-10-15 | 1983-12-13 | Texas Instruments Incorporated | CMOS Source/drain implant process without compensation of polysilicon doping |
US4454648A (en) * | 1982-03-08 | 1984-06-19 | Mcdonnell Douglas Corporation | Method of making integrated MNOS and CMOS devices in a bulk silicon wafer |
US4412375A (en) * | 1982-06-10 | 1983-11-01 | Intel Corporation | Method for fabricating CMOS devices with guardband |
JPS5965481A (ja) * | 1982-10-06 | 1984-04-13 | Nec Corp | 半導体装置 |
US4462151A (en) * | 1982-12-03 | 1984-07-31 | International Business Machines Corporation | Method of making high density complementary transistors |
JPH0636425B2 (ja) * | 1983-02-23 | 1994-05-11 | テキサス インスツルメンツ インコ−ポレイテツド | Cmos装置の製造方法 |
US4527325A (en) * | 1983-12-23 | 1985-07-09 | International Business Machines Corporation | Process for fabricating semiconductor devices utilizing a protective film during high temperature annealing |
US4753897A (en) * | 1986-03-14 | 1988-06-28 | Motorola Inc. | Method for providing contact separation in silicided devices using false gate |
US4908688A (en) * | 1986-03-14 | 1990-03-13 | Motorola, Inc. | Means and method for providing contact separation in silicided devices |
JPS6364844U (fr) * | 1986-10-17 | 1988-04-28 | ||
US5679968A (en) * | 1990-01-31 | 1997-10-21 | Texas Instruments Incorporated | Transistor having reduced hot carrier implantation |
US5091332A (en) * | 1990-11-19 | 1992-02-25 | Intel Corporation | Semiconductor field oxidation process |
EP0764980A1 (fr) * | 1995-09-20 | 1997-03-26 | Lucent Technologies Inc. | Amélioration de l'oxydation localisée de silicium |
KR100213201B1 (ko) * | 1996-05-15 | 1999-08-02 | 윤종용 | 씨모스 트랜지스터 및 그 제조방법 |
KR100876927B1 (ko) * | 2001-06-01 | 2009-01-07 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 열처리장치 및 열처리방법 |
US7419863B1 (en) * | 2005-08-29 | 2008-09-02 | National Semiconductor Corporation | Fabrication of semiconductor structure in which complementary field-effect transistors each have hypoabrupt body dopant distribution below at least one source/drain zone |
US8779509B2 (en) | 2012-07-02 | 2014-07-15 | Infineon Technologies Austria Ag | Semiconductor device including an edge area and method of manufacturing a semiconductor device |
CN116225135B (zh) * | 2023-05-11 | 2023-07-21 | 上海海栎创科技股份有限公司 | 一种低压差线性稳压器 |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE1104070B (de) * | 1959-01-27 | 1961-04-06 | Siemens Ag | Verfahren zur Herstellung einer eine eigenleitende oder nahezu eigenleitende Zone aufweisenden Halbleitertriode |
US3356858A (en) * | 1963-06-18 | 1967-12-05 | Fairchild Camera Instr Co | Low stand-by power complementary field effect circuitry |
US3411051A (en) * | 1964-12-29 | 1968-11-12 | Texas Instruments Inc | Transistor with an isolated region having a p-n junction extending from the isolation wall to a surface |
GB1280022A (en) * | 1968-08-30 | 1972-07-05 | Mullard Ltd | Improvements in and relating to semiconductor devices |
US3631312A (en) * | 1969-05-15 | 1971-12-28 | Nat Semiconductor Corp | High-voltage mos transistor method and apparatus |
US3812519A (en) * | 1970-02-07 | 1974-05-21 | Tokyo Shibaura Electric Co | Silicon double doped with p and as or b and as |
NL170348C (nl) * | 1970-07-10 | 1982-10-18 | Philips Nv | Werkwijze voor het vervaardigen van een halfgeleiderinrichting, waarbij op een oppervlak van een halfgeleiderlichaam een tegen dotering en tegen thermische oxydatie maskerend masker wordt aangebracht, de door de vensters in het masker vrijgelaten delen van het oppervlak worden onderworpen aan een etsbehandeling voor het vormen van verdiepingen en het halfgeleiderlichaam met het masker wordt onderworpen aan een thermische oxydatiebehandeling voor het vormen van een oxydepatroon dat de verdiepingen althans ten dele opvult. |
US3648125A (en) * | 1971-02-02 | 1972-03-07 | Fairchild Camera Instr Co | Method of fabricating integrated circuits with oxidized isolation and the resulting structure |
NL160988C (nl) * | 1971-06-08 | 1979-12-17 | Philips Nv | Halfgeleiderinrichting met een halfgeleiderlichaam, be- vattende ten minste een eerste veldeffecttransistor met geisoleerde stuurelektrode en werkwijze voor de vervaar- diging van de halfgeleiderinrichting. |
US3806371A (en) * | 1971-07-28 | 1974-04-23 | Motorola Inc | Method of making complementary monolithic insulated gate field effect transistors having low threshold voltage and low leakage current |
DE2247975C3 (de) * | 1972-09-29 | 1979-11-15 | Siemens Ag, 1000 Berlin Und 8000 Muenchen | Verfahren zur Herstellung von Dünnschicht-Schaltungen mit komplementären MOS-Transistoren |
US3793088A (en) * | 1972-11-15 | 1974-02-19 | Bell Telephone Labor Inc | Compatible pnp and npn devices in an integrated circuit |
-
1974
- 1974-06-03 US US475357A patent/US3920481A/en not_active Expired - Lifetime
-
1975
- 1975-05-06 CA CA226,397A patent/CA1013866A/en not_active Expired
- 1975-05-19 GB GB21106/75A patent/GB1502668A/en not_active Expired
- 1975-05-21 IT IT68320/75A patent/IT1032952B/it active
- 1975-05-30 FR FR7516973A patent/FR2275880A1/fr active Granted
- 1975-05-31 DE DE2524263A patent/DE2524263C2/de not_active Expired
- 1975-06-02 NL NLAANVRAGE7506519,A patent/NL185882C/xx not_active IP Right Cessation
- 1975-06-02 JP JP50065452A patent/JPS515970A/ja active Pending
-
1981
- 1981-06-25 HK HK280/81A patent/HK28081A/xx unknown
Also Published As
Publication number | Publication date |
---|---|
HK28081A (en) | 1981-07-03 |
JPS515970A (fr) | 1976-01-19 |
GB1502668A (en) | 1978-03-01 |
DE2524263C2 (de) | 1985-06-27 |
US3920481A (en) | 1975-11-18 |
FR2275880B1 (fr) | 1981-08-21 |
NL7506519A (nl) | 1975-12-05 |
CA1013866A (en) | 1977-07-12 |
IT1032952B (it) | 1979-06-20 |
NL185882C (nl) | 1990-08-01 |
DE2524263A1 (de) | 1975-12-11 |
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