ES2122158T3 - Metodo para formar contactos con regiones de fuentes y drenadores. - Google Patents
Metodo para formar contactos con regiones de fuentes y drenadores.Info
- Publication number
- ES2122158T3 ES2122158T3 ES94300406T ES94300406T ES2122158T3 ES 2122158 T3 ES2122158 T3 ES 2122158T3 ES 94300406 T ES94300406 T ES 94300406T ES 94300406 T ES94300406 T ES 94300406T ES 2122158 T3 ES2122158 T3 ES 2122158T3
- Authority
- ES
- Spain
- Prior art keywords
- substrate
- layer
- sources
- drainers
- regions
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000000758 substrate Substances 0.000 abstract 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract 1
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 239000011248 coating agent Substances 0.000 abstract 1
- 238000000576 coating method Methods 0.000 abstract 1
- 239000004020 conductor Substances 0.000 abstract 1
- 238000004519 manufacturing process Methods 0.000 abstract 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract 1
- 229920005591 polysilicon Polymers 0.000 abstract 1
- 229910021332 silicide Inorganic materials 0.000 abstract 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 abstract 1
- 229910052710 silicon Inorganic materials 0.000 abstract 1
- 239000010703 silicon Substances 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
- H01L21/76889—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances by forming silicides of refractory metals
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28525—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising semiconducting material
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Memories (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
SE DESCRIBE UN METODO DE FABRICACION SEMICONDUCTORA QUE SE PUEDE APLICAR A LA FORMACION DE CONTACTOS A FUENTES Y DESAGUES, ESPECIALMENTE EN APLICACIONES SRAM. SE FORMAN UN DIELECTRICO (POR EJEMPLO 127) Y UN CONDUCTOR DE POLISILICIO DE RECUBRIMIENTO (POR EJEMPLO 131) Y SE MODELAN EXPONIENDO UN SUSTRATO SEMICONDUCTOR (POR EJEMPLO 123). SE DEPOSITA UNA CAPA DE SILICIURO (POR EJEMPLO 132), ESTABLECIENDO CONTACTO ASI CON LA CAPA DE POLISILICIO (POR EJEMPLO 131), Y EL SUSTRATO (POR EJEMPLO 123). LA POSTERIOR MODELACION DE LA CAPA DE SILICIO (POR EJEMPLO 132) USANDO UNA MASCARA DURA DE OXIDO PROPORCIONA CONTACTO ELECTRICO ENTRE LA CAPA DE POLISILICIO (POR EJEMPLO 131) Y EL SUSTRATO, SIN PELIGRO DE HACER SURCOS DENTRO DEL SUSTRATO (POR EJEMPLO 123).
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US98721393A | 1993-01-26 | 1993-01-26 |
Publications (1)
Publication Number | Publication Date |
---|---|
ES2122158T3 true ES2122158T3 (es) | 1998-12-16 |
Family
ID=25533110
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
ES94300406T Expired - Lifetime ES2122158T3 (es) | 1993-01-26 | 1994-01-19 | Metodo para formar contactos con regiones de fuentes y drenadores. |
Country Status (7)
Country | Link |
---|---|
US (1) | US5654240A (es) |
EP (1) | EP0609014B1 (es) |
JP (1) | JPH06318682A (es) |
KR (1) | KR100311059B1 (es) |
DE (1) | DE69413861T2 (es) |
ES (1) | ES2122158T3 (es) |
TW (1) | TW230266B (es) |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5843815A (en) * | 1997-01-15 | 1998-12-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for fabricating a MOSFET device, for an SRAM cell, using a self-aligned ion implanted halo region |
US6043129A (en) * | 1997-06-09 | 2000-03-28 | Integrated Device Technology, Inc. | High density MOSFET with raised source and drain regions |
US6063676A (en) * | 1997-06-09 | 2000-05-16 | Integrated Device Technology, Inc. | Mosfet with raised source and drain regions |
US6562724B1 (en) * | 1997-06-09 | 2003-05-13 | Texas Instruments Incorporated | Self-aligned stack formation |
US5949143A (en) * | 1998-01-22 | 1999-09-07 | Advanced Micro Devices, Inc. | Semiconductor interconnect structure with air gap for reducing intralayer capacitance in metal layers in damascene metalization process |
US6103455A (en) * | 1998-05-07 | 2000-08-15 | Taiwan Semiconductor Manufacturing Company | Method to form a recess free deep contact |
US6117754A (en) * | 1998-05-11 | 2000-09-12 | Texas Instruments - Acer Incorporated | Trench free process for SRAM with buried contact structure |
US6007733A (en) * | 1998-05-29 | 1999-12-28 | Taiwan Semiconductor Manufacturing Company | Hard masking method for forming oxygen containing plasma etchable layer |
US6019906A (en) * | 1998-05-29 | 2000-02-01 | Taiwan Semiconductor Manufacturing Company | Hard masking method for forming patterned oxygen containing plasma etchable layer |
US6492276B1 (en) | 1998-05-29 | 2002-12-10 | Taiwan Semiconductor Manufacturing Company | Hard masking method for forming residue free oxygen containing plasma etched layer |
US6165898A (en) * | 1998-10-23 | 2000-12-26 | Taiwan Semiconductor Manufacturing Company | Dual damascene patterned conductor layer formation method without etch stop layer |
US6429124B1 (en) | 1999-04-14 | 2002-08-06 | Micron Technology, Inc. | Local interconnect structures for integrated circuits and methods for making the same |
Family Cites Families (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4288256A (en) * | 1977-12-23 | 1981-09-08 | International Business Machines Corporation | Method of making FET containing stacked gates |
NL186352C (nl) * | 1980-08-27 | 1990-11-01 | Philips Nv | Werkwijze ter vervaardiging van een halfgeleiderinrichting. |
EP0192093B1 (en) * | 1985-01-30 | 1990-06-13 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the same |
US4994402A (en) * | 1987-06-26 | 1991-02-19 | Hewlett-Packard Company | Method of fabricating a coplanar, self-aligned contact structure in a semiconductor device |
KR900008868B1 (ko) * | 1987-09-30 | 1990-12-11 | 삼성전자 주식회사 | 저항성 접촉을 갖는 반도체 장치의 제조방법 |
US5210048A (en) * | 1988-10-19 | 1993-05-11 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device with offset transistor and method for manufacturing the same |
US5110753A (en) * | 1988-11-10 | 1992-05-05 | Texas Instruments Incorporated | Cross-point contact-free floating-gate memory array with silicided buried bitlines |
US5162262A (en) * | 1989-03-14 | 1992-11-10 | Mitsubishi Denki Kabushiki Kaisha | Multi-layered interconnection structure for a semiconductor device and manufactured method thereof |
US4978637A (en) * | 1989-05-31 | 1990-12-18 | Sgs-Thomson Microelectronics, Inc. | Local interconnect process for integrated circuits |
US5151387A (en) * | 1990-04-30 | 1992-09-29 | Sgs-Thomson Microelectronics, Inc. | Polycrystalline silicon contact structure |
JPH04179239A (ja) * | 1990-11-14 | 1992-06-25 | Sony Corp | 半導体装置の製造方法 |
US5124280A (en) * | 1991-01-31 | 1992-06-23 | Sgs-Thomson Microelectronics, Inc. | Local interconnect for integrated circuits |
FR2677481B1 (fr) * | 1991-06-07 | 1993-08-20 | Commissariat Energie Atomique | Procede de fabrication d'une cellule de memoire non volatile et cellule de memoire obtenue. |
US5149665A (en) * | 1991-07-10 | 1992-09-22 | Micron Technology, Inc. | Conductive source line for high density programmable read-only memory applications |
US5270240A (en) * | 1991-07-10 | 1993-12-14 | Micron Semiconductor, Inc. | Four poly EPROM process and structure comprising a conductive source line structure and self-aligned polycrystalline silicon digit lines |
KR940010315B1 (ko) * | 1991-10-10 | 1994-10-22 | 금성 일렉트론 주식회사 | 반도체 소자의 미세 패턴 형성 방법 |
US5246883A (en) * | 1992-02-06 | 1993-09-21 | Sgs-Thomson Microelectronics, Inc. | Semiconductor contact via structure and method |
-
1993
- 1993-12-06 TW TW082110302A patent/TW230266B/zh not_active IP Right Cessation
-
1994
- 1994-01-19 EP EP94300406A patent/EP0609014B1/en not_active Expired - Lifetime
- 1994-01-19 ES ES94300406T patent/ES2122158T3/es not_active Expired - Lifetime
- 1994-01-19 DE DE69413861T patent/DE69413861T2/de not_active Expired - Fee Related
- 1994-01-25 KR KR1019940001235A patent/KR100311059B1/ko not_active IP Right Cessation
- 1994-01-26 JP JP6006698A patent/JPH06318682A/ja active Pending
-
1996
- 1996-04-12 US US08/635,226 patent/US5654240A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
EP0609014B1 (en) | 1998-10-14 |
JPH06318682A (ja) | 1994-11-15 |
KR100311059B1 (ko) | 2001-12-15 |
EP0609014A3 (en) | 1995-01-04 |
TW230266B (es) | 1994-09-11 |
EP0609014A2 (en) | 1994-08-03 |
DE69413861D1 (de) | 1998-11-19 |
US5654240A (en) | 1997-08-05 |
DE69413861T2 (de) | 1999-04-22 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
FG2A | Definitive protection |
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