Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
  • H01L23/64—Impedance arrangements
  • H01L23/66—High-frequency adaptations
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
  • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
  • H01L23/3157—Partial encapsulation or coating
  • H01L23/3164—Partial encapsulation or coating the coating being a foil
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
  • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
  • H01L2224/10—Bump connectors; Manufacturing methods related thereto
  • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
  • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
  • H01L2224/161—Disposition
  • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
  • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
  • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/01—Chemical elements
  • H01L2924/01004—Beryllium [Be]
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/01—Chemical elements
  • H01L2924/0102—Calcium [Ca]
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/01—Chemical elements
  • H01L2924/01068—Erbium [Er]
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/01—Chemical elements
  • H01L2924/01078—Platinum [Pt]
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/01—Chemical elements
  • H01L2924/01079—Gold [Au]
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
  • H01L2924/097—Glass-ceramics, e.g. devitrified glass
  • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/10—Details of semiconductor or other solid state devices to be connected
  • H01L2924/102—Material of the semiconductor or solid state bodies
  • H01L2924/1025—Semiconducting materials
  • H01L2924/10251—Elemental semiconductors, i.e. Group IV
  • H01L2924/10253—Silicon [Si]
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
  • H01L2924/151—Die mounting substrate
  • H01L2924/153—Connection portion
  • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
  • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
  • H01L2924/151—Die mounting substrate
  • H01L2924/153—Connection portion
  • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
  • H01L2924/191—Disposition
  • H01L2924/19101—Disposition of discrete passive components
  • H01L2924/19106—Disposition of discrete passive components in a mirrored arrangement on two different side of a common die mounting substrate
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/30—Technical effects
  • H01L2924/301—Electrical effects
  • H01L2924/3025—Electromagnetic shielding
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
  • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
  • Y10T29/00—Metal working
  • Y10T29/49—Method of mechanical manufacture
  • Y10T29/49002—Electrical device making
  • Y10T29/49117—Conductor or circuit manufacturing
  • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
  • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
  • Y10T29/49144—Assembling to base an electrical component, e.g., capacitor, etc. by metal fusion
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
  • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
  • Y10T29/00—Metal working
  • Y10T29/49—Method of mechanical manufacture
  • Y10T29/49002—Electrical device making
  • Y10T29/49117—Conductor or circuit manufacturing
  • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
  • Y10T29/49155—Manufacturing circuit on or in base

Definitions

• hermetically sealed high-frequency packages for modules mainly consist of milled metal housings, which are gold-plated and then sealed with a soldered-on metal cover.
• Hermetic single-component ceramic housings, such as those used for OF components, are also expensive and less suitable for components with high power dissipation.
• Usual HF metal housings as they are often used for modules, if no hermeticity but good shielding is necessary, are very expensive, very large and not hermetically sealed.
• RF module housings based on the latest LTCC technology are also expensive.
• the ceramic only serves to guide the cable while the cover is being soldered on.
• Typical OF filter housings which are based on HTCC technology, are roll seam welded and can be used up to approx. 5 GHz for components without high power dissipation.
• the cover welding is complex and the housings can only be used for a limited frequency range.
• DE 100 41 770 A1 discloses a substrate with a first dielectric layer, a high-frequency structure layer, which contains a high-frequency distribution network, and at least one low-frequency structure layer.
• a module thus formed also includes a cover.
• From WO 97/45955 AI, WO 99/43084 AI, DE 195 48 048 AI and DE 198 18 824 AI electronic components located on circuit carriers are known, which are covered with covers, in particular in the form of foils. Metal foils used here have proven to be very difficult to handle and often have not proven to be long-term.
• the object of the invention is to specify an inexpensive method for producing a high-frequency package.
• a circuit carrier is connected to a component via contacts which space the component from the circuit carrier, so that cavities are formed between the component, the circuit carrier and the contacts.
• a film is applied to the component and the circuit carrier in such a way that it lies closely against the surface of the circuit carrier on which the component is located and on the sides of the component not facing the circuit carrier. After it has been applied to the component and the circuit carrier, the film is provided with a metallization.
• the metallization is preferably applied by sputtering or vapor deposition and then galvanically reinforced.
• a window can be opened in the film on the side of the component facing away from the circuit carrier, through which window the component can be contacted. If the window is opened before the film is metallized, the contact can be made immediately by the metallization.
• a solder bump is applied to the side of the circuit carrier on which the component is attached. This solder bump projects above the component in that it is higher than the component when viewed from the circuit carrier.
• the package consisting of circuit carrier, component, foil and metallization of the foil on the side on which the component is arranged on the circuit carrier can be electrically connected to, for example, another circuit carrier via the solder bump.
• the component is in particular an active component, a high-frequency component and / or a high-frequency component.
• one or more passive components can also be arranged on the circuit carrier.
• the passive components are preferably arranged on the side of the circuit carrier opposite the component.
• FIG. 1 shows a circuit carrier equipped on one side with screen-printed solder bumps on the rear of the circuit carrier
• Figure 2 shows a double-sided circuit carrier with attached solder balls or solder bumps on the front of the circuit carrier and a surface-mounted passive component on the back of the circuit carrier.
• Components 1 in the form of chips are bumped and, in the case of printed contacts 2 in the form of solder bumps, these are remelted.
• a circuit carrier 3 can also be bumped.
• the components 1 are separated, dipped upside down with the contacts 2 into flux and placed on connection pads of the circuit carrier 3, for example made of ceramic. This creates cavities 4 between the component 1, the contacts 2 and the circuit carrier 3.
• a film 5 is laminated over the entire surface of the components 1 and removed at contact points and on the module edges (saw marks), for example by means of a laser.
• the film 5 is provided with a metallization 6, for example by means of Cu sputtering, which is optionally galvanically reinforced.
• one or more frames 12 run in the form of metallizations on the ceramic on which the film 5 has been removed.
• the metal shielding stretched over the components 1 in the form of the metallization 6 is connected directly to the circuit carrier 3. This creates a hermetic package.
• the contacts 2 in the form of bumps in the cavities 4 are surrounded by air, that is to say the dielectric constant between the contacts 2 is approximately 1, use in high-frequency technology is possible.
• Components with high losses for example GaAs chips, can be ground thin before they are put on.
• a window 7 cut freely in the photo by means of a laser or the like lie 5 on the side of the component 1 facing away from the circuit carrier 3 enables the copper metallization 6 to be contacted directly on the component surface. The heat dissipation is thus not hindered by the film 5. In the same way, a ground connection of the component substrate back can be realized.
• a contact element 8 in the form of a solder bump is arranged on the side of the circuit carrier 3 opposite the component 1.
• a passive component 9 is arranged on the side of the circuit carrier 3 opposite the component 1 and is soldered to solder 10.
• a contact element 11 in the form of a solder bump is arranged, which rises higher above the surface of the circuit carrier 3 than the component 1 with the contacts 2.
• the variants shown represent only preferred embodiments.
• Si or GaAs chips can also be used in mixed assembly.
• LTCC ceramics have been tested as substrates for the circuit carrier, other ceramics, such as HTCC or Al2O3, or organic substrates, such as FR5, with the lowest possible expansion coefficients are also conceivable.
• the embodiment according to FIG. 1 can be made pick & place-capable, for example, by a casting compound, which enables inexpensive assembly.
• chips need to be contacted by wire bonding, they can either be arranged on the back or can also be inserted under the shielding film 5 with a protective cover.
• Cooling of components is possible, for example by applying heat sinks,

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• Physics & Mathematics (AREA)
• Engineering & Computer Science (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• General Physics & Mathematics (AREA)
• Computer Hardware Design (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Power Engineering (AREA)
• Health & Medical Sciences (AREA)
• Manufacturing & Machinery (AREA)
• Electromagnetism (AREA)
• Toxicology (AREA)
• Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
• Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
• Surface Acoustic Wave Elements And Circuit Networks Thereof (AREA)
• Microwave Amplifiers (AREA)
• Wire Bonding (AREA)

Applications Claiming Priority (2)

Publications (1)

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Family Applications (1)

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• 2003
  • 2003-06-30 DE DE10329329A patent/DE10329329B4/de not_active Expired - Fee Related
• 2004
  • 2004-06-29 EP EP04741915A patent/EP1639642A2/de not_active Withdrawn
  • 2004-06-29 CN CNB2004800008421A patent/CN100382306C/zh not_active Expired - Fee Related
  • 2004-06-29 US US10/527,961 patent/US20060162157A1/en not_active Abandoned
  • 2004-06-29 WO PCT/EP2004/051282 patent/WO2005001934A2/de active Application Filing
  • 2004-06-29 JP JP2005518163A patent/JP2006510235A/ja active Pending
  • 2004-06-29 KR KR1020057004365A patent/KR100697434B1/ko not_active IP Right Cessation

Non-Patent Citations (1)

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