CN100382306C - 节约成本的高频包装 - Google Patents
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- 238000005476 soldering Methods 0.000 claims description 15
- 238000000034 method Methods 0.000 claims description 13
- 239000011248 coating agent Substances 0.000 claims description 10
- 238000000576 coating method Methods 0.000 claims description 10
- 238000009434 installation Methods 0.000 claims 1
- 239000002184 metal Substances 0.000 abstract description 5
- 239000010408 film Substances 0.000 description 14
- 238000005516 engineering process Methods 0.000 description 7
- 238000007789 sealing Methods 0.000 description 7
- 239000011796 hollow space material Substances 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 239000000919 ceramic Substances 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 238000005507 spraying Methods 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- SWPMTVXRLXPNDP-UHFFFAOYSA-N 4-hydroxy-2,6,6-trimethylcyclohexene-1-carbaldehyde Chemical compound CC1=C(C=O)C(C)(C)CC(O)C1 SWPMTVXRLXPNDP-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 229910052593 corundum Inorganic materials 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 235000013399 edible fruits Nutrition 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000003801 milling Methods 0.000 description 1
- 125000000962 organic group Chemical group 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 238000012797 qualification Methods 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
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- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
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Abstract
为了生成一种高频包装,一个元器件通过触点与一个电路载体相连,这些触点将所述元器件相对于电路载体间隔开,在元器件和电路载体上涂覆一层薄膜,并且这层薄膜被金属喷镀。
Description
通常的、密封的、用于模块的高频包装最主要由被铣削的金属壳体构成,该壳体被镀金并且接下来用一个被钎焊的金属壳进行封闭。密封的单个元器件-陶瓷壳体、例如其用于OFW-元器件同样花费巨大,并且对于损耗功率较大的元器件来说越来越不适用了。
当不需要密封性而是需要一种良好的屏蔽时,普通的HF-金属壳体非常贵、非常大并且不再气密地密封,如其经常应用于模块那样。
同样昂贵的是基于最新的LTCC-技术(低温共烧陶瓷技术)的HF-模块壳体。在此,陶瓷只是在盖子被钎焊时用于线路安装。
典型的基于HTCC-技术(高温共烧陶瓷技术)的OFW-过滤器壳体被滚子接缝焊接,并且直到约5GHz对于元器件来说可没有大的耗损功率地被使用。盖子焊接当然比较复杂,并且壳体只是可以应用于一个限定的频率范围。
现有的、密封的CSP-壳体由于在高频范围内将要用到的金-锡-钎焊盖子同样是昂贵的。
DE 10041770 A1中公开了一种具有一个第一电介质层、一个高频结构层和至少一个低频结构层的基底,其中高频结构层包括一个高频-配电***。一个由此而形成的模块还包括一个盖子。
WO 97/45955 A1、WO 99/43084 A1、DE 19548048 A1和DE 19818824 A1中公开了位于电路载体上的电子元器件,这些电子元器件利用盖子、特别是以薄膜的方式被覆盖。此处所用的金属薄膜用手工操作非常困难,并且经常不能被证明为是长期稳定的。
由这一点出发,本发明的任务是给出一个节约成本的用于制造高频包装的方法。
这个任务通过在独立权利要求中给定的发明来解决。有利的方案在从属权利要求中得出。
与此对应,一个电路载体与一个元器件通过触点相连,这些触点将元器件相对于电路载体隔开,从而在元器件、电路载体和触点之间形成空心空间。在该元器件和电路载体上涂覆一层薄膜,使得该薄膜紧紧地贴靠在电路载体(所述元器件位于该电路载体上)的上表面上,并且紧紧地贴靠在元器件的不是面对电路载体的侧面上。在将薄膜涂覆到元器件和电路载体上后,薄膜设置一个金属喷镀涂层。一个钎焊凸缘(Lotbump)设置在电路载体的装配有元器件的侧面上。这个钎焊凸缘如此超出元器件:该钎焊凸缘从电路载体看去比元器件要高。由此,通过电路载体、元器件、薄膜和薄膜的金属喷镀涂层构成的包装在侧面(在该侧面上在电路载体上设置元器件)通过钎焊凸缘例如与另一个电路载体电连接。
该金属喷镀涂层最好通过溅射或者蒸镀来涂覆,并且接下来加强电流。
在薄膜中可以在元器件的背对电路载体的侧面上打开一个窗口,通过该窗口可以接触元器件。窗口的打开在薄膜被金属化之前进行,因此触点可以同样通过所述金属喷镀涂层制造出来。
元器件特别是一个有源元器件、一个高频元器件和/或一个超高频元器件。
在元器件之外,在电路载体上还设置一个或者多个无源的元器件。该无源的元器件最好设置在电路载体的与元器件对置的侧面上。
本发明其它的优点和特征借助于附图从对实施例的说明中得出。
附图示出:
图1是一个单面装备的电路载体的视图,该电路载体具有位于电路载体背面上的丝网印刷的钎焊凸缘;
图2是一个双面装备的电路载体的视图,该电路载体具有位于电路载体前面的、被安放的钎焊头或者钎焊凸缘以及一个位于电路载体后面的、安装在上表面处的无源元器件。
包装的过程在凹槽里进行,并且可以例如如下文中实施的那样进行。与本发明的通用性相对应,在过程链中可以作很多的改动。
元器件1以芯片的形式被***,并且被印刷的触点2以钎焊凸缘的形式被包围熔化。另一种方案中,一个电路载体3也被***。
元器件1单独地、翻转地以触点2浸渍在熔剂中,并且放置在例如用陶瓷制成的电路载体3的连接垫上。此处,在元器件1、触点2和电路载体3之间生成一个空心空间4。
接着将一个薄膜5完全平坦地层压在元器件1上,并且在接触位置处以及在模块边缘(锯齿痕迹)处例如借助于激光进行平整。
薄膜5通过完全平坦的涂层例如借助于铜-溅射设置一个金属喷镀涂层6,该金属喷镀必要时加强电流。
最好在电路载体3上以在陶瓷上进行金属喷镀涂层的方式围绕一个或者多个框架12,在这些框架处薄膜5被平整。在此,通过元器件1张紧的金属屏蔽层以金属喷镀涂层6的方式直接与电路载体3相连。由此形成了一种密封的包装。
因为触点2以凸缘的形式在空心空间4中被空气包围,也就是在触点2之间的绝缘常数约为1,因此可以使用直到超高频技术的技术。具有高的损耗功率的元器件、例如GaAs-芯片(砷化镓芯片)可以在其被安放之前被磨细。可以借助于激光或者类似方式在薄膜5内在元器件1背对电路载体3的侧面上暴露地切削出窗口7,使得铜-喷镀涂层6直接在元器件上表面上被接触。因此,热量导出不会被薄膜5阻止。元器件基底背面的接地连接可以以相同的方式来实现。
在按照图1的实施方式中,在电路载体3的与元器件1对置的侧面上以一个钎焊凸缘的方式设置一个接触元件8。
在按照图2的实施方式中,在电路载体3的与元器件1对置的侧面上设置一个无源的元器件9并且以钎料10来钎焊。
此外,在电路载体3的侧面(在该侧面上存在元器件1)上以一个钎焊凸缘的方式设置一个接触元件11,该接触元件在电路载体3的上表面上高出具有触点2的元器件1。
所示的变型方案只是说明了优选的实施方式。作为元器件例如Si芯片或者GaAs-芯片也可以进行混合装备。LTCC-陶瓷用作电路载体的基底得到了考验,其它的具有尽可能微小的延伸系数的陶瓷、如HTCC或者Al2O3或者如FR5的有机基底同样可以考虑使用。按照图1的实施方式例如通过一种填料是有取置能力的(pick & place-faehig),这可以实现一种节约成本的装备。
如果芯片必须通过引线结合法来接触,那么芯片可以或者设置在背面或者也用一个安全罩安装在屏蔽薄膜5下边。
本发明所有的实施方式说明了以下优点:
-超高频能力(>20GHz),因为没有不充满的(在所述凸缘之间ε=1)、短的、恒定长度的信号传输时间(倒装芯片代替引线结合器),
-密封的密封性和ESD-屏蔽在制造成本非常小的情况下使用,
-元器件可以散热、例如通过运用冷却体,
-通用性:可以与HTCC-技术和LTCC-技术结合的不同的元器件载体和电路载体、SMD元器件也可以例如安装在电路载体背面上,
-易于与不同的包装类型匹配。
Claims (9)
1.一种方法,其中
-一个电路载体(3)与一个元器件(1)通过触点(2)相连,该触点将元器件(1)相对于电路载体(3)间隔开,
-一个薄膜(5)涂覆在元器件(1)和电路载体(3)上,
-薄膜(5)被金属喷镀,
-在电路载体(3)上安装一个接触元件(11),
-在电路载体(3)的布置元器件(1)的侧面上设置的所述接触元件(11)超出元器件(1)。
2.按照权利要求1所述的方法,其中薄膜(5)的金属喷镀涂层(6)加强电流。
3.按照权利要求1或2所述的方法,其中在所述薄膜(5)中、在元器件(1)的背对电路载体(3)的侧面上打开一个窗口(7)。
4.按照权利要求1或2所述的方法,其中元器件(1)是一个高频元器件。
5.按照权利要求4所述的方法,其中元器件(1)是一个超高频元器件.
6.按照权利要求1或2所述的方法,其中在电路载体(3)上设置一个无源的元器件(9)。
7.按照权利要求6所述的方法,其中无源的元器件(9)设置在电路载体(3)的与元器件(1)对置的侧面上。
8.按照权利要求1所述的方法,其中所述接触元件是钎焊凸缘。
9.按照权利要求1至8中任意一项所述的方法生产出来的高频包装。
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DE10329329A DE10329329B4 (de) | 2003-06-30 | 2003-06-30 | Hochfrequenz-Gehäuse und Verfahren zu seiner Herstellung |
DE10329329.9 | 2003-06-30 |
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CN1701440A CN1701440A (zh) | 2005-11-23 |
CN100382306C true CN100382306C (zh) | 2008-04-16 |
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US (1) | US20060162157A1 (zh) |
EP (1) | EP1639642A2 (zh) |
JP (1) | JP2006510235A (zh) |
KR (1) | KR100697434B1 (zh) |
CN (1) | CN100382306C (zh) |
DE (1) | DE10329329B4 (zh) |
WO (1) | WO2005001934A2 (zh) |
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KR100691160B1 (ko) * | 2005-05-06 | 2007-03-09 | 삼성전기주식회사 | 적층형 표면탄성파 패키지 및 그 제조방법 |
KR100703090B1 (ko) * | 2005-08-30 | 2007-04-06 | 삼성전기주식회사 | 후면 접지형 플립칩 반도체 패키지 |
DE102006025162B3 (de) * | 2006-05-30 | 2008-01-31 | Epcos Ag | Flip-Chip-Bauelement und Verfahren zur Herstellung |
DE102010054782A1 (de) | 2010-12-16 | 2012-06-21 | Epcos Ag | Gehäustes elektrisches Bauelement |
JP5799541B2 (ja) | 2011-03-25 | 2015-10-28 | 株式会社ソシオネクスト | 半導体装置及びその製造方法 |
FR2984882A1 (fr) | 2011-12-23 | 2013-06-28 | Saint Gobain Ct Recherches | Procede de fabrication d'un produit mesoporeux. |
KR101356791B1 (ko) | 2012-01-20 | 2014-01-27 | 한국과학기술원 | 박막형 수퍼커패시터 및 그의 제조 방법 |
CN105702664A (zh) * | 2012-11-16 | 2016-06-22 | 日月光半导体制造股份有限公司 | 半导体封装构造及其制造方法 |
US9484313B2 (en) * | 2013-02-27 | 2016-11-01 | Advanced Semiconductor Engineering, Inc. | Semiconductor packages with thermal-enhanced conformal shielding and related methods |
WO2015197551A1 (de) * | 2014-06-23 | 2015-12-30 | Epcos Ag | Gehäuse für ein elektrisches bauelement und verfahren zur herstellung eines gehäuses für ein elektrisches bauelement |
CN106816420A (zh) * | 2015-11-30 | 2017-06-09 | 讯芯电子科技(中山)有限公司 | 一种声波元件封装结构及其制造方法 |
US10741501B1 (en) * | 2018-10-22 | 2020-08-11 | Keysight Technologies, Inc. | Systems and methods for sheathing electronic components |
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- 2004-06-29 CN CNB2004800008421A patent/CN100382306C/zh not_active Expired - Fee Related
- 2004-06-29 US US10/527,961 patent/US20060162157A1/en not_active Abandoned
- 2004-06-29 WO PCT/EP2004/051282 patent/WO2005001934A2/de active Application Filing
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Also Published As
Publication number | Publication date |
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JP2006510235A (ja) | 2006-03-23 |
CN1701440A (zh) | 2005-11-23 |
KR100697434B1 (ko) | 2007-03-20 |
EP1639642A2 (de) | 2006-03-29 |
WO2005001934A3 (de) | 2005-05-12 |
KR20050042200A (ko) | 2005-05-04 |
US20060162157A1 (en) | 2006-07-27 |
DE10329329B4 (de) | 2005-08-18 |
WO2005001934A2 (de) | 2005-01-06 |
DE10329329A1 (de) | 2005-02-17 |
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