EP1214735A1 - Methode zur herstellung relaxierter silizium-germanium-schichten - Google Patents
Methode zur herstellung relaxierter silizium-germanium-schichtenInfo
- Publication number
- EP1214735A1 EP1214735A1 EP00974128A EP00974128A EP1214735A1 EP 1214735 A1 EP1214735 A1 EP 1214735A1 EP 00974128 A EP00974128 A EP 00974128A EP 00974128 A EP00974128 A EP 00974128A EP 1214735 A1 EP1214735 A1 EP 1214735A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- germanium
- layer
- source gas
- gas
- component
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
- C30B25/02—Epitaxial-layer growth
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
- C30B29/10—Inorganic compounds or compositions
- C30B29/52—Alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02381—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02441—Group 14 semiconducting materials
- H01L21/0245—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02494—Structure
- H01L21/02496—Layer structure
- H01L21/0251—Graded layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
Definitions
- the invention relates to the field of relaxed SiGe layers.
- CVD is, under most conditions and products, the most economical method of depositing thin layers of crystalline semiconductors.
- High thin-film growth rates are essential in producing economical relaxed SiGe materials on Si substrates, since the SiGe layers are relatively thick.
- the highest growth rates known to date, which have been deposited in non-commercial equipment, have been achieved with CVD, with a maximum growth rate of about 6 micrometers per hour.
- CVD deposition equipment can become too coated with thin film deposit in areas other than the substrate area. If this deposition is too great, it may prevent a large number of consecutive wafer deposition processes, leading to greater cost.
- An additional problem is that in attempting to deposit films at high growth rates, gas-phase nucleation can occur, in which particles of SiGe, Si, or Ge form in the gas stream and subsequently deposit on the wafer surface.
- FIG. 1 is a graph showing the growth rate of epitaxial silicon as a function of growth temperature for a variety of Si source gases;
- FIG. 2 is a graph of the threading dislocation density at the surface of a relaxed
- FIGs. 3A and 3B are schematic block diagrams of exemplary structures with a uniform cap layer of Si,. x Ge x (0 ⁇ x ⁇ l) and Si 07 Ge 03 , respectively, on a silicon substrate using a relaxed SiGe graded buffer layer in accordance with the invention.
- FIG. 1 is a graph showing the growth rate of silicon versus temperature for various source gases. Two distinct growth regimes are evident. For low temperatures, the growth rate has an exponential dependence on temperature, indicating that the growth is reaction rate or kinetically limited. For high temperatures, the growth rate has a weak dependence on temperature, indicating that the growth is mass transport or diffusion limited. Epitaxial layers are formed in the mass transport limited regime to minimize the effects of temperature variations during growth.
- germane-chlorine-based gas used to increase the decomposition temperature.
- chlorogermanes can be used to extend growth temperatures to more than 200°C over germane growth temperatures without increasing gas phase nucleation. In this way, the decomposition temperatures of the gases can be optimally chosen such that very high growth rates can be achieved at high temperatures.
- the most readily available germanium-chlorine source gas is germanium tetrachloride, (GeCl 4 ). This gas, unlike germane, can be used at growth temperatures in excess of 800°C to grow thick, relaxed SiGe layers without excessive equipment coating and particle formation. It can be combined with any of the source gases for silicon, such as silane, dichlorosilane, trichlorosilane, and silicon tetrachloride to form high quality SiGe layers.
- FIGs. 3A and 3B are schematic block diagrams of exemplary structures with a uniform cap layer of Si !.x Ge x (0 ⁇ x ⁇ 1) and Si 07 Ge 03 , respectively, on a silicon substrate using a relaxed SiGe graded buffer layer in accordance with the invention.
- the structures include a monocrystalline silicon substrate 300, a SiGe graded buffer layer 302, and a uniform concentration SiGe cap layer 304, 306.
- the SiGe buffer layer 302 is a series of SiGe layers with increasing Ge concentration, usually with a gradient of less than 25% Ge per micron. By increasing the Ge concentration gradually, the strain due to the lattice mismatch between Si and Ge is relieved and the threading dislocation density is minimized.
- the cap layers are high quality
- SiGe layer with uniform Ge concentration that can be used as a platform for device fabrication.
- FIG. 3 A shows a generic structure where the cap layer 304 Ge concentration can vary from 0 ⁇ x ⁇ l.
- FIG. 3B shows a structure where the cap layer 306 is Si 07 Ge 03 .
Landscapes
- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Manufacturing & Machinery (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Materials Engineering (AREA)
- Crystallography & Structural Chemistry (AREA)
- Metallurgy (AREA)
- Organic Chemistry (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Crystals, And After-Treatments Of Crystals (AREA)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US15485199P | 1999-09-20 | 1999-09-20 | |
US154851P | 1999-09-20 | ||
PCT/US2000/040938 WO2001022482A1 (en) | 1999-09-20 | 2000-09-19 | Method of producing relaxed silicon germanium layers |
Publications (1)
Publication Number | Publication Date |
---|---|
EP1214735A1 true EP1214735A1 (de) | 2002-06-19 |
Family
ID=22553074
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP00974128A Withdrawn EP1214735A1 (de) | 1999-09-20 | 2000-09-19 | Methode zur herstellung relaxierter silizium-germanium-schichten |
Country Status (3)
Country | Link |
---|---|
EP (1) | EP1214735A1 (de) |
JP (1) | JP2003517726A (de) |
WO (1) | WO2001022482A1 (de) |
Families Citing this family (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7041170B2 (en) * | 1999-09-20 | 2006-05-09 | Amberwave Systems Corporation | Method of producing high quality relaxed silicon germanium layers |
AU2002341803A1 (en) | 2001-09-24 | 2003-04-07 | Amberwave Systems Corporation | Rf circuits including transistors having strained material layers |
FR2836159B1 (fr) * | 2002-02-15 | 2004-05-07 | Centre Nat Rech Scient | Procede de formation de couche de carbure de silicium ou de nitrure d'element iii sur un substrat adapte |
US7060632B2 (en) * | 2002-03-14 | 2006-06-13 | Amberwave Systems Corporation | Methods for fabricating strained layers on semiconductor substrates |
GB0212616D0 (en) | 2002-05-31 | 2002-07-10 | Univ Warwick | Formation of lattice-tuning semiconductor substrates |
WO2003105206A1 (en) | 2002-06-10 | 2003-12-18 | Amberwave Systems Corporation | Growing source and drain elements by selecive epitaxy |
EP2267762A3 (de) | 2002-08-23 | 2012-08-22 | Taiwan Semiconductor Manufacturing Co., Ltd. | Halbleiter-Heterostrukturen mit reduzierter Anhäufung von Versetzungen und entsprechende Herstellungsverfahren |
US7594967B2 (en) * | 2002-08-30 | 2009-09-29 | Amberwave Systems Corporation | Reduction of dislocation pile-up formation during relaxed lattice-mismatched epitaxy |
JP4949628B2 (ja) | 2002-10-30 | 2012-06-13 | 台湾積體電路製造股▲ふん▼有限公司 | Cmosプロセス中に歪み半導基板層を保護する方法 |
ATE504082T1 (de) | 2003-05-27 | 2011-04-15 | Soitec Silicon On Insulator | Verfahren zur herstellung einer heteroepitaktischen mikrostruktur |
DE102005000826A1 (de) * | 2005-01-05 | 2006-07-20 | Siltronic Ag | Halbleiterscheibe mit Silicium-Germanium-Schicht und Verfahren zu deren Herstellung |
JP4894390B2 (ja) * | 2006-07-25 | 2012-03-14 | 信越半導体株式会社 | 半導体基板の製造方法 |
EP2104135B1 (de) * | 2008-03-20 | 2013-06-12 | Siltronic AG | Halbleiterwafer mit Heteroepitaxialschicht und Verfahren zur Herstellung des Wafers |
EP4220686B1 (de) * | 2022-01-31 | 2024-07-10 | Siltronic AG | Verfahren zur abscheidung einer spannungsrelaxierten gradierten pufferschicht aus silizium-germanium auf einer oberfläche eines substrats |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3935040A (en) * | 1971-10-20 | 1976-01-27 | Harris Corporation | Process for forming monolithic semiconductor display |
US5221413A (en) * | 1991-04-24 | 1993-06-22 | At&T Bell Laboratories | Method for making low defect density semiconductor heterostructure and devices made thereby |
-
2000
- 2000-09-19 WO PCT/US2000/040938 patent/WO2001022482A1/en not_active Application Discontinuation
- 2000-09-19 JP JP2001525758A patent/JP2003517726A/ja active Pending
- 2000-09-19 EP EP00974128A patent/EP1214735A1/de not_active Withdrawn
Non-Patent Citations (1)
Title |
---|
See references of WO0122482A1 * |
Also Published As
Publication number | Publication date |
---|---|
WO2001022482A9 (en) | 2002-08-08 |
JP2003517726A (ja) | 2003-05-27 |
WO2001022482A1 (en) | 2001-03-29 |
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