EP0596474A2 - Schaltungsanordnung zum kontrollierten Abschalten eines MOS-Feldeffekttransistors - Google Patents

Schaltungsanordnung zum kontrollierten Abschalten eines MOS-Feldeffekttransistors Download PDF

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Publication number
EP0596474A2
EP0596474A2 EP93117822A EP93117822A EP0596474A2 EP 0596474 A2 EP0596474 A2 EP 0596474A2 EP 93117822 A EP93117822 A EP 93117822A EP 93117822 A EP93117822 A EP 93117822A EP 0596474 A2 EP0596474 A2 EP 0596474A2
Authority
EP
European Patent Office
Prior art keywords
gate
circuit
source
voltage
effect transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP93117822A
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English (en)
French (fr)
Other versions
EP0596474B1 (de
EP0596474A3 (de
Inventor
Erich Bayer
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Deutschland GmbH
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Texas Instruments Deutschland GmbH
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Publication date
Application filed by Texas Instruments Deutschland GmbH filed Critical Texas Instruments Deutschland GmbH
Publication of EP0596474A2 publication Critical patent/EP0596474A2/de
Publication of EP0596474A3 publication Critical patent/EP0596474A3/de
Application granted granted Critical
Publication of EP0596474B1 publication Critical patent/EP0596474B1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
    • H03K17/082—Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit
    • H03K17/0822—Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit in field-effect transistor switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the invention relates to a circuit arrangement for controlled switch-off of a metal-oxide semiconductor (MOS) field-effect transistor assigned to the feed circuit of an electrical load, serving particularly as a low-side driver and including an overcurrent detection means and a discharge circuit which is interposed between the gate terminal and the source terminal of the MOS field-effect transistor and which is gate-controllable by the overcurrent detection means for discharging a charge stored in the gate source capacitance in accordance with a predefinable time constant in an overcurrent condition.
  • MOS metal-oxide semiconductor
  • the MOS field-effect transistors are protected from overcurrents, particularly short-circuit currents, by arranging for any such overcurrents to be detected and the power transistor concerned to be switched off.
  • the object of this is to prevent the MOS field-effect transistor from being ruined by thermal overload.
  • the required switch-off is achieved by a simple switch for short-circuiting the gate-source circuit of the MOS field-effect transistor so that discharge of the gate-source capacitance is achieved as quickly as possible.
  • This fast switch-off causes a quick change in the gate potential which due to, for instance, possible inductance in the feeder lines may result in a considerable increase in voltage.
  • This circuit arrangement has the disadvantage, however, that the short-circuit current continues to increase during the actual switch-off action any may even attain values, by the time switch-off is complete, which may amount to a multiple more than the value measured just before switch-off was triggered. Under these circumstances the short-circuit currents may attain values as high as, for example, 100 A, especially in the case of MOS field-effect transistors having a low switch-on resistance and sources having a low internal impedance.
  • the object of the invention is to provide, especially in the case of a low-side driver, a circuit arrangement of the aforementioned kind which is exceptionally simple to realize in which the time span, in which an uncontrolled short-circuit current may flow, is reduced to a minimum and which, at the same time, ensures a reliable switch-off in the absence of voltage increases constituting a hazard to the power transistor.
  • the time constant predefinable by the discharge circuit is switchable between two different values as soon as the MOS field-effect transistor exhibits a gate-source voltage located between an upper voltage range, in which there is practically no change of drain-source resistance with a change of gate-source voltage, and a lower voltage range in which the drain-source resistance changes with the gate-source voltage and in that the time constant has a relatively low value as long as the gate-source voltage is located in the upper voltage range, it assuming a relatively high value as soon as the gate-source voltage is located in the lower voltage range.
  • an extremly reliable protective circuit is provided which particularly in the case of a low-side driver can be realized by the simplest means and with which the switch-off and discharge behaviour as a function of the gate-source voltage profile is divided into a sequence of time periods which the first, whilst the drain-source resistance remains practically unchanged, is quickly passed through and the second period, during which the actual change in resistance occurs, is extended.
  • the time span in which the resulting over current or short-circuit current can practially not be controlled is reduced to a minimum.
  • the resulting change in the gate-source voltage during this first switch-off or discharge period at at a maximum practically no change in the current occurs in the feeder circuit due to the changes in the drain-source resistance being so slight that they can be ignored, so that despite this period being passed through quickly, no increases in voltages whatsoever, for instance due to line inductances, are to be feared.
  • the time duration of the second period of the switch-off or discharge action is extended to such an extent that the occurrence of voltage peaks endangering the MOS field-effect transistors is safely eliminated, despite the large changes in resistance.
  • the transition in time from the first to the second period of the switch-off or discharge action is substantially defined by the instant at which the gate-source voltage has achieved such a value that the drain-source resistance increases perceptibly as a function of the gate-source voltage.
  • Entry into the second period of the switch-off or discharge action is preferably timed to follow slightly before this transition voltage being reached, i.e. already when the gate-source voltage is slightly above this transition voltage. In this way a high degree of safield-effect transistory is achieved, without having to accept an appreciable loss in time as regards the switch-off action.
  • the discharge circuit includes a parallel circuit of a resistance means having at least one ohmic resistor and a diode arrangement of one or more diodes circuited in series.
  • This exceptionally simple circuit embodiment can be employed to special advantage in the case of a low-side driver or a source circuit, whereby the discharge circuit is usefully connected directly to the gate and source terminals of the MOS field-effect transistor.
  • the forward voltage of the diode arrangement is thus to be selected essentially the same as the gate-source transition voltage located between the upper and the lower voltage range. As long as the gate-source voltage is located above the transition voltage or in the upper voltage range the diode arrangement is conducting so that the ohmic resistance in parallel to it is bypassed and discharge of the gate-source capacitance via the diodes and of a switch which is usefully closed via the overcurrent detector means is affected as quickly as possible.
  • the diode arrangement reverses so that the gate-source capacitance is subsequently discharged via the ohmic resistor and the switch. In this case a significantly higher time constant results, as determined by the values of the gate-source capacitance and by the ohmic resistance.
  • Fig. 1 illustrates the feeder circuit 10 for an electric load Z L in series with a metal-oxide semiconductor field-effect transistor To which is assigned a conventional switch-off device for an emergency switch-off in case of a short circuit.
  • the drain terminal D of the MOS field-effect transistor To is connected via the electric load Z L to the positive supply voltage terminal V B whilst its source terminal S is at ground potential.
  • the MOS field-effect transistor To is thus employed as a low-side driver (LSD) in a source circuit.
  • L s low-side driver
  • This conventional switch-off device comprises an electronic switch S interposed between the gate terminal G of the MOS field-effect transistor To and ground M and the source terminal S of the MOS field-effect transistor respectively and can be signalled via an overcurrent detection means 12 via which the switch S is closed as soon as a short circuit indicated by the dotted lines is detected, for instance, in the voltage drop across the load Z L .
  • the gate terminal of the MOS field-effect transistor is placed at ground potential, resulting in the gate-source capacitance C GS being short-circuited and thus discharged with minimum delay.
  • Fig. 2 shows the circuit principle of an example embodiment of the circuit arrangement according to the invention for controlled switch-off of a metal-oxide semiconductor field-effect transistor To, i.e. again a power transistor which serves as a low-side driver in a feed circuit 10 for an electric load Z L is interposed between the drain terminal D of the MOS field-effect transistor To and the positive voltage supply terminal V B to ground (M).
  • the electric load Z L is in turn input by a common source. In this case, however, the line inductance which is always involved, is not shown.
  • a discharge circuit 14 which can be switched between the gate terminal G of the MOS field-effect transistor To and ground (M) comprises a parallel circuit of an ohmic resistor R and a series arrangement of several diodes Di - D n circuited in series with an electronic switch S.
  • This electronic switch S can be signalled via an overcurrent detection means 12 by means of which the feeder circuit 10 containing the MOS field-effect transistor To is monitored for possible short-circuit currents, by e.g. sensing the voltage drop across the load Z L .
  • the overcurrent detector means 12 is designed in such a way that the switch S is closed as soon as short-circuit indicated by the dashed lines occurs.
  • the forward voltage n. U D of the diode arrangement Di - D n is selected so that i r corresponds to a transition value U GSB of the gate-source voltage U GS which is located between an upper voltage range B - C, in which there is practically no change of the drain-source resistance R DS with the gate-source voltage, and a lower voltage range A-B in which the drain-source resistance R DS changes with the gate-source voltage (viz. Fig. 3).
  • the number of diodes D 1 -D n exhibiting in each case a forward voltage U D is to be selected corresponding to the transition voltage U GSB so that when the switch S is closed, this diode arrangement D 1 -D n is first conducting at higher gate-source voltages U GS , but reverses in due time before there is any perceptible increase in the drain-source resistance R DS with increasing gate-source voltage U GS (viz. Fig. 3).
  • Such an increase in the drain-source resistance R DS can be sensed according to Fig. 3 e.g. in the area of the point B on the resistance curve, at which the gate-source voltage U GS assumes the transition value U GSB which is located between the upper voltage range B-C and the lower voltage range A-B.
  • Point C on the characteristic of the drain-source resistance R DS shown in Fig. 3 corresponds to the gate-source switch-on voltage U GSein, whilst point A on the resistance characteristic is attained at the threshold voltage U T at which the MOS field-effect transistor To is OFF or the drain-source resistance R os assumes its high value.
  • the R DS characteristic is, at first, substantially horizontal in a relatively large voltage range C-B, this meaning that there is practically no change of the drain-source resistance R DS in this range with the reduction of the gate-source voltage U GS during switch-off.
  • drain-source resistance R DS sharply increases, particularly in the last section of the lower voltage range B-A, to finally achieve at point A its highest value corresponding to the OFF condition.
  • the dashed horizontal line represents the asymptote approximated by the resistance characteristic for high values of the gate-source voltages U GS .
  • the deviation DR DS with respect to the asymptotes is still so small as to be negligable.
  • the transition voltage U GSB at which the diode arrangement Di - D n begins to reverse, may be preferably shifted somewhat further in the direction of higher gate-source voltages U GS , resulting in a small spacing from the point B on the resistance characteristic.
  • the difference between the gate-source ON voltage U GSein and the transition voltage U GSB should always be as large as possible.
  • the resulting deviation DR DS of the transition voltage U GSB from the asymptotes shown by the dashed lines should be as small as possible.
  • the gate-source voltage U GS is initially still relatively high, i.e. higher than the forward voltage n ⁇ U D of the diode arrangement Di - D n , the latter is initially conducting after the electronic switch S is closed.
  • the diode arrangement Di - D n remains conducting until the gate-source voltage U GS exceeds the transition value U GSB (viz. Fig.3) or the threshold voltage n ⁇ U D of the diode arrangement. This results in the gate-source capacitance, to span the relatively large, upper voltage range B - C, being discharged very quickly with a time constant t 1 in the region of zero.
  • the gate-source capacitance C GS is no longer discharged via the diode arrangement , but instead through the resistor R.
  • the gate-source capacitance C GS is accordingly discharged with a significantly higher time constant t 2 as determined by the values of the gate-source capacitance C GS and the ohmic resistor R.
  • Fig. 4 shows the time profile of the gate voltage V G during the switch-off and/or discharge action, according to which the gate voltage V G in the upper voltage range C - B drops very quickly from the ON voltage U Gein to the transition voltage V GB whilst in the lower voltage range B - A the gate voltage V G sinks relatively slowly to the value zero from the transition value V GB .
  • Time constant t 1 which during the initial switch-off phase is significantly shorter than t 2 to span the upper voltage range C - B, minimizes the time span in which the short-circuit current cannot be controlled. Since there is practically no change in the drain-source resistance R os during this initial switch-off phase no overvoltages due to line inductance L s (viz. Fig. 1) can occur, despite the very quick discharge.
  • the MOS field-effect transistor To thus has optimum protection in any phase of the switch-off action.

Landscapes

  • Electronic Switches (AREA)
  • Emergency Protection Circuit Devices (AREA)
  • Protection Of Static Devices (AREA)
EP93117822A 1992-11-03 1993-11-03 Schaltungsanordnung zum kontrollierten Abschalten eines MOS-Feldeffekttransistors Expired - Lifetime EP0596474B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE4237119 1992-11-03
DE4237119A DE4237119C1 (de) 1992-11-03 1992-11-03 Schaltungsanordnung zum kontrollierten Abschalten eines Metall-Oxid-Halbleiter-Feldeffekttransistors

Publications (3)

Publication Number Publication Date
EP0596474A2 true EP0596474A2 (de) 1994-05-11
EP0596474A3 EP0596474A3 (de) 1994-11-23
EP0596474B1 EP0596474B1 (de) 1998-03-04

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Application Number Title Priority Date Filing Date
EP93117822A Expired - Lifetime EP0596474B1 (de) 1992-11-03 1993-11-03 Schaltungsanordnung zum kontrollierten Abschalten eines MOS-Feldeffekttransistors

Country Status (4)

Country Link
EP (1) EP0596474B1 (de)
JP (1) JP3494682B2 (de)
KR (1) KR100315409B1 (de)
DE (2) DE4237119C1 (de)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106461723A (zh) * 2014-05-27 2017-02-22 雷诺有限合伙公司 场效应晶体管和相关的故障检测装置
CN116990655A (zh) * 2023-09-26 2023-11-03 安徽大学 一种基于漏-源电压变化率的晶体管短路检测电路和方法

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AT407681B (de) * 1995-05-15 2001-05-25 Elin Ebg Traction Gmbh Verfahren zur abschaltung eines spannungsgesteuerten halbleiters
DE19619120A1 (de) * 1996-05-11 1997-11-13 Telefunken Microelectron Schaltvorrichtung mit Leistungs-FET und Kurzschlußerkennung
JP4432953B2 (ja) 2006-09-27 2010-03-17 株式会社日立製作所 半導体電力変換装置
JP5587133B2 (ja) * 2010-10-22 2014-09-10 ローム株式会社 ハイサイドスイッチ回路、インターフェイス回路、および電子機器
GB2597738A (en) 2020-07-31 2022-02-09 Aptiv Tech Ltd A method and switching circuit for connecting and disconnecting current to a load having inductance

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1229140B (de) * 1962-03-01 1966-11-24 Atlas Werke Ag Schaltungsanordnung zur Erzeugung einer zeitabhaengig ansteigenden oder abfallenden Spannung
US4504779A (en) * 1983-03-11 1985-03-12 Hewlett-Packard Company Electrical load drive and control system
DE4012382A1 (de) * 1990-04-18 1991-10-24 Licentia Gmbh Verfahren und anordnung zum abschalten eines leistungshalbleiterschalters mit mos-steuereingang bei ueberstroemen

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3936544A1 (de) * 1988-12-21 1990-06-28 Siemens Ag Schaltungsanordnung zum schutz eines leistungs-mosfet
DE3905645A1 (de) * 1989-02-21 1990-08-23 Licentia Gmbh Ansteuerverfahren zur verbesserung des ueberstromabschaltverhaltens von leistungshalbleiterschaltern mit mos-steuereingang

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1229140B (de) * 1962-03-01 1966-11-24 Atlas Werke Ag Schaltungsanordnung zur Erzeugung einer zeitabhaengig ansteigenden oder abfallenden Spannung
US4504779A (en) * 1983-03-11 1985-03-12 Hewlett-Packard Company Electrical load drive and control system
DE4012382A1 (de) * 1990-04-18 1991-10-24 Licentia Gmbh Verfahren und anordnung zum abschalten eines leistungshalbleiterschalters mit mos-steuereingang bei ueberstroemen

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106461723A (zh) * 2014-05-27 2017-02-22 雷诺有限合伙公司 场效应晶体管和相关的故障检测装置
CN106461723B (zh) * 2014-05-27 2020-07-24 雷诺有限合伙公司 场效应晶体管和相关的故障检测装置
CN116990655A (zh) * 2023-09-26 2023-11-03 安徽大学 一种基于漏-源电压变化率的晶体管短路检测电路和方法
CN116990655B (zh) * 2023-09-26 2023-12-19 安徽大学 一种基于漏-源电压变化率的晶体管短路检测电路和方法

Also Published As

Publication number Publication date
DE69317206D1 (de) 1998-04-09
KR940012840A (ko) 1994-06-24
EP0596474B1 (de) 1998-03-04
DE4237119C1 (de) 1994-02-24
DE69317206T2 (de) 1998-07-09
JP3494682B2 (ja) 2004-02-09
KR100315409B1 (ko) 2002-02-19
JPH06216734A (ja) 1994-08-05
EP0596474A3 (de) 1994-11-23

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