EP0110701B1 - Input buffer circuit - Google Patents
Input buffer circuit Download PDFInfo
- Publication number
- EP0110701B1 EP0110701B1 EP83307239A EP83307239A EP0110701B1 EP 0110701 B1 EP0110701 B1 EP 0110701B1 EP 83307239 A EP83307239 A EP 83307239A EP 83307239 A EP83307239 A EP 83307239A EP 0110701 B1 EP0110701 B1 EP 0110701B1
- Authority
- EP
- European Patent Office
- Prior art keywords
- circuit
- fet
- source follower
- input
- input buffer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
- H03K19/0952—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using Schottky type FET MESFET
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00369—Modifications for compensating variations of temperature, supply voltage or other physical parameters
- H03K19/00384—Modifications for compensating variations of temperature, supply voltage or other physical parameters in field effect transistor circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/01—Modifications for accelerating switching
- H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
- H03K19/01707—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
- H03K19/018507—Interface arrangements
- H03K19/018535—Interface arrangements of Schottky barrier type [MESFET]
Definitions
- the present invention relates to input buffer circuits and more particularly to an input buffer circuit for a digital integrated circuit of FETs which can receive ECL level signals.
- Figure 1 of the accompanying drawings shows by way of example a known input buffer circuit of a digital integrated circuit constructed of FETs (field effect transistors).
- This circuit comprises an inverter which consists of normally "on” type FETs Q 3 and Q 4 , and a level shifting circuit which consists of diodes D and a resistor R.
- the level shifting circuit shifts an input level V in in order to convert it into a voltage level capable of switching the inverter of the succeeding stage, that is, a transition logic level.
- Figure 2 of the accompanying drawings is a graph of transfer characteristics in Figure 1.
- Curves a, b, and c indicate cases where the ratio WJW3 between the gate widths of the FETs Q 3 and Q 4 is set at 5,13 and 50, respectively.
- This graph illustrates the case where a supply voltage V ss is set at -2 V, the threshold voltage V T of the FET at -1 V and the level shift magnitude V s of the diodes D at 1.55 V.
- an input logic swing required for satisfactorily switching the output may be smaller as the ratio between the gate width W 4 of the FET Q 4 and the gate width W 3 of the FET Q 3 is greater.
- the output of the inverter needs to be satisfactorily switched in a range of signal levels from -1.45 V to -1.15 V. It will be noted from Figure 2 that W 4 /W 3 needs to be at least 13 in order to satisfy the above specification.
- the input buffer of Figure 1 has the following two disadvantages:
- Figure 3 of the accompanying drawing is a graph of the transfer characteristics in the case where the threshold voltage V T has fluctuated in the circuit of Figure 1
- Figure 4 of the accompanying drawings is a graph of transfer characteristics in the case where the supply voltage V ss has fluctuated in the same circuit.
- the input necessary for reliably switching the output is about -1.6 V as a low level and about -0.9 V as a high level, that is, the logic swing becomes about 0.7 V.
- This value is approximately double that of the input logic swing 0.3 V which is originally required in the absence of any fluctuation, and it becomes a serious problem.
- the value of 0.7 V corresponds to the addition of about 0.4 V which is the width of the change of the input logic threshold value of the inverter, the change being attributed to the fluctuation of the threshold voltage V T or the supply voltage V ss .
- a further additional input logic swing of 1.1 V with 0.4 V is required.
- the gate width ratio WJW3 is set to be smaller, the influence of the fluctuation of the threshold voltage V T is somewhat mitigated, but the input logic swing originally required increases as stated before. It can accordingly be said that, in the presence of the manufacture dispersion or the supply voltage fluctuation, the signal of the ECL level cannot be received by the circuit of Figure 1.
- FR - A-2,230,125 discloses in Figure 5 a particular application of a voltage regulation system which comprises a resistance and saturable resistance in series across which a fixed potential is applied.
- a diode connected transistorT1 constituting the saturable resistance is connected in series with a resistor R constituting said resistance and a transistor T2 across a predetermined potential.
- Series connected transistors T3 and T4 are connected between the source of fixed potential (+V1 ) and earth.
- the output from the circuit is taken from the junction between the two transistors T3 and T4, and the base of T4 is connected to the junction between the resistance R and diode connected transistor T1.
- the input is applied to the base of the transistor T2.
- GB-1,447,476 discloses a semiconductor circuit arrangement having a plurality of inverting stages and a sample inverting stage.
- Each inverting stage includes an inverting semiconductor device and a load semiconductor device.
- the sample inverting stage includes means for degrading a logic level signal derived therefrom and a regulator associated with the load device for varying its conductance by means of a control signal applied to counteract the degradation.
- the control signal is also applied to the load device of one or more of the other inverting stages for logic level connection purposes.
- US-A-4,242,604 discloses an integrated buffer circuit having a selectable stabilized trip voltage, which circuit includes an input stage and a reference stage. Each of these stages includes a MOS field effect transistor, a substantially constant resistance device coupling the drain of the input transistor to a bias source, and a device having a resistance which is variable in response to control signals coupling the source of the input transistor to another bias source.
- a signal generated at the drain of the transistor in the reference stage is connected to all the variable resistance devices as the control signal. This signal varies the variable resistance in such a way as to compensate for threshold voltage variations in the transistor of the input stage and thus stabilize the selected trip voltage of the input stage.
- an input buffer circuit comprising an inverter circuit; a source follower circuit having first and second FETs of an identical conductivity type whose source-drain paths are connected in series, the gate of said first FET being connected to a circuit input for receiving the input signal, the output of the source follower circuit being connected to the inverter circuit either directly or through a level shift circuit, characterized in that a control voltage is supplied to the gate of said second FET in said source follower circuit to control a transition logic level of said source follower circuit in order to compensate for fluctuations of the input logic threshold of the inverter circuit due to fluctuations of the threshold voltage and/or fluctuations of the supply voltage.
- Figure 5 is a circuit diagram showing an embodiment of an input buffer circuit according to the present invention.
- Figures 6 and 7 are graphs of the transfer characteristics of the circuit in Figure 5;
- Figure 8 is a circuit diagram of a control circuit showing an embodiment of the present invention.
- Figure 9 is a block diagram showing an example of connection between the input buffer circuit of Figure 5 and the control circuit of Figure 8;
- Figures 10, 11, 12, 13, 14, 15, 16 and 17 are circuit diagrams of input buffer circuits each showing another embodiment of the present invention.
- Figure 18 is an arrangement diagram of a control circuit showing another embodiment of the present invention.
- the input buffer circuit includes first, second, third and fourth FETs, Q 1 , Q 2 , Q 3 and Q 4 respectively, and diodes D 2 and a resistor R for level shift.
- Symbols V ss , V SS2 and V LL indicate supply voltages
- symbols V in , V out and V cont indicate voltages at an input terminal, output terminal and control voltage input terminal, respectively.
- the FETs Q 3 and Q 4 constitute an inverter
- the diodes D 2 and the resistor R constitute a level shifting circuit, these elements forming the same circuit as in the prior-art input buffer shown in Figure 1.
- the FETs Q 1 and Q 2 constitute a source follower circuit. Unlike an ordinary source follower circuit, this source follower circuit features that current flowing therethrough can be controlled with the voltage fed to the control voltage input terminal V cont .
- the level shift magnitude of the diodes D 2 will be designated by V s , the source voltage of the FET Q 1 by V 1 , and the gate widths of the FETs Q I -Q 4 by W 1 ⁇ W 4 respectively.
- V s the source voltage of the FET Q 1 by V 1
- W 1 ⁇ W 4 the gate widths of the FETs Q I -Q 4 by W 1 ⁇ W 4 respectively.
- V SS2 and the threshold voltage V T are selected so as to operate the FETs Q1 and Q 2 constituting the source follower, in their saturation regions at all times.
- V in V 1 , V cont and V SS2 Since the saturation condition holds for the FETs Q 1 and Q 2 constituting the source follower, the relationship of V in V 1 , V cont and V SS2 becomes as follows:
- V becomes a voltage obtained by converting the level of the input voltage V ln by a certain value which is determined by V T , V SS2 and V cont .
- V LTH denote the value of V, at this time, namely, the input logic threshold value of the inverter
- V 1TH is given by the following equation:
- V lnTH denote the value of V ln at this time, namely, the input logic threshold value of the circuit of Figure 5, the following is obtained from equations (1) and (2):
- V lnTH can be set at a desired value by selecting the control voltage V cont as follows:
- Figures 6 and 7 are graphs of the transfer characteristics of the circuit in Figure 5, respectively.
- Curves e and f in Figure 6 indicate the transfer characteristics in the cases where the threshold voltage V T has become -1.3 V and -0.7 V, respectively, and curves g and h in Figure 7 the transfer characteristics in the cases where the supply voltage V ss has become -2.2 V and -1.8 V, respectively.
- V cont V T1' V T2 , V T3 and V T4 denote the threshold voltages of the FETs Q 1' Q 2 , Q 3 and Q 4 , respectively.
- the control circuit includes first, second, third and fourth FETs, Q 1 ', Q 2 ', Q 3 ' and Q 4 ' respectively, and divides D2 and a resistor R for level shift. Portions constructed of these elements are identical in arrangement to the input buffer of Figure 5, except that the gate of the FET Q 1 ' is supplied with a reference voltage V ref instead of the input voltage V, n .
- the circuit also includes an inverter circuit INV.
- the input logic threshold voltage of this inverter circuit INV is designed so as to become a value close to the logic threshold voltage of the output V out of the circuit in Figure 5.
- the circuit includes diodes D, a resistor R * and a supply voltage V LL * , these elements constituting a level shifting circuit for adjusting the output level of the inverter circuit INV to the level of the control voltage V cont .
- the output V CONT ' of the level shifting circuit is connected to the gate electrode of the FET Q 2 ' so as to apply feedback.
- the output V CONT ' is also a terminal for deriving the control voltage, and it is connected to the control voltage terminal V cont of the input buffer in Figure 5.
- control voltage V CONT ' has become somewhat higher than V cont . Then, current flowing through the N-channel FET Q 2 ' increases to lower V 1 ' and to raise V 2 ', so that the output of the inverter INV becomes close to the low level. Thus, the control voltage V CONT ' lowers.
- control circuit of Figure 8 forms a feedback circuit which functions in the direction of lowering V CONT ' when this voltage has risen. Accordingly, when the control voltage V CONT has conversely become somewhat lower, the output of the inverter INV functions in the direction of raising the control voltage V CONT '. In this way, the control voltage V CONT ' settles to a value close to V cont , so that the control voltage stable against the fluctuations of the threshold voltage V T and the supply voltage V ss can be attained.
- Figure 9 is a block diagram showing an embodiment in the case of where the control circuit of Figure 8 is connected to a plurality of input buffers of Figure 5. In this manner the control circuit can also supply a control voltage to a plurality of input buffers.
- the circuit shown in block form in Figure 9 includes an ECL LSI, 10 and a FET LSI 20.
- the circuit further includes output buffers 11, 12 and 13 within the ECL LSI 10, input buffers 14 and 15 within the ECL LSI 10, input buffers 21, 22 and 23 being the same as the one shown in Figure 5, these input buffers being within the FET LSI 20, output buffers 24 and 25 within the FET LSI 20; and a control circuit 26 being the same as that shown in Figure 8.
- the level shift magnitudes of the diodes D 2 in Figure 5 and the diodes D 2 ' in Figure 8 need not be equal to each other. When they are not equal, a voltage obtained by subtracting the difference of the level shift magnitudes from the voltage V lnTH may be applied as the reference voltage V ref . It is impossible to make the threshold voltages V T of the respective FETs quite equal. However, as regards the dispersion of the threshold voltages V T of FETs which are simultaneously manufactured within a single LSI chip, relative fluctuations can be made smaller than absolute fluctuations from a design value.
- the input logic threshold value of the inverter INV has been set at a value close to the transition logic level of the output voltage V out of the circuit in Figure 5.
- the fluctuation of the supply voltage is amplified to change the control voltage V CONT ', and the inverter INV operates as described above.
- the constituent circuits of the inverter INV and the number of constituent stages thereof and the kinds of power sources to be used may be chosen anyhow. Further, it is sometimes the case that the number of the diodes D * changes depending upon the output levels of the inverter INV.
- the output of the inverter INV is directly connected to the control voltage V CONT ' and the gate of the FET Q 2 ', to dispense with the diodes D * , resistor R * and supply voltage V LL *, or the sense of the diodes D * becomes the opposite.
- the supply voltages V ss and V SS2 or the supply voltages V LL and V LL ', V LL * may well be equalized.
- Figures 10, 11, 12, 13, 14, 15, 16 and 17 are arrangement diagrams of input buffers each showing further embodiments of the present invention.
- the embodiment of Figure 10 is such that, in the arrangement of Figure 5, the level shifting circuit composed of the diodes D 2 , resistor R and voltage source V LL is replaced with diodes D, connected in series between the FETs Q, and Q 2 , so as to derive the output of the source follower circuit from between the diodes D, and the FET Q 2 and to supply it to the inverter circuit of the succeeding stage.
- the embodiment of Figure 11 is such that, in the arrangement of Figure 5, diodes D, are further connected in series between the FETs Q, and Q 2 , so as to derive the output of the source follower circuit from between the diodes D, and the FET Q 2 and to supply it to the inverter circuit of the succeeding stage through the diodes D 2 .
- the embodiment of Figure 12 is such that, in the arrangement of Figure 5, the level shifting circuit composed of the diodes D 2 , resistor R and voltage source V LL is omitted so as to directly supply the inverter circuit of the succeeding stage with the output of the source follower circuit derived from between the FETs Q 1 and Q 2 .
- the embodiment of Figure 13 is such that, in the arrangement of Figure 11, the FET Q 3 is replaced with a resistor R 3 .
- FIG. 14 The embodiments of Figure 14,15,16 or 17 are such that, in the arrangements of Figure 5,10,11 or 12, a coupling capacitor C is connected between the input end V ln (the gate electrode of the FET Q 1 ) of the source follower circuit and the input end (the gate electrode of the FET Q 4 ) of the inverter circuit, respectively.
- the effect of the present invention is similarly achieved even when the circuit of Figure 5 or the same constituent portions in Figure 8 as in Figure 5 is/are replaced with the circuit shown in Figure 10, 11, 12, 13, 14, 15, 16 or 17.
- the circuit to be used as the input buffer, and the circuit to be used as a part of the control circuit can be selected from among Figures 5, 10, 11, 12, 13, 14, 15, 16 and 17 independently of each other.
- the relations to be met by the FET device constants and circuit constants of the circuit for use as the input buffer and the circuit for use as a part of the control circuit are the same as the relations of equation (6) mentioned before:
- the four FETs Q 1 , Q 2 , Q 3 and Q 4 in one input buffer can be brought closer than the distance between the input buffer and the control circuit, the dispersion of the threshold voltages V T can be made still smaller than in the case of the conditions of equation (6). Accordingly a more remarkable.effect can be expected.
- Figure 18 is an arrangement diagram showing another embodiment of the control circuit portion of the present invention.
- any of the level shifting resistors R used in the various embodiments, except the simple control circuit shown in Figure 18, can be replaced with any desired current limiter.
- One example is a FET whose source electrode and gate electrode are connected in common.
- FETs used in the respective embodiments have been of the N-channel, they all may well be P-channel FETs, with the polarities of the diodes and the supply voltages reversed.
- the coupling capacitor C is connected between the input terminal V ln and the gate electrode of the FET Q 4 , increase in the delay time can be reduced. Needless to say, the connection of such coupling capacitor C is also applicable to circuits in which the FET Q 3 is replaced with the resistor as shown in Figure 13.
- the control circuit is feared to oscillate. For avoiding this drawback, it is effective to connect a capacitor between the terminal of the control voltage V CONT ' and the power source.
- a signal of any desired level can be received by altering the voltage to be applied as the reference voltage V ref of the control circuit.
- the present invention can realize an input buffer less susceptible to manufacturing dispersions or supply voltage fluctuations, without increasing power consumption or delay time. Therefore, the invention is very effective when applied to any sort of FET integrated circuit such as GaAs MESFETs or Si MOS devices.
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Power Engineering (AREA)
- Logic Circuits (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP208301/82 | 1982-11-27 | ||
JP57208301A JPS5999819A (ja) | 1982-11-27 | 1982-11-27 | 入力インタ−フエイス回路 |
Publications (3)
Publication Number | Publication Date |
---|---|
EP0110701A2 EP0110701A2 (en) | 1984-06-13 |
EP0110701A3 EP0110701A3 (en) | 1985-01-09 |
EP0110701B1 true EP0110701B1 (en) | 1987-09-30 |
Family
ID=16553980
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP83307239A Expired EP0110701B1 (en) | 1982-11-27 | 1983-11-28 | Input buffer circuit |
Country Status (5)
Country | Link |
---|---|
US (1) | US4697110A (ja) |
EP (1) | EP0110701B1 (ja) |
JP (1) | JPS5999819A (ja) |
CA (1) | CA1201179A (ja) |
DE (1) | DE3373963D1 (ja) |
Families Citing this family (23)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0763140B2 (ja) * | 1985-11-13 | 1995-07-05 | 松下電器産業株式会社 | ゲ−ト回路 |
NZ218649A (en) * | 1985-12-20 | 1989-04-26 | Fujitsu Ltd | Slice amplifier using two fets and slice level control circuitry |
US4701643A (en) * | 1986-03-24 | 1987-10-20 | Ford Microelectronics, Inc. | FET gate current limiter circuits |
DE3765203D1 (de) * | 1986-07-21 | 1990-10-31 | Siemens Ag | Integrierbare schaltung zur pegelumsetzung. |
JPH0752837B2 (ja) * | 1987-03-11 | 1995-06-05 | 三菱電機株式会社 | 論理回路 |
US4877976A (en) * | 1987-03-13 | 1989-10-31 | Gould Inc. | Cascade FET logic circuits |
DK136988A (da) * | 1987-03-13 | 1988-09-14 | Gould Inc | Kaskadekoblede, logiske fet-kredsloeb |
US4798978A (en) * | 1987-04-30 | 1989-01-17 | Gain Electronics Corporation | GAAS FET logic having increased noise margin |
US4782250A (en) * | 1987-08-31 | 1988-11-01 | International Business Machines Corporation | CMOS off-chip driver circuits |
US4970413A (en) * | 1987-10-28 | 1990-11-13 | Gigabit Logic | VBB-feedback threshold compensation |
US4868427A (en) * | 1987-10-30 | 1989-09-19 | Gazelle Microcircuits, Inc. | ECL to TTL circuit |
US4814635A (en) * | 1987-11-27 | 1989-03-21 | Motorola, Inc. | Voltage translator circuit |
JP2574859B2 (ja) * | 1988-03-16 | 1997-01-22 | 株式会社日立製作所 | Fet論理回路 |
JP2751422B2 (ja) * | 1988-06-27 | 1998-05-18 | 日本電気株式会社 | 半導体装置 |
DE4011937A1 (de) * | 1989-04-17 | 1990-10-18 | Mitsubishi Electric Corp | Eingangspufferschaltkreis fuer integrierte halbleiterschaltkreise |
NL8901170A (nl) * | 1989-05-10 | 1990-12-03 | Philips Nv | Geintegreerde schakeling met een signaalniveauconverter. |
FR2648643B1 (fr) * | 1989-06-20 | 1991-08-30 | Thomson Composants Microondes | Circuit d'interface entre deux circuits numeriques de natures differentes |
JP2774176B2 (ja) * | 1990-03-20 | 1998-07-09 | 富士通株式会社 | 半導体集積回路 |
JPH0567933A (ja) * | 1991-09-06 | 1993-03-19 | Toshiba Corp | レベルシフト回路 |
JP3315178B2 (ja) * | 1993-02-19 | 2002-08-19 | 三菱電機株式会社 | レベルシフト回路 |
US6605974B2 (en) * | 2001-07-31 | 2003-08-12 | Telefonaktiebolaget Lm Ericsson(Publ) | Level shifter with gain |
JP5038710B2 (ja) | 2006-12-28 | 2012-10-03 | 株式会社日立製作所 | レベル変換回路 |
KR101711236B1 (ko) * | 2009-10-09 | 2017-02-28 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 반도체 장치 |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3299291A (en) * | 1964-02-18 | 1967-01-17 | Motorola Inc | Logic elements using field-effect transistors in source follower configuration |
GB1447476A (en) * | 1972-11-28 | 1976-08-25 | Plessey Co Ltd | Semiconductor circuit arrangements |
JPS5845137B2 (ja) * | 1973-05-04 | 1983-10-07 | 株式会社日立製作所 | デンシジユウソウチ |
FR2230125A1 (en) * | 1973-05-16 | 1974-12-13 | Thomson Csf | Intergrated FET voltage converter with FET in series with resistor - to give constant difference between input and output voltages |
US4023050A (en) * | 1976-05-10 | 1977-05-10 | Gte Laboratories Incorporated | Logic level converter |
US4242604A (en) * | 1978-08-10 | 1980-12-30 | National Semiconductor Corporation | MOS Input circuit with selectable stabilized trip voltage |
FR2469052A1 (fr) * | 1979-11-05 | 1981-05-08 | Thomson Csf | Comparateur a memoire, assurant la regeneration de signaux electriques numeriques, et systeme de transmission numerique utilisant un tel comparateur |
FR2485832A1 (fr) * | 1980-06-24 | 1981-12-31 | Thomson Csf | Inverseur logique, et operateur a plusieurs sorties derive de cet inverseur, utilisant au moins un transistor a effet de champ a faible tension de seuil |
JPS5750135A (en) * | 1980-09-09 | 1982-03-24 | Nec Corp | Inverter circuit |
US4393315A (en) * | 1981-05-18 | 1983-07-12 | Sperry Corporation | High-gain stabilized converter |
US4453095A (en) * | 1982-07-16 | 1984-06-05 | Motorola Inc. | ECL MOS Buffer circuits |
US4496856A (en) * | 1982-07-21 | 1985-01-29 | Sperry Corporation | GaAs to ECL level converter |
JPS5943631A (ja) * | 1982-09-06 | 1984-03-10 | Hitachi Ltd | レベル変換入力回路 |
US4558235A (en) * | 1983-08-31 | 1985-12-10 | Texas Instruments Incorporated | MESFET logic gate having both DC and AC level shift coupling to the output |
-
1982
- 1982-11-27 JP JP57208301A patent/JPS5999819A/ja active Pending
-
1983
- 1983-11-25 CA CA000442012A patent/CA1201179A/en not_active Expired
- 1983-11-28 EP EP83307239A patent/EP0110701B1/en not_active Expired
- 1983-11-28 US US06/555,618 patent/US4697110A/en not_active Expired - Fee Related
- 1983-11-28 DE DE8383307239T patent/DE3373963D1/de not_active Expired
Also Published As
Publication number | Publication date |
---|---|
JPS5999819A (ja) | 1984-06-08 |
US4697110A (en) | 1987-09-29 |
CA1201179A (en) | 1986-02-25 |
DE3373963D1 (en) | 1987-11-05 |
EP0110701A3 (en) | 1985-01-09 |
EP0110701A2 (en) | 1984-06-13 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
EP0110701B1 (en) | Input buffer circuit | |
US5451898A (en) | Bias circuit and differential amplifier having stabilized output swing | |
US4970415A (en) | Circuit for generating reference voltages and reference currents | |
JP2525346B2 (ja) | 定電流源回路を有する差動増幅回路 | |
US5021691A (en) | Level conversion circuit having capability of supplying output signal with controlled logical level | |
US20060017457A1 (en) | Temperature-compensated output buffer method and circuit | |
US4380710A (en) | TTL to CMOS Interface circuit | |
US20060097769A1 (en) | Level shift circuit and semiconductor circuit device including the level shift circuit | |
US5212458A (en) | Current mirror compensation circuit | |
EP0594305A1 (en) | Comparator circuit | |
US5514983A (en) | CMOS full duplex transmission-reception circuit | |
US4701643A (en) | FET gate current limiter circuits | |
US5565795A (en) | Level converting circuit for reducing an on-quiescence current | |
US5128556A (en) | Current-switching type logic circuit | |
US6281731B1 (en) | Control of hysteresis characteristic within a CMOS differential receiver | |
US5973544A (en) | Intermediate potential generation circuit | |
US4071784A (en) | MOS input buffer with hysteresis | |
US5656952A (en) | All-MOS differential high speed output driver for providing positive-ECL levels into a variable load impedance | |
US6229382B1 (en) | MOS semiconductor integrated circuit having a current mirror | |
US4968904A (en) | MESFET circuit with threshold-compensated source-follower output | |
US4798979A (en) | Schottky diode logic for E-mode FET/D-mode FET VLSI circuits | |
US5051626A (en) | Buffer circuit for logic level conversion | |
US4771189A (en) | FET gate current limiter circuit | |
US5648734A (en) | Buffer circuit and bias circuit | |
US7034568B2 (en) | Logic circuit |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
|
17P | Request for examination filed |
Effective date: 19840109 |
|
AK | Designated contracting states |
Designated state(s): DE FR GB NL |
|
PUAL | Search report despatched |
Free format text: ORIGINAL CODE: 0009013 |
|
AK | Designated contracting states |
Designated state(s): DE FR GB NL |
|
17Q | First examination report despatched |
Effective date: 19860514 |
|
GRAA | (expected) grant |
Free format text: ORIGINAL CODE: 0009210 |
|
AK | Designated contracting states |
Kind code of ref document: B1 Designated state(s): DE FR GB |
|
REF | Corresponds to: |
Ref document number: 3373963 Country of ref document: DE Date of ref document: 19871105 |
|
ET | Fr: translation filed | ||
PLBE | No opposition filed within time limit |
Free format text: ORIGINAL CODE: 0009261 |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT |
|
26N | No opposition filed | ||
PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: GB Payment date: 19951117 Year of fee payment: 13 |
|
PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: DE Payment date: 19960129 Year of fee payment: 13 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: GB Effective date: 19961128 |
|
GBPC | Gb: european patent ceased through non-payment of renewal fee |
Effective date: 19961128 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: DE Effective date: 19970801 |
|
PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: FR Payment date: 19971119 Year of fee payment: 15 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: FR Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 19990730 |
|
REG | Reference to a national code |
Ref country code: FR Ref legal event code: ST |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: FR Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 19971130 |