EP0057351B1 - Schaltung zum Angleichen der Signalverzögerungszeiten von miteinander verbundenen Halbleiterschaltungen - Google Patents

Schaltung zum Angleichen der Signalverzögerungszeiten von miteinander verbundenen Halbleiterschaltungen Download PDF

Info

Publication number
EP0057351B1
EP0057351B1 EP82100160A EP82100160A EP0057351B1 EP 0057351 B1 EP0057351 B1 EP 0057351B1 EP 82100160 A EP82100160 A EP 82100160A EP 82100160 A EP82100160 A EP 82100160A EP 0057351 B1 EP0057351 B1 EP 0057351B1
Authority
EP
European Patent Office
Prior art keywords
signal
circuit
die
voltage
der
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
EP82100160A
Other languages
German (de)
English (en)
French (fr)
Other versions
EP0057351A2 (de
EP0057351A3 (en
Inventor
Jack Arthur Dorler
Michael Owen Jenkins
Joseph Michael Mosley
Stephen Douglas Weitzel
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of EP0057351A2 publication Critical patent/EP0057351A2/de
Publication of EP0057351A3 publication Critical patent/EP0057351A3/de
Application granted granted Critical
Publication of EP0057351B1 publication Critical patent/EP0057351B1/de
Expired legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/462—Regulating voltage or current wherein the variable actually regulated by the final control device is dc as a function of the requirements of the load, e.g. delay, temperature, specific voltage/current characteristic
    • G05F1/466—Sources with reduced influence on propagation delay

Definitions

  • the invention relates to a circuit for matching the signal delay times of interconnected semiconductor chips with respect to a setpoint value, which is characterized by the frequency of an externally supplied pulse train and is achieved by means of a control circuit provided on each semiconductor chip by changing the electrical power supplied to the semiconductor chip.
  • the control circuit contains a controllable oscillator and a phase comparison circuit in which the frequency of the controllable oscillator is compared with that of the first pulse train supplied and, in the event of a deviation, is readjusted until synchronization.
  • the current method of circuit design is to design logic circuits and regular arrangements out of them that operate at a certain power level.
  • additional circuits are provided on a semiconductor chip in order to minimize the change in the current level within the logic gate, while the temperature, the supply voltages and also the influences of the manufacturing process vary from lot to lot.
  • Figure 1 shows a typical signal delay versus power curve with an arrow showing current design practice - choosing a power level, maintaining that power level and accepting the resulting signal delay.
  • the design attempts to minimize changes in operational behavior under a number of conditions.
  • the signal delay curve of a gate as a function of power in Figure 1 can move in any direction and even change its slope.
  • the control circuit for the power loss has its own faults. This results in a wide spread of the switching speeds of the logic gates.
  • Figure 2 shows a curve of gate signal delay as a function of power dissipation and serves to illustrate the preferred design method according to the invention.
  • the switching speed or signal delay of the logic gate is selected and the power loss within the circuit is set so that this switching speed is achieved. This is accomplished by designing circuits on the semiconductor chip that are sensitive to the performance characteristics of the logic circuits or matrix arrays on the chip that are applicable during balancing operations.
  • This special circuit (controller for the signal delay) generates a signal which indicates the behavior of the semiconductor chip (switching speed as a function of the power), which is compared with a periodic reference or clock signal used for the entire system. The comparison generates a signal which regulates the electrical power supplied to the logic and / or matrix circuits on the semiconductor chip and thus the operating behavior.
  • the digital control circuit contains a comparison circuit in which the signal delay of a clock pulse in a chain of inverters is compared with the very precisely defined clock interval. Depending on the comparison result, the counter reading of a bidirectional counter is increased or decreased by 1.
  • the counter reading is decoded via a decoder, which changes the divider ratio of a voltage divider by connecting or disconnecting one of a plurality of parallel resistors by means of one of a plurality of transistors. This changes the voltage present at the tap of the voltage divider, which is fed to an emitter follower. The voltage emitted by this is supplied to the semiconductor chips as a supply voltage and influences their signal delay time.
  • European patent application 46 482 also describes a circuit for matching the signal delay times of the logic gates of different semiconductor chips, in which a control circuit for the signal delay is likewise provided on each semiconductor chip.
  • An external clock pulse common to all semiconductor chips is fed to it as a reference signal.
  • the control circuit compares its phase position with that of a pulse train that is supplied by a voltage-controlled oscillator belonging to the control circuit.
  • the voltage obtained and compared as a result of comparison influences the voltage-controlled oscillator until the two pulse trains are synchronized.
  • the increased tension will also Logic gates supplied. It changes their consumption of electrical power so that the desired signal delay, which is a function of the electrical power, is achieved.
  • the invention achieves the object of designing a circuit of the aforementioned type in such a way that it also provides an indication of the relative signal delay of a semiconductor chip with respect to a setpoint.
  • semiconductor chips can be divided into different categories with regard to their relative signal delay and used accordingly.
  • the phase comparison circuit also generates signals B, C, Ü and D which, in conjunction with signals U and D, provide an indication of whether the frequency of the signal supplied by the voltage controlled oscillator is equal to the clock frequency.
  • This display is used to determine whether the semiconductor chip has the AC performance that is dictated by the clock.
  • the AC measurement circuit generates three signals - HIGH, LOW and EQUAL.
  • the "HIGH” signal indicates that the frequency of the voltage controlled oscillator is higher than the clock frequency.
  • the "LOW” signal indicates that the frequency of the voltage controlled oscillator is lower than the clock frequency.
  • the signal “SAME” indicates that the frequency of the voltage controlled oscillator is equal to the clock frequency.
  • phase comparison circuit the low-pass filter, the buffer circuit and the level shift circuit need not be on the semiconductor chip itself.
  • the important circuit that must be on the semiconductor chip is the voltage controlled oscillator, which senses the switching speed or gate signal delay that is present on the semiconductor chip.
  • the other four logic circuit blocks can be present outside the semiconductor chip on another semiconductor chip or can also be composed of discrete components.
  • the voltage controlled oscillator must be on the same semiconductor chip as the logic gates to be controlled.
  • Fig. 5 shows a logic block diagram of the phase comparison circuit and the AC measurement circuit.
  • the phase comparison circuit can be a commercially available one.
  • the logic gates are composed of the circuits of FIG. 12.
  • the function of this logic circuit is to compare the phase of the two input signals, the system clock supplied externally to the semiconductor chip and the level-shifted signal of the voltage-controlled oscillator, and to generate a logic signal at the outputs U and D which has the same frequency as the input signals and has a pulse width that is proportional to the phase difference of the two input signals.
  • the logic elements used in the AC measuring circuit are also composed of the circuits according to FIG. 12.
  • the function of this circuit is to determine whether the frequency of the voltage controlled oscillator signal is equal to, greater than or less than that of the clock signal. This is accomplished by using different clock signals within the phase comparison circuit to determine whether the condition is equality or inequality.
  • the signal "LOW” is generated by the NOR operation of the signals 0, D and C. It can also be seen from FIG. 5 that the signal “FAST” is generated by the NOR operation of the signals U, D and B. As can be seen from Fig. 5, the signal "EQUAL is generated by the NOR operation of the signals HIGH and LOW.
  • Fig. 6 shows the circuit diagram of the low-pass filter.
  • the two input signals U and D are added and filtered to remove the carrier frequency.
  • the output signal VCS ' is a direct current signal.
  • the cut-off frequency of the low-pass filter is chosen so that the ripple of the signal VCS 'is minimal and at the same time the stability of the phase-locked loop is maintained.
  • the 11 shows a reference voltage generator.
  • the voltage is generated by the components TA, TB, TC and TD.
  • the component TE is used to supply the reference voltage BREF to the other circuits.
  • the reference voltage of this circuit serves as a logic threshold for the logic gates of Fig. 12 and for the phase comparison circuit of Fig. 5.
  • the reference voltage VREF is also used by the level shift circuit of Fig. 9. This voltage serves as the reference voltage for the logic signals.
  • Fig. 8 shows the circuit of the voltage controlled oscillator. It consists of N logic gates, which are shown individually in FIG. 10 and are connected to one another in a loop arrangement, the output of gate 1 leading to the input of gate 2 and this continuing until gate N, the output of which on the input of gate 1 is returned.
  • This circuit oscillates at a frequency which is dependent on the gate signal delay of the N elements.
  • the actual gate signal delay of each element is controlled by the VCS signal. It can be seen that the VCS signal changes the performance of each gate. Any change in the gate signal delay results in a change in the frequency of the RLF signal. As the VCS signal increases, the frequency of the RLF signal also increases, and as the VCS signal decreases, the frequency of the RLF signal also decreases.
  • the output signal RLF of this circuit reaches the level shift circuit.
  • the VR signal is the logic reference signal of the gates in this loop.
  • Fig. 9 shows the level shift circuit. Their purpose is to change the logic level of the RLF signal so that signals are obtained which are compatible with the clock signal shown in Fig. 4A generated outside the semiconductor chip.
  • the signal RLF changes between the voltage levels above the signal VR and below this signal.
  • the elements TA, TB, TC and TD form a logic gate configuration in which the current through the element TC flows either through the element TA or through the element TB, depending on the input voltage RLF.
  • the signal VREF which is derived from the circuit of FIG. 11, serves two functions. The first function is to generate a reference current for the current source elements TC and TD. This reference current is generated using elements G, TF and E and elements TC and D of the current source supplied using a current mirror configuration, the connection between TF and TC.
  • the second function of voltage VREF is to clamp the level-shifted output signal of the voltage controlled oscillator using diodes J and H so that the output signal is either above the voltage VREF by the voltage drop across a diode or the voltage drop across a diode below this voltage .
  • the mode of operation of the circuit according to FIG. 9 is controlled by the input signal RLF.
  • the current through element TC flows through element TA.
  • the current through element K flows through element J, which generates a voltage for the level-shifted signal of the voltage-controlled oscillator which is greater than the signal VREF by the voltage drop across the diode.
  • Fig. 12 shows the circuit diagram of an internal gate used in the phase comparison circuit of Fig. 5. The operation of this gate is similar to that of a gate which is implemented using current transfer technology.
  • the reference voltage VREF is generated by the circuit of FIG. 11. The output voltages are clamped levels that are either above or below the signal VREF by the voltage drop across a diode.
  • the circuit of Figure 12 is shown with only two input transistors TA and TB, but other additional transistors can be connected in the same way to form a three or four input logic gate.
  • a voltage at input 1 or at input 2 which is above the input reference voltage VREF, conducts the current through this transistor and pulls the output potential 0 by the voltage drop across a diode below the voltage VREF.
  • the output voltage 0 is higher than the voltage VREF by the voltage drop across a diode. If the voltages at inputs 1 and 2 are both less than the voltage VREF, the current flows through the element TC and pulls the signal at the output 0 of the diode below the value VREF. The output signals in the circuit are clamped by diodes to provide the correct voltages to control the remainder of the phase control circuit shown in FIG. 4.
  • FIG. 10 is the circuit diagram of a typical logic gate used in both the voltage controlled oscillator (FIG. 8) and the logic gates in the rest of the semiconductor chip, as indicated in FIG. 4.
  • the elements TD and E form a current source which is controlled by a signal VCS.
  • the signal VCS therefore directly controls the power within the logic gate and thus its switching speed.
  • the logic gate is shown with two inputs, transistors TA and TB, but additional transistors can be provided for further inputs, which are connected in the same way.
  • Outputs 0 and 0 are connected to the signal VR via diodes, so that the output voltages are either above or below the signal VR by the voltage drop across a diode.
  • the A Output voltages 1 and 2 of the circuit are either above or below the signal VR, so that when either the input signal 1 or the input signal 2 is above the voltage VR, the current flows through the element TD via the conductive transistor.
  • the output voltage 0 is then around the voltage drop across a diode below the voltage VR. If neither the input voltage 1 nor the input voltage 2 are above the voltage VR, then the output voltage 0 is one diode voltage drop above the voltage VR.
  • both input signals 1 and 2 are below voltage VR, the current through element TD flows through element TC so that signal 0 is below the voltage VR by one diode voltage drop. If both inputs 1 and 2 have the high potential, then the output voltage 0 is lower than the voltage VR by a diode voltage drop.
  • the VR signal is applied to all of the logic gates on the semiconductor chip that are controlled by the signal delay regulator, including those logic gates of the voltage controlled oscillator of FIG. 8, so that all of these logic gates use the same threshold voltage.
  • the circuit of Fig. 7 is a buffer circuit. It represents a high input impedance for the signal VCS 'and a low output impedance for the signal VCS, so that this signal can be routed to all logic gates over the entire semiconductor chip, as shown in FIG. 4.
  • the circuit is a differential amplifier, which has a gain factor of 1.
  • the elements TA, TB and D form the differential input stage of the circuit.
  • the input signal VCS ' is compared using the elements TA, TB and D with the signal at node 1.
  • the elements TE, TF, G, TH, J and K provide the necessary signal conditions so that the signal at node 1 is identical to the input signal VCS '.
  • the TM and N elements provide additional output buffering and voltage shifting to provide a VCS signal which is applied to the logic gates and the voltage controlled oscillator as shown in FIG.
  • FIG. 4A shows a series of waveforms and potential levels which are to be considered in connection with the explanation of the mode of operation of the controller for the signal delay according to FIG. 4. 4 are the waveform W1 (clock) and the waveform W2 (level-shifted signal of the voltage-controlled oscillator). As shown in Fig. 4A, each of these waveforms has a part of each pulse period in which the voltage waveform is larger than the voltage VREF and a part in which the level is lower than the voltage VREF. It is also apparent from the curves W1 and W2 of FIG.
  • the curves W1 and W2 have the same periodicity or pulse repetition frequency.
  • the waveform W1 of the clock pulses in phase leads the level-shifted waveform W2 of the voltage-controlled oscillator.
  • the output signal U of the phase comparison circuit is a level which is constant over time and is denoted by L1 in FIG. 4A. Note that the size of L1 is larger than that of VREF. 4A that the output signal ⁇ is the curve shape W3.
  • the curve shape W3 is a periodic pulse train which has a pulse repetition frequency which is equal to that of the curve shape W1. It can also be seen that the duration of the pulses in the curve W3 is the same or directly proportional to the phase difference between the curves W1 and W1. As can be seen from FIG.
  • the signal VCS ' is a constant DC voltage level L2 over time.
  • the magnitude L2 of the signal VCS ' is a function of the average potential of the signals U (L1) and D (curve shape W3) and the pulse duration of the curve shape W3.
  • the signal VCS has a size L3 which is below the size L2 of the signal VCS 'by the base-emitter voltage of a transistor. From Fig. 4A it also appears that the size L2 of the signal VCS 'by an increase, for. B.
  • the curve W4 represents a periodic pulse train that corresponds to the signal RLF of FIGS. 4 and 8 corresponds.
  • the magnitude of the voltage VR is also shown.
  • the curve shape W2 level-shifted signal of the voltage-controlled oscillator
  • the curve shape W4 correspond to one another in terms of the periodicity and the pulse duration.
  • the waveform W4 (RLF) is shifted by the level shift circuit (FIG. 9) and becomes the level shift signal of the voltage controlled oscillator, which is the output signal of the level shift circuit of FIG. 4.
  • the figures 4B, 4C and 4D show a series of waveforms and potential levels which are to be considered in conjunction with the explanation of the operation of the phase comparison circuit and the AC measuring circuit according to FIG. These three figures (4B, 4C and 4D) show the curves and potential levels for the conditions that the frequency of the voltage controlled oscillator is lower, higher or equal to the clock frequency.
  • Fig. 4B shows a series of waveforms and potential levels, which are to be considered in connection with the explanation of the operation of the phase comparison circuit and the AC measuring circuit of Fig. 5 for the example that the frequency of the voltage controlled oscillator is lower than the clock frequency quenz is.
  • 5 are the waveforms W5 (clock) and W6 (level-shifted signal of the voltage-controlled oscillator).
  • the curve W5 has a smaller periodicity than the curve W6, therefore the curve W6 has a lower frequency than the curve W5.
  • the signal U is the curve shape W7.
  • the curve W7 is a periodic pulse train that was generated from the curves W5 and W6.
  • the transition of the curve shape W7 from a level below the voltage VREF to an above level corresponds to the transition of the curve shape W5 from a level below the voltage VREF to an above level.
  • the transition of the curve shape W7 from a level above the voltage VREF to an underlying level corresponds to the transition of the curve shape W6 from a level below the voltage VREF to an above level.
  • the signal B is the curve W8 and the signal C is the curve W9.
  • the curves W8 and W9 are generated from the curves W5 and W6.
  • the curves W8 and W9 have periodicities and pulse durations which depend on the logical levels of the curves W5 and W6 and on their level changes. From Fig.
  • the signal D is a DC level, which is denoted by 14.
  • the HIGH signal is a DC level designated L5.
  • the signal LOW is represented by the curve W10 and the signal EQUAL by the curve W11.
  • the level L5 corresponding to the HIGH signal is the result of the NOR operation of the curves W7 and W8 and the level L4.
  • the curve W10 corresponding to the LOW signal is the result of the NOR operation of the curve W9, the inversion of the curve W7 and the inversion of the level L4.
  • the curve W11 which corresponds to the signal EQUAL, is the result of the NOR operation of the curve profiles W10 and the level L5.
  • Fig. 4C shows a series of waveforms and potential levels which are to be considered in connection with the explanation of the operation of the phase comparison circuit and the AC measuring circuit according to Fig. 5 for the example in which the frequency of the voltage-controlled oscillator is higher than the clock frequency. 5 are the waveforms W12 (clock) and W13 (level-shifted signal of the voltage-controlled oscillator). As can be seen from FIG. 4C, the curve W12 has a longer periodicity than the curve W13, therefore the curve W13 has a higher frequency than the curve 12. From FIG. 4C it can be seen that the signal D is the curve W16 . This curve is a periodic pulse train, which is generated from the curves W12 and W13.
  • the transition of curve shape 16 from a level below voltage VREF to a higher level corresponds to the transition of curve shape W12 from a level below voltage VREF to a higher level.
  • a transition in the curve W16 from a level above the voltage VREF to a level below this voltage corresponds to the transition of the curve profile W13 from a level below the voltage VREF to a level above this voltage.
  • signal B is curve shape W14
  • signal C is curve shape W15.
  • the curves W14 and W15 are generated from the curves W12 and W13.
  • the curves W14 and W15 have periodicities and pulse durations which depend on the logical levels of the curves W12 and W13 and on the changes in these levels. From Fig.
  • the signal U is a DC level, which is denoted by L6. It can be seen from Fig. 4C that the HIGH signal is a curve represented by W17. It can also be seen from this figure that the LOW signal is represented by the level L7 and the EQUAL signal is represented by the curve shape W18.
  • the curve W17 which corresponds to the signal HIGH, is the result of a NOR operation of the curves W16 and W14 and the level L6.
  • the level L7 which corresponds to the signal LOW, is the result of a NOR operation of the curve shape W15, the inverted curve shape W16 and the inverted level L6.
  • the curve shape W18 which corresponds to the signal SAME, is the result of the NOR operation of the curve shape W17 and the level L7.
  • Fig. 4D shows a series of waveforms and potential levels, which are to be considered in connection with the explanation of the operation of the phase comparison circuit and the AC measuring circuit according to Fig. 5 in the event that the frequency of the voltage controlled oscillator is equal to the clock frequency.
  • the input signals for the phase comparison circuit according to FIG. 5 are the curve profile W19 (clock) and the curve profile 20 (level-shifted signal of the voltage-controlled oscillator).
  • the curve W19 has the same periodicity as the curve W20, therefore the curve W20 has the same frequency as the curve W19.
  • FIG. 4D shows that the signal U is the curve W21 and that from the curves W19 and W20 was generated.
  • a transition from a level below the voltage VREF to an overlying level corresponds to a transition of the curve profile W19 from a level below the voltage VREF to an above level.
  • the transition from a level above the voltage VREF to an underlying level corresponds to the transition of the curve profile W20 from a level below the voltage VREF to an overlying level.
  • signal B is curve shape W22
  • signal C is curve shape W23.
  • the curves W22 and W23 are generated from the curves W19 and W20.
  • the curves W22 and W23 have periodicities and pulse durations which depend on the logical levels of the curves W19 and W20 and their changes. From Fig.
  • the signal D is a DC level, which is designated L8. It can also be seen from FIG. 4D that the HIGH signal is a DC current level designated L9. It can also be seen that the LOW signal is represented by level L10 and the EQUAL signal is represented by level L11. As can be seen from the earlier explanation of the AC measuring circuit, the level L9, which corresponds to the signal HIGH, is the result of a NOR operation of the curves W21 and W22 and the level L8. The level L10, which corresponds to the signal LOW, is the result of the NOR combination of the curve shape W23, the inversion of the curve shape W21 and the inversion of the level L8. The level L11, which corresponds to the signal SAME, is the result of a NOR operation of the levels L10 and L9.
  • the signal VCS (L3) is the output of the buffer circuit of the regulator for the signal delay shown in FIG.
  • this output signal VCS is used to determine the point on the curve. which represents the gate signal delay as a function of power, at which the logic circuits operate. This variable is therefore decisive for the constant switching speed or gate signal delay of the logic circuits which receive the signal VCS.
  • Fig. 13 shows the circuit of the voltage controlled oscillator used, which is constructed in transistor-transistor logic.
  • the input signal VCS to the circuit controls the power in each logic gate (Fig. 14).
  • VCS voltage controlled oscillator
  • changing the power in the logic gates of the voltage controlled oscillator results in a frequency change in the signal RLF.
  • Implementation by transistor-transistor logic in this preferred embodiment may make the level shift circuit (Fig. 9) unnecessary for changing the voltage levels of the RLF signal. If a level shift circuit is not required, as can be easily determined by a person skilled in the art, the signal RLF replaces the level shifted signal of the voltage controlled oscillator as an input signal for the 0 phase comparison circuit (FIG. 5).
  • the VR signal and the level-shifted signal of the voltage controlled oscillator would be removed from the circuit since they are no longer required.
  • the new level shift circuit may not require the VR signal to generate a level-shifted oscillator signal that is compatible with the comparison circuit.
  • Experts are also known. that the use of transistor-transistor logic or any other logic in the comparison circuit may require additional circuits for the signals U and D (Fig. 4) to appear as signals with the correct source impedances and / or voltage / current levels and / or temperature responses and so that corrections can be made to the power supply so that the control circuit (Fig. 4) works correctly for the signal delay.
  • FIG. 14 is an example of a transistor-transistor logic gate that can be used in the voltage controlled oscillator of FIG. 13. Other known configurations of transistor-transistor logic can also be used.
  • the signal VCS generated by the buffer circuit or the power amplifier (FIG. 7) passes to all logic gates of the voltage-controlled oscillator (FIG. 13) and to the logic gates in the remaining part of the semiconductor chip, not shown. which may or may not include the 0 comparison circuit (FIG. 5).
  • the control signal VCS changes the power in the logic gate (Fig. 14). As the VCS signal increases, the power supplied to the logic gate increases, resulting in a decrease in the gate signal delay.
  • FIG. 15 shows the voltage-controlled oscillator used in the configuration of the integrated injection logic (FL).
  • the input signal to the circuit the VCS signal in the logic gate of Fig. 16 or the VCS signal in the logic gate of Fig. 17, controls the power in each logic gate.
  • the level shift circuit is it required or not, the level-shifted signal of the voltage controlled oscillator and / or the signal VR may or may not be required, and additional circuitry for proper operation of the signal delay controller (FIG. 4) may or may not be necessary.
  • the signal delay controller FIG. 4
  • FIG. 16 and 17 show two examples of controlling the power of a 12L gate.
  • Figure 16 shows that the current through element TA is controlled by a variable voltage. VCS.
  • the voltage VCC has a fixed value, so that when the voltage of the signal VCS decreases, the power supplied to the logic gate increases, and thereby the signal delay of the logic gate decreases. As the voltage of the signal VCS increases, the power supplied to the logic gate decreases, which in turn increases the signal delay of the logic gate.
  • the signals U and D generated by the comparison circuit (FIG. 5) must be logically inverted (U and D) .
  • Fig. 17 shows a 12L gate controlled by a voltage change across element B.
  • the base of element TA is connected to ground so that when signal VCS changes, the current through element TA changes.
  • the voltage VCS signal increases, the power in the logic gate increases and its signal delay decreases.
  • the voltage of the VCS signal decreases, the power supplied to the logic gate also decreases, and with it the signal delay.
  • the voltage VCS is not distributed to the voltage controlled oscillator and the remaining logic gates on the semiconductor chip. Instead, the signal VCS "is distributed to the voltage controlled oscillator and the remaining logic gates on the semiconductor chip.
  • Fig. 18 shows the circuit of a voltage controlled oscillator that can be used in an embodiment with field effect transistors.
  • the input signal VCS controls the power that is supplied to each logic gate (Fig. 19).
  • a change in the power supplied to the gates of the voltage controlled oscillator results in a change in the frequency of the signal RLF.
  • Increasing the power supplied to the logic gate decreases the signal delay and decreasing the power supplied to the logic gate increases its signal delay.
  • the switching speed can be set or regulated by changing the power supplied to the circuit.
  • the device by which the power can be varied is brought about by a feedback loop which essentially contains the signal of an oscillator (which is composed of the gates to be controlled), a reference signal (clock), a device for comparing the reference and Oscillator signals that generate an error signal and a device for converting the error signal into the appropriate control signal.
  • a feedback loop which essentially contains the signal of an oscillator (which is composed of the gates to be controlled), a reference signal (clock), a device for comparing the reference and Oscillator signals that generate an error signal and a device for converting the error signal into the appropriate control signal.
  • the oscillator can be constructed in any way from a number of ways known to those skilled in the art. The use of a voltage controlled oscillator has been described for explanation. A clock signal was selected as the reference signal.
  • the comparison circuit which performs the function of a frequency / voltage converter or a frequency / current converter, can be any device known to the person skilled in the art, such as a pulse width modulator, D flip-flops, digital-to-analog converter or phase locked loops.
  • a phase comparison circuit operating as a phase locked loop has been described in particularly detail.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Logic Circuits (AREA)
  • Electronic Switches (AREA)
EP82100160A 1981-01-29 1982-01-12 Schaltung zum Angleichen der Signalverzögerungszeiten von miteinander verbundenen Halbleiterschaltungen Expired EP0057351B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US06/229,417 US4383216A (en) 1981-01-29 1981-01-29 AC Measurement means for use with power control means for eliminating circuit to circuit delay differences
US229417 1981-01-29

Publications (3)

Publication Number Publication Date
EP0057351A2 EP0057351A2 (de) 1982-08-11
EP0057351A3 EP0057351A3 (en) 1982-09-01
EP0057351B1 true EP0057351B1 (de) 1984-07-04

Family

ID=22861163

Family Applications (1)

Application Number Title Priority Date Filing Date
EP82100160A Expired EP0057351B1 (de) 1981-01-29 1982-01-12 Schaltung zum Angleichen der Signalverzögerungszeiten von miteinander verbundenen Halbleiterschaltungen

Country Status (4)

Country Link
US (1) US4383216A (ja)
EP (1) EP0057351B1 (ja)
JP (1) JPS57140033A (ja)
DE (1) DE3260302D1 (ja)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4939389A (en) * 1988-09-02 1990-07-03 International Business Machines Corporation VLSI performance compensation for off-chip drivers and clock generation
US5337254A (en) * 1991-12-16 1994-08-09 Hewlett-Packard Company Programmable integrated circuit output pad
US5254891A (en) * 1992-04-20 1993-10-19 International Business Machines Corporation BICMOS ECL circuit suitable for delay regulation
JP3754070B2 (ja) * 1994-02-15 2006-03-08 ラムバス・インコーポレーテッド 遅延ロック・ループ
US5794019A (en) * 1997-01-22 1998-08-11 International Business Machines Corp. Processor with free running clock with momentary synchronization to subsystem clock during data transfers
US5959481A (en) * 1997-02-18 1999-09-28 Rambus Inc. Bus driver circuit including a slew rate indicator circuit having a one shot circuit
US6002280A (en) * 1997-04-24 1999-12-14 Mitsubishi Semiconductor America, Inc. Adaptable output phase delay compensation circuit and method thereof
US7256628B2 (en) * 2003-01-29 2007-08-14 Sun Microsystems, Inc. Speed-matching control method and circuit
US7330080B1 (en) 2004-11-04 2008-02-12 Transmeta Corporation Ring based impedance control of an output driver
KR100803360B1 (ko) * 2006-09-14 2008-02-14 주식회사 하이닉스반도체 Ｐｌｌ 회로 및 그 제어 방법
US8564411B2 (en) * 2006-12-04 2013-10-22 Michelin Recherche Et Technique Back-door data synchronization for a multiple remote measurement system
CN104932305B (zh) * 2015-05-29 2017-11-21 福州瑞芯微电子股份有限公司 采样延时调整方法及装置

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4818671B1 (ja) * 1969-06-06 1973-06-07
DE2021824C3 (de) * 1970-05-05 1980-08-14 Ibm Deutschland Gmbh, 7000 Stuttgart Monolithische Halbleiterschaltung
US3602799A (en) * 1970-06-24 1971-08-31 Westinghouse Electric Corp Temperature stable constant current source
DE2060504C3 (de) * 1970-12-09 1973-08-30 Itt Ind Gmbh Deutsche Monolithisch integrierbare Schaltungsanordnung zum Ansteuern eines oder mehrerer als stromkonstanthaltende Elemente angeordneter Transistoren
JPS5033753B1 (ja) * 1971-02-05 1975-11-01
US3794861A (en) * 1972-01-28 1974-02-26 Advanced Memory Syst Inc Reference voltage generator circuit
US4145621A (en) * 1972-03-04 1979-03-20 Ferranti Limited Transistor logic circuits
US3743850A (en) * 1972-06-12 1973-07-03 Motorola Inc Integrated current supply circuit
US3803471A (en) * 1972-12-22 1974-04-09 Allis Chalmers Variable time ratio control having power switch which does not require current equalizing means
US3808468A (en) * 1972-12-29 1974-04-30 Ibm Bootstrap fet driven with on-chip power supply
US3978473A (en) * 1973-05-01 1976-08-31 Analog Devices, Inc. Integrated-circuit digital-to-analog converter
US4029974A (en) * 1975-03-21 1977-06-14 Analog Devices, Inc. Apparatus for generating a current varying with temperature
US4004164A (en) * 1975-12-18 1977-01-18 International Business Machines Corporation Compensating current source
US4100431A (en) * 1976-10-07 1978-07-11 Motorola, Inc. Integrated injection logic to linear high impedance current interface
US4160934A (en) * 1977-08-11 1979-07-10 Bell Telephone Laboratories, Incorporated Current control circuit for light emitting diode
US4172992A (en) * 1978-07-03 1979-10-30 National Semiconductor Corporation Constant current control circuit
DE2855724A1 (de) * 1978-12-22 1980-07-03 Ibm Deutschland Verfahren und vorrichtung zur angleichung der unterschiedlichen signalverzoegerungszeiten von halbleiterchips
US4346343A (en) * 1980-05-16 1982-08-24 International Business Machines Corporation Power control means for eliminating circuit to circuit delay differences and providing a desired circuit delay

Also Published As

Publication number Publication date
EP0057351A2 (de) 1982-08-11
JPS57140033A (en) 1982-08-30
EP0057351A3 (en) 1982-09-01
US4383216A (en) 1983-05-10
JPH0315381B2 (ja) 1991-02-28
DE3260302D1 (en) 1984-08-09

Similar Documents

Publication Publication Date Title
EP0046482B1 (de) Schaltung zum Angleichen der Signalverzögerungszeiten von untereinander verbundenen Halbleiterchips
DE69120562T2 (de) Subnanosekunde kalibrierte Verzögerungsleitungsstruktur
DE4445311C2 (de) Zeitsignal-Erzeugungsschaltung
DE2541131C2 (de) Schaltungsanordnung zum Konstanthalten der Schaltverzögerung von FET-Inverterstufen in einer integrierten Schaltung
DE68924394T2 (de) Vorrichtung zum Erzeugen einer Referenzspannung für einen eine kapazitive Bootstrapschaltung enthaltenden Schalter.
DE4342266C2 (de) Taktgenerator sowie Phasenkomparator zur Verwendung in einem solchen Taktgenerator
EP0057351B1 (de) Schaltung zum Angleichen der Signalverzögerungszeiten von miteinander verbundenen Halbleiterschaltungen
DE3924593A1 (de) Verzoegerungseinrichtung
DE3733554A1 (de) Pll-verzoegerungsschaltung
DE2422653C2 (de) Integrierte Halbleiteranordnung mit Feldeffekt-Transistoren
DE3881261T2 (de) Phasenverriegelter Datendetektor.
DE3688433T2 (de) Optischer speicher mit einem bistabilen halbleiterlaser und zwei injektionsstromquellen zur individuellen kontrolle de bistabilitaet.
DE102014119097A1 (de) Spannungsregler mit schneller übergangsreaktion
DE19725459A1 (de) Von externer Spannung unabhängiger Sperrvorspannungspegeldetektor
DE2648560C2 (de) Synchronisierung von Taktsignalen mit Eingangssignalen
DE112018005269B4 (de) Differenzladungspumpe
EP0460274B1 (de) Verfahren und Schaltungsanordnung für einen Phasenkomparator
DE2008253A1 (de) Treiberstufe
DE69202304T2 (de) Phasenregelschleife mit einer die Energie aufrechterhaltenden gesteuerten Ladungspumpe für schnelle Kanalumschaltung.
DE2945697A1 (de) Regelungsschaltung zur konstanthaltung der geschwindigkeit eines gleichstrommotors
DE2429183C3 (de) Schaltungsanordnung zum Erzeugen einer synchronisierten periodischen Spannung
DE102019207959A1 (de) Schaltung und verfahren zur erzeugung einer linearen verzögerung
DE2805051C2 (de) Phasenvergleichs-Schaltanordnung
DE3786741T2 (de) Digitalimpulssignalgenerator und Spannungsreglerkreis.
DE10136320B4 (de) Anordnung und Verfahren zum Umschalten von Transistoren

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

PUAL Search report despatched

Free format text: ORIGINAL CODE: 0009013

AK Designated contracting states

Designated state(s): DE FR GB IT

AK Designated contracting states

Designated state(s): DE FR GB IT

17P Request for examination filed

Effective date: 19821116

ITF It: translation for a ep patent filed

Owner name: IBM - DR. ALFREDO BRAVI

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

AK Designated contracting states

Designated state(s): DE FR GB IT

REF Corresponds to:

Ref document number: 3260302

Country of ref document: DE

Date of ref document: 19840809

ET Fr: translation filed
PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

26N No opposition filed
ITTA It: last paid annual fee
PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: DE

Payment date: 19920121

Year of fee payment: 11

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: GB

Payment date: 19921222

Year of fee payment: 12

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: FR

Payment date: 19921223

Year of fee payment: 12

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: DE

Effective date: 19931001

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: GB

Effective date: 19940112

GBPC Gb: european patent ceased through non-payment of renewal fee

Effective date: 19940112

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: FR

Effective date: 19940930

REG Reference to a national code

Ref country code: FR

Ref legal event code: ST