EP0057351A3 - Circuit for delay normalisation of interconnected semiconductor circuits - Google Patents

Circuit for delay normalisation of interconnected semiconductor circuits Download PDF

Info

Publication number: EP0057351A3
Authority: EP; European Patent Office
Prior art keywords: normalisation; delay; circuit; semiconductor circuits; interconnected semiconductor
Prior art date: 1981-01-29
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.): Granted

Application number

EP82100160A

Other languages

German (de)

Other versions

EP0057351B1 (en

EP0057351A2 (en

Inventor

Jack Arthur Dorler

Michael Owen Jenkins

Joseph Michael Mosley

Stephen Douglas Weitzel

Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)

International Business Machines Corp

Original Assignee

International Business Machines Corp

Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)

1981-01-29

Filing date

1982-01-12

Publication date

1982-09-01

1982-01-12 Application filed by International Business Machines Corp filed Critical International Business Machines Corp

1982-08-11 Publication of EP0057351A2 publication Critical patent/EP0057351A2/en

1982-09-01 Publication of EP0057351A3 publication Critical patent/EP0057351A3/en

1984-07-04 Application granted granted Critical

1984-07-04 Publication of EP0057351B1 publication Critical patent/EP0057351B1/en

Status Expired legal-status Critical Current

Links

Classifications

- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/462—Regulating voltage or current wherein the variable actually regulated by the final control device is dc as a function of the requirements of the load, e.g. delay, temperature, specific voltage/current characteristic
- G05F1/466—Sources with reduced influence on propagation delay

Landscapes

Engineering & Computer Science (AREA)
Physics & Mathematics (AREA)
Electromagnetism (AREA)
General Physics & Mathematics (AREA)
Radar, Positioning & Navigation (AREA)
Automation & Control Theory (AREA)
Semiconductor Integrated Circuits (AREA)
Logic Circuits (AREA)
Electronic Switches (AREA)

EP82100160A 1981-01-29 1982-01-12 Circuit for delay normalisation of interconnected semiconductor circuits Expired EP0057351B1 (en)

Applications Claiming Priority (2)

Application Number	Priority Date	Filing Date	Title
US06/229,417 US4383216A (en)	1981-01-29	1981-01-29	AC Measurement means for use with power control means for eliminating circuit to circuit delay differences
US229417		1981-01-29

Publications (3)

Publication Number	Publication Date
EP0057351A2 EP0057351A2 (en)	1982-08-11
EP0057351A3 true EP0057351A3 (en)	1982-09-01
EP0057351B1 EP0057351B1 (en)	1984-07-04

Family

ID=22861163

Family Applications (1)

Application Number	Title	Priority Date	Filing Date
EP82100160A Expired EP0057351B1 (en)	1981-01-29	1982-01-12	Circuit for delay normalisation of interconnected semiconductor circuits

Country Status (4)

Country	Link
US (1)	US4383216A (en)
EP (1)	EP0057351B1 (en)
JP (1)	JPS57140033A (en)
DE (1)	DE3260302D1 (en)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
US4939389A (en) *	1988-09-02	1990-07-03	International Business Machines Corporation	VLSI performance compensation for off-chip drivers and clock generation
US5337254A (en) *	1991-12-16	1994-08-09	Hewlett-Packard Company	Programmable integrated circuit output pad
US5254891A (en) *	1992-04-20	1993-10-19	International Business Machines Corporation	BICMOS ECL circuit suitable for delay regulation
JP3754070B2 (en) *	1994-02-15	2006-03-08	ラムバス・インコーポレーテッド	Delay lock loop
US5794019A (en) *	1997-01-22	1998-08-11	International Business Machines Corp.	Processor with free running clock with momentary synchronization to subsystem clock during data transfers
US5959481A (en) *	1997-02-18	1999-09-28	Rambus Inc.	Bus driver circuit including a slew rate indicator circuit having a one shot circuit
US6002280A (en) *	1997-04-24	1999-12-14	Mitsubishi Semiconductor America, Inc.	Adaptable output phase delay compensation circuit and method thereof
US7256628B2 (en) *	2003-01-29	2007-08-14	Sun Microsystems, Inc.	Speed-matching control method and circuit
US7330080B1 (en)	2004-11-04	2008-02-12	Transmeta Corporation	Ring based impedance control of an output driver
KR100803360B1 (en) *	2006-09-14	2008-02-14	주식회사 하이닉스반도체	Pll circuit and method for controlling the same
US8564411B2 (en) *	2006-12-04	2013-10-22	Michelin Recherche Et Technique	Back-door data synchronization for a multiple remote measurement system
CN104932305B (en) *	2015-05-29	2017-11-21	福州瑞芯微电子股份有限公司	Sampling time delay method of adjustment and device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
EP0012839A1 (en) *	1978-12-22	1980-07-09	International Business Machines Corporation	Method and device for adjusting the different time delays of semiconductor chips by changing the working voltage
EP0046482A1 (en) *	1980-05-16	1982-03-03	International Business Machines Corporation	Circuit for delay normalisation of interconnected semiconductor chips

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
JPS4818671B1 (en) *	1969-06-06	1973-06-07
DE2021824C3 (en) *	1970-05-05	1980-08-14	Ibm Deutschland Gmbh, 7000 Stuttgart	Monolithic semiconductor circuit
US3602799A (en) *	1970-06-24	1971-08-31	Westinghouse Electric Corp	Temperature stable constant current source
DE2060504C3 (en) *	1970-12-09	1973-08-30	Itt Ind Gmbh Deutsche	Monolithically integrable circuit arrangement for controlling one or more transistors arranged as elements that maintain a constant current
JPS5033753B1 (en) *	1971-02-05	1975-11-01
US3794861A (en) *	1972-01-28	1974-02-26	Advanced Memory Syst Inc	Reference voltage generator circuit
US4145621A (en) *	1972-03-04	1979-03-20	Ferranti Limited	Transistor logic circuits
US3743850A (en) *	1972-06-12	1973-07-03	Motorola Inc	Integrated current supply circuit
US3803471A (en) *	1972-12-22	1974-04-09	Allis Chalmers	Variable time ratio control having power switch which does not require current equalizing means
US3808468A (en) *	1972-12-29	1974-04-30	Ibm	Bootstrap fet driven with on-chip power supply
US3978473A (en) *	1973-05-01	1976-08-31	Analog Devices, Inc.	Integrated-circuit digital-to-analog converter
US4029974A (en) *	1975-03-21	1977-06-14	Analog Devices, Inc.	Apparatus for generating a current varying with temperature
US4004164A (en) *	1975-12-18	1977-01-18	International Business Machines Corporation	Compensating current source
US4100431A (en) *	1976-10-07	1978-07-11	Motorola, Inc.	Integrated injection logic to linear high impedance current interface
US4160934A (en) *	1977-08-11	1979-07-10	Bell Telephone Laboratories, Incorporated	Current control circuit for light emitting diode
US4172992A (en) *	1978-07-03	1979-10-30	National Semiconductor Corporation	Constant current control circuit

1981
- 1981-01-29 US US06/229,417 patent/US4383216A/en not_active Expired - Lifetime
- 1981-12-11 JP JP56198691A patent/JPS57140033A/en active Granted
1982
- 1982-01-12 EP EP82100160A patent/EP0057351B1/en not_active Expired
- 1982-01-12 DE DE8282100160T patent/DE3260302D1/en not_active Expired

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
EP0012839A1 (en) *	1978-12-22	1980-07-09	International Business Machines Corporation	Method and device for adjusting the different time delays of semiconductor chips by changing the working voltage
EP0046482A1 (en) *	1980-05-16	1982-03-03	International Business Machines Corporation	Circuit for delay normalisation of interconnected semiconductor chips

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
IBM Technical Disclosure Bulletin, Band 16, Nr. 7, Dezember 1973 New York (US) H.H. BERGER: "Switching Speed Control in Digital Circuits" seiten 2304-2305 * ingesamt * *
IEEE International Solid-State Circuits Conference, Digest of Technical Papers, Band 19, Nr. 19, 18. Februar 1976, New York (US) G.M. BLASER u.a.: "Substrate and Load Gate Voltage Compensation" seiten 56, 57 * insgesamt * *

Also Published As

Publication number	Publication date
EP0057351B1 (en)	1984-07-04
EP0057351A2 (en)	1982-08-11
JPS57140033A (en)	1982-08-30
US4383216A (en)	1983-05-10
JPH0315381B2 (en)	1991-02-28
DE3260302D1 (en)	1984-08-09

Legal Events

Date	Code	Title	Description
1982-06-11	PUAI	Public reference made under article 153(3) epc to a published international application that has entered the european phase	Free format text: ORIGINAL CODE: 0009012
1982-06-28	PUAL	Search report despatched	Free format text: ORIGINAL CODE: 0009013
1982-08-11	AK	Designated contracting states	Designated state(s): DE FR GB IT
1982-09-01	AK	Designated contracting states	Designated state(s): DE FR GB IT
1983-01-26	17P	Request for examination filed	Effective date: 19821116
1984-03-15	ITF	It: translation for a ep patent filed	Owner name: IBM - DR. ALFREDO BRAVI
1984-05-04	GRAA	(expected) grant	Free format text: ORIGINAL CODE: 0009210
1984-07-04	AK	Designated contracting states	Designated state(s): DE FR GB IT
1984-08-09	REF	Corresponds to:	Ref document number: 3260302 Country of ref document: DE Date of ref document: 19840809
1984-08-24	ET	Fr: translation filed
1985-05-10	PLBE	No opposition filed within time limit	Free format text: ORIGINAL CODE: 0009261
1985-05-10	STAA	Information on the status of an ep patent application or granted ep patent	Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT
1985-07-10	26N	No opposition filed
1991-01-31	ITTA	It: last paid annual fee
1992-01-21	PGFP	Annual fee paid to national office [announced via postgrant information from national office to epo]	Ref country code: DE Payment date: 19920121 Year of fee payment: 11
1992-12-22	PGFP	Annual fee paid to national office [announced via postgrant information from national office to epo]	Ref country code: GB Payment date: 19921222 Year of fee payment: 12
1992-12-23	PGFP	Annual fee paid to national office [announced via postgrant information from national office to epo]	Ref country code: FR Payment date: 19921223 Year of fee payment: 12
1993-10-01	PG25	Lapsed in a contracting state [announced via postgrant information from national office to epo]	Ref country code: DE Effective date: 19931001
1994-01-12	PG25	Lapsed in a contracting state [announced via postgrant information from national office to epo]	Ref country code: GB Effective date: 19940112
1994-09-07	GBPC	Gb: european patent ceased through non-payment of renewal fee	Effective date: 19940112
1994-09-30	PG25	Lapsed in a contracting state [announced via postgrant information from national office to epo]	Ref country code: FR Effective date: 19940930
1994-11-25	REG	Reference to a national code	Ref country code: FR Ref legal event code: ST

Publication	Publication Date	Title
DE3175288D1 (en)	1986-10-16	Circuit for delay normalisation of interconnected semiconductor chips
DE3279013D1 (en)	1988-10-13	Semiconductor integrated circuit
GB2075752B (en)	1984-05-23	Semiconductor integrated circuits
GB8500176D0 (en)	1985-02-13	Semiconductor integrated circuit
DE3279429D1 (en)	1989-03-09	Semiconductor integrated memory circuit
JPS5588428A (en)	1980-07-04	Signal delay equalizer circuit for semiconductor chip
DE3176601D1 (en)	1988-02-11	Semiconductor memory circuit
DE3260302D1 (en)	1984-08-09	Circuit for delay normalisation of interconnected semiconductor circuits
GB2091459B (en)	1985-09-11	Semiconductor integrated circuit
GB2126782B (en)	1986-06-25	Semiconductor integrated circuit devices
GB8329430D0 (en)	1983-12-07	Semiconductor circuit element
DE3272424D1 (en)	1986-09-11	Semiconductor integrated circuit
IE810294L (en)	1981-08-16	Semiconductor memory circuit
EP0073726A3 (en)	1984-11-07	Semi-conductor memory circuit
DE3275613D1 (en)	1987-04-09	Semiconductor circuit
DE3264963D1 (en)	1985-09-05	Semiconductor integrated circuit
DE3380891D1 (en)	1989-12-28	Semiconductor integrated circuit
GB2154061B (en)	1986-04-09	Methods of manufacturing semiconductor circuit devices
JPS57178406A (en)	1982-11-02	Semiconductor circuit
EP0239913A3 (en)	1988-03-30	Semiconductor memory circuit
GB8301731D0 (en)	1983-02-23	Semiconductor integrated circuit
GB8317520D0 (en)	1983-08-03	Semiconductor switching circuits
GB2135549B (en)	1985-03-20	Semiconductor integrated circuits
SG40987G (en)	1987-07-17	Methods of manufacturing semiconductor circuit devices
GB2085653B (en)	1984-06-20	Semiconductor logic circuits