DE69929100D1 - Teilsilizidierungsverfahren zur Bildung von flachen Source/Drain-Übergängen - Google Patents

Teilsilizidierungsverfahren zur Bildung von flachen Source/Drain-Übergängen

Info

Publication number
DE69929100D1
DE69929100D1 DE69929100T DE69929100T DE69929100D1 DE 69929100 D1 DE69929100 D1 DE 69929100D1 DE 69929100 T DE69929100 T DE 69929100T DE 69929100 T DE69929100 T DE 69929100T DE 69929100 D1 DE69929100 D1 DE 69929100D1
Authority
DE
Germany
Prior art keywords
shallow source
drain junctions
form shallow
siliciding process
partial
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69929100T
Other languages
English (en)
Other versions
DE69929100T2 (de
Inventor
Jer-Shen Maa
Sheng Teng Hsu
Chien-Hsiung Peng
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Sharp Microelectronics Technology Inc
Original Assignee
Sharp Corp
Sharp Microelectronics Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp, Sharp Microelectronics Technology Inc filed Critical Sharp Corp
Application granted granted Critical
Publication of DE69929100D1 publication Critical patent/DE69929100D1/de
Publication of DE69929100T2 publication Critical patent/DE69929100T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
    • H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
DE69929100T 1998-02-13 1999-01-22 Teilsilicidierungsverfahren zur Bildung von flachen Source/Drain-Übergängen Expired - Fee Related DE69929100T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/023,383 US6071782A (en) 1998-02-13 1998-02-13 Partial silicidation method to form shallow source/drain junctions
US23383 1998-02-13

Publications (2)

Publication Number Publication Date
DE69929100D1 true DE69929100D1 (de) 2006-02-02
DE69929100T2 DE69929100T2 (de) 2006-08-24

Family

ID=21814770

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69929100T Expired - Fee Related DE69929100T2 (de) 1998-02-13 1999-01-22 Teilsilicidierungsverfahren zur Bildung von flachen Source/Drain-Übergängen

Country Status (6)

Country Link
US (2) US6071782A (de)
EP (1) EP0936664B1 (de)
JP (1) JP3723359B2 (de)
KR (1) KR100397913B1 (de)
DE (1) DE69929100T2 (de)
TW (1) TW400557B (de)

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US6235598B1 (en) 1998-11-13 2001-05-22 Intel Corporation Method of using thick first spacers to improve salicide resistance on polysilicon gates
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US6251762B1 (en) 1999-12-09 2001-06-26 Intel Corporation Method and device for improved salicide resistance on polysilicon gates
US6265271B1 (en) * 2000-01-24 2001-07-24 Taiwan Semiconductor Manufacturing Company Integration of the borderless contact salicide process
US6251779B1 (en) * 2000-06-01 2001-06-26 United Microelectronics Corp. Method of forming a self-aligned silicide on a semiconductor wafer
US6706631B1 (en) * 2000-07-25 2004-03-16 Advanced Micro Devices, Inc. Method of controlling sheet resistance of metal silicide regions by controlling the salicide strip time
JP3305301B2 (ja) * 2000-08-02 2002-07-22 松下電器産業株式会社 電極構造体の形成方法及び半導体装置の製造方法
US6368963B1 (en) * 2000-09-12 2002-04-09 Advanced Micro Devices, Inc. Passivation of semiconductor device surfaces using an iodine/ethanol solution
US6521515B1 (en) 2000-09-15 2003-02-18 Advanced Micro Devices, Inc. Deeply doped source/drains for reduction of silicide/silicon interface roughness
CN1633703A (zh) * 2000-12-06 2005-06-29 先进微装置公司 使用一步快速热退火工艺及尾端处理形成硅化镍的方法
US6605513B2 (en) * 2000-12-06 2003-08-12 Advanced Micro Devices, Inc. Method of forming nickel silicide using a one-step rapid thermal anneal process and backend processing
US6468900B1 (en) * 2000-12-06 2002-10-22 Advanced Micro Devices, Inc. Dual layer nickel deposition using a cobalt barrier to reduce surface roughness at silicide/junction interface
KR100545538B1 (ko) * 2001-01-04 2006-01-25 인피네온 테크놀로지스 아게 반도체 소자의 도핑 영역과의 컨택트 제조 방법
KR20030002867A (ko) * 2001-06-30 2003-01-09 주식회사 하이닉스반도체 반도체 소자의 제조 방법
KR100400785B1 (ko) * 2001-12-28 2003-10-08 주식회사 하이닉스반도체 반도체 소자의 살리사이드 형성 방법
JP3657915B2 (ja) * 2002-01-31 2005-06-08 株式会社東芝 半導体装置および半導体装置の製造方法
KR100739837B1 (ko) * 2003-02-19 2007-07-13 마쯔시다덴기산교 가부시키가이샤 불순물 도입 방법 및 불순물 도입 장치
US7005376B2 (en) 2003-07-07 2006-02-28 Advanced Micro Devices, Inc. Ultra-uniform silicides in integrated circuit technology
DE10345374B4 (de) * 2003-09-30 2006-08-10 Advanced Micro Devices, Inc., Sunnyvale Halbleiterbauteil mit einem Nickel/Kobaltsilizidgebiet, das in einem Siliziumgebiet gebildet ist und Verfahren zu seiner Herstellung
JP4979234B2 (ja) * 2003-10-09 2012-07-18 パナソニック株式会社 接合の形成方法およびこれを用いて形成された被処理物
KR100558006B1 (ko) * 2003-11-17 2006-03-06 삼성전자주식회사 니켈 샐리사이드 공정들 및 이를 사용하여 반도체소자를제조하는 방법들
JP3879003B2 (ja) * 2004-02-26 2007-02-07 国立大学法人名古屋大学 シリサイド膜の作製方法
US7105429B2 (en) * 2004-03-10 2006-09-12 Freescale Semiconductor, Inc. Method of inhibiting metal silicide encroachment in a transistor
CN1993806A (zh) * 2004-06-04 2007-07-04 松下电器产业株式会社 引入杂质的方法
KR100840786B1 (ko) * 2006-07-28 2008-06-23 삼성전자주식회사 저저항 게이트 전극을 구비하는 반도체 장치 및 이의제조방법
JP5214261B2 (ja) 2008-01-25 2013-06-19 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US20090201075A1 (en) * 2008-02-12 2009-08-13 Yannis Tsividis Method and Apparatus for MOSFET Drain-Source Leakage Reduction
US8207784B2 (en) 2008-02-12 2012-06-26 Semi Solutions, Llc Method and apparatus for MOSFET drain-source leakage reduction
JP2010028084A (ja) 2008-06-17 2010-02-04 Toshiba Corp 半導体装置の製造方法
JP5430904B2 (ja) 2008-10-15 2014-03-05 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP2010171327A (ja) 2009-01-26 2010-08-05 Toshiba Corp 半導体装置の製造方法
JP5341994B2 (ja) * 2009-06-26 2013-11-13 株式会社東芝 半導体装置の製造方法
JP5659098B2 (ja) * 2011-07-19 2015-01-28 株式会社東芝 半導体装置の製造方法
JP2013084678A (ja) * 2011-10-06 2013-05-09 Elpida Memory Inc 半導体装置の製造方法
US9806253B2 (en) 2015-11-16 2017-10-31 Samsung Electronics Co., Ltd. Method for providing a high perpendicular magnetic anisotropy layer in a magnetic junction usable in spin transfer torque magnetic devices using multiple anneals
CN111785622B (zh) * 2020-07-15 2022-10-21 上海华力集成电路制造有限公司 形成金属硅化物的退火工艺、装置及金属接触层形成方法

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Also Published As

Publication number Publication date
DE69929100T2 (de) 2006-08-24
KR19990071451A (ko) 1999-09-27
EP0936664A3 (de) 2000-04-19
US6071782A (en) 2000-06-06
JP3723359B2 (ja) 2005-12-07
TW400557B (en) 2000-08-01
EP0936664A2 (de) 1999-08-18
EP0936664B1 (de) 2005-12-28
KR100397913B1 (ko) 2003-12-18
US6218249B1 (en) 2001-04-17
JPH11251591A (ja) 1999-09-17

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