JP5659098B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP5659098B2 JP5659098B2 JP2011158052A JP2011158052A JP5659098B2 JP 5659098 B2 JP5659098 B2 JP 5659098B2 JP 2011158052 A JP2011158052 A JP 2011158052A JP 2011158052 A JP2011158052 A JP 2011158052A JP 5659098 B2 JP5659098 B2 JP 5659098B2
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- 238000004519 manufacturing process Methods 0.000 title claims description 26
- 239000004065 semiconductor Substances 0.000 title claims description 19
- 239000000758 substrate Substances 0.000 claims description 49
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 46
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 44
- 229910052710 silicon Inorganic materials 0.000 claims description 44
- 239000010703 silicon Substances 0.000 claims description 44
- RUFLMLWJRZAWLJ-UHFFFAOYSA-N nickel silicide Chemical compound [Ni]=[Si]=[Ni] RUFLMLWJRZAWLJ-UHFFFAOYSA-N 0.000 claims description 39
- 229910021334 nickel silicide Inorganic materials 0.000 claims description 39
- 229910052759 nickel Inorganic materials 0.000 claims description 23
- 239000012535 impurity Substances 0.000 claims description 20
- 238000000034 method Methods 0.000 claims description 18
- 239000013078 crystal Substances 0.000 claims description 11
- 230000015572 biosynthetic process Effects 0.000 claims description 5
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 2
- 238000009832 plasma treatment Methods 0.000 claims description 2
- 238000001816 cooling Methods 0.000 claims 1
- 230000005855 radiation Effects 0.000 claims 1
- 238000009792 diffusion process Methods 0.000 description 15
- 230000002159 abnormal effect Effects 0.000 description 6
- 239000007789 gas Substances 0.000 description 6
- PEUPIGGLJVUNEU-UHFFFAOYSA-N nickel silicon Chemical compound [Si].[Ni] PEUPIGGLJVUNEU-UHFFFAOYSA-N 0.000 description 6
- 230000008569 process Effects 0.000 description 6
- 239000007790 solid phase Substances 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 230000007246 mechanism Effects 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 238000004151 rapid thermal annealing Methods 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 230000001678 irradiating effect Effects 0.000 description 4
- 230000003071 parasitic effect Effects 0.000 description 4
- 230000004913 activation Effects 0.000 description 3
- 229910017052 cobalt Inorganic materials 0.000 description 3
- 239000010941 cobalt Substances 0.000 description 3
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000000149 penetrating effect Effects 0.000 description 3
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 2
- 238000004220 aggregation Methods 0.000 description 2
- 230000002776 aggregation Effects 0.000 description 2
- 229910052799 carbon Inorganic materials 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 239000010453 quartz Substances 0.000 description 2
- 238000001953 recrystallisation Methods 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- CEPICIBPGDWCRU-UHFFFAOYSA-N [Si].[Hf] Chemical compound [Si].[Hf] CEPICIBPGDWCRU-UHFFFAOYSA-N 0.000 description 1
- 238000005280 amorphization Methods 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- QZPSXPBJTPJTSZ-UHFFFAOYSA-N aqua regia Chemical compound Cl.O[N+]([O-])=O QZPSXPBJTPJTSZ-UHFFFAOYSA-N 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 125000001475 halogen functional group Chemical group 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- 230000036632 reaction speed Effects 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Ceramic Engineering (AREA)
- Element Separation (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Recrystallisation Techniques (AREA)
- Electrodes Of Semiconductors (AREA)
- Thin Film Transistor (AREA)
Description
図1及び図2を用いて本実施形態の製造方法を説明する。この図1及び図2は、MOSFET(Metal Oxide Semiconductor Field Effect Transistor)のチャネル方向に沿った断面に対応し、シリコン基板101上に設けられるMOSFETの製造工程を示す。それぞれの図において、左側が、P型MOSFETが形成されるP型MOSFET領域10であり、右側が、N型MOSFETが形成されるN型MOSFET領域11である。ここでは、MOSFETの製造方法を例に説明するが、本発明は、このような半導体装置に限られるものではなく、他の半導体装置であっても良い。
図8から図10を用いて、第2の実施形態にかかるFin型トランジスタ(FinFET)の製造方法を説明する。FinFETは、シリコン基板を短冊状に細く切り出して突起状領域を形成し(この突起状領域をFinと呼ぶ)、これにゲート電極を立体交差させることで、切り出した突起状領域の上面及び側面をチャネルとするようなMOSFETである。ここでは、N型のFinFETの製造方法について説明するが、本発明は、このような半導体装置に限られるものではなく、他の半導体装置やP型のFinFETであっても良い。
11 N型MOSFET領域
12 ゲート電極
20 製造装置
21 導波管
101、201、301 シリコン基板
102、302 STI
103 N型拡散層
104 P型拡散層
105 ゲート絶縁膜
106 金属膜
107 多結晶シリコン膜
108、109 Extension拡散層
110 ゲート側壁膜
111、112 ソース/ドレイン領域
113、114、115、203、306 アモルファス領域
117、204、308 ニッケル膜
118、119、205、309 ニッケルシリサイド膜
202 単結晶層
303 側壁膜
304 Fin
305 エピタキシャルシリコン層
307 単結晶部
Claims (4)
- シリコン基板中または基板上のシリコン層中のチャネル領域上に、ゲート絶縁膜を介してゲート電極を形成し、
前記シリコン基板または前記シリコン層に所望の不純物を注入することにより、チャネル方向に沿って前記チャネル領域を挟むように前記シリコン基板または前記シリコン層中にソース領域とドレイン領域とを形成し、
前記ソース領域及び前記ドレイン領域の表面をアモルファス化することにより、それぞれの表面に前記不純物を含むアモルファス領域を形成し、
前記アモルファス領域の上に、ニッケル膜を形成し、
マイクロ波を照射して、前記アモルファス領域と前記ニッケル膜とを反応させて前記ニッケル膜の側から前記アモルファス領域内へシリサイド化反応を進行させてニッケルシリサイド膜を形成しつつ、前記シリコン基板または前記シリコン層の側から前記ニッケル膜の側へ向けて前記アモルファス領域のアモルファスシリコンを結晶化させて前記ニッケルシリサイド膜の下方に単結晶層を形成し、
未反応の前記ニッケル膜を除去する、
ことを特徴とする半導体装置の製造方法。 - 前記マイクロ波の照射は、前記シリコン基板または前記基板の温度が150℃から350℃となるように行われることを特徴とする請求項1に記載の半導体装置の製造方法。
- 前記マイクロ波の照射は、前記シリコン基板または前記基板を冷却しながら行われることを特徴とする請求項1又は2に記載の半導体装置の製造方法。
- 前記アモルファス領域の形成は、プラズマ処理により行われることを特徴とする請求項1から3のいずれか1つに記載の半導体装置の製造方法。
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JP2011158052A JP5659098B2 (ja) | 2011-07-19 | 2011-07-19 | 半導体装置の製造方法 |
US13/415,628 US8658520B2 (en) | 2011-07-19 | 2012-03-08 | Method of manufacturing semiconductor device |
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JP2011158052A JP5659098B2 (ja) | 2011-07-19 | 2011-07-19 | 半導体装置の製造方法 |
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JP2013026333A JP2013026333A (ja) | 2013-02-04 |
JP5659098B2 true JP5659098B2 (ja) | 2015-01-28 |
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JP (1) | JP5659098B2 (ja) |
Families Citing this family (7)
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JP5856545B2 (ja) * | 2012-07-06 | 2016-02-09 | 株式会社東芝 | 半導体装置及びその製造方法 |
JP2014063897A (ja) * | 2012-09-21 | 2014-04-10 | Toshiba Corp | 半導体装置の製造方法、アニール装置及びアニール方法 |
US8872225B2 (en) * | 2012-12-20 | 2014-10-28 | Intel Corporation | Defect transferred and lattice mismatched epitaxial film |
GB201309333D0 (en) * | 2013-05-23 | 2013-07-10 | Agency Science Tech & Res | Purine diones as WNT pathway modulators |
US9093379B2 (en) * | 2013-05-29 | 2015-07-28 | International Business Machines Corporation | Silicidation blocking process using optically sensitive HSQ resist and organic planarizing layer |
US9853148B2 (en) * | 2016-02-02 | 2017-12-26 | Taiwan Semiconductor Manufacturing Company Ltd. | Power MOSFETs and methods for manufacturing the same |
FR3073976B1 (fr) * | 2017-11-23 | 2019-12-27 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Methode de fabrication de couples de transistors cmos de type " fin-fet " a basse temperature |
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TW369686B (en) * | 1993-07-27 | 1999-09-11 | Semiconductor Energy Lab Corp | Semiconductor device and process for fabricating the same |
US6051483A (en) * | 1996-11-12 | 2000-04-18 | International Business Machines Corporation | Formation of ultra-shallow semiconductor junction using microwave annealing |
JPH09321304A (ja) * | 1996-03-22 | 1997-12-12 | Seiko Epson Corp | Mos素子を含む半導体装置およびその製造方法 |
US6051283A (en) * | 1998-01-13 | 2000-04-18 | International Business Machines Corp. | Microwave annealing |
US6071782A (en) * | 1998-02-13 | 2000-06-06 | Sharp Laboratories Of America, Inc. | Partial silicidation method to form shallow source/drain junctions |
US6410430B1 (en) * | 2000-07-12 | 2002-06-25 | International Business Machines Corporation | Enhanced ultra-shallow junctions in CMOS using high temperature silicide process |
US7238557B2 (en) * | 2001-11-14 | 2007-07-03 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method of fabricating the same |
EP1719164B1 (en) * | 2004-02-19 | 2010-07-28 | Nxp B.V. | Method of manufacturing a semiconductor device |
JP2006351581A (ja) | 2005-06-13 | 2006-12-28 | Fujitsu Ltd | 半導体装置の製造方法 |
JP2009111214A (ja) | 2007-10-31 | 2009-05-21 | Renesas Technology Corp | 半導体装置及びその製造方法 |
JP2011035371A (ja) | 2009-07-07 | 2011-02-17 | Toshiba Corp | 半導体装置の製造方法及び半導体製造装置 |
JP5537102B2 (ja) | 2009-09-11 | 2014-07-02 | 株式会社東芝 | 半導体装置の製造方法 |
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JP2013026333A (ja) | 2013-02-04 |
US8658520B2 (en) | 2014-02-25 |
US20130023102A1 (en) | 2013-01-24 |
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