DE69904685T2 - Sequentielle logische Schaltung mit Betriebs- und Schlafmodus - Google Patents

Sequentielle logische Schaltung mit Betriebs- und Schlafmodus

Info

Publication number
DE69904685T2
DE69904685T2 DE69904685T DE69904685T DE69904685T2 DE 69904685 T2 DE69904685 T2 DE 69904685T2 DE 69904685 T DE69904685 T DE 69904685T DE 69904685 T DE69904685 T DE 69904685T DE 69904685 T2 DE69904685 T2 DE 69904685T2
Authority
DE
Germany
Prior art keywords
operating
logic circuit
sleep mode
sequential logic
sequential
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69904685T
Other languages
English (en)
Other versions
DE69904685D1 (de
Inventor
Tadahiko Ogawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Application granted granted Critical
Publication of DE69904685D1 publication Critical patent/DE69904685D1/de
Publication of DE69904685T2 publication Critical patent/DE69904685T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits
    • H03K3/0375—Bistable circuits provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/012—Modifications of generator to improve response time or to decrease power consumption
DE69904685T 1998-10-02 1999-10-01 Sequentielle logische Schaltung mit Betriebs- und Schlafmodus Expired - Fee Related DE69904685T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10280767A JP2000114935A (ja) 1998-10-02 1998-10-02 順序回路

Publications (2)

Publication Number Publication Date
DE69904685D1 DE69904685D1 (de) 2003-02-06
DE69904685T2 true DE69904685T2 (de) 2003-10-23

Family

ID=17629683

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69904685T Expired - Fee Related DE69904685T2 (de) 1998-10-02 1999-10-01 Sequentielle logische Schaltung mit Betriebs- und Schlafmodus

Country Status (4)

Country Link
US (1) US6310491B1 (de)
EP (1) EP0993116B1 (de)
JP (1) JP2000114935A (de)
DE (1) DE69904685T2 (de)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3587299B2 (ja) * 2000-07-12 2004-11-10 沖電気工業株式会社 半導体集積回路
US20020120843A1 (en) * 2001-02-21 2002-08-29 Goodman Steven Dale Method and system for preventing reset of a cryptographic subsystem when entering or recovering from a powered-off sleep state
US6882200B2 (en) * 2001-07-23 2005-04-19 Intel Corporation Controlling signal states and leakage current during a sleep mode
JP4974202B2 (ja) * 2001-09-19 2012-07-11 ルネサスエレクトロニクス株式会社 半導体集積回路
US6552576B1 (en) * 2002-03-12 2003-04-22 Sun Microsystems, Inc. Noise immune transmission gate
US6794914B2 (en) * 2002-05-24 2004-09-21 Qualcomm Incorporated Non-volatile multi-threshold CMOS latch with leakage control
US6850103B2 (en) * 2002-09-27 2005-02-01 Texas Instruments Incorporated Low leakage single-step latch circuit
DE10323861A1 (de) 2003-05-26 2004-12-30 Infineon Technologies Ag Integrierte Schaltung und Verfahren zum Betreiben der integrierten Schaltung, insbesondere zum Versetzen derselben in einen Stromsparmodus
US7148745B1 (en) 2003-09-25 2006-12-12 Cypress Semiconductor Corporation Sleep mode recovery
KR100539254B1 (ko) * 2004-03-13 2005-12-27 삼성전자주식회사 테스트용 스캔 체인을 이용한 반도체 장치의 슬립모드에서의 데이터 보존 회로 및 그 보존 방법
KR100733447B1 (ko) * 2005-09-28 2007-06-29 주식회사 하이닉스반도체 누설전류 방지를 위한 메모리장치의 데이터 출력 멀티플렉서
US8421502B2 (en) * 2005-11-10 2013-04-16 Intel Corporation Power reducing logic and non-destructive latch circuits and applications
GB2447944B (en) * 2007-03-28 2011-06-29 Advanced Risc Mach Ltd Reducing leakage power in low power mode
US20080303573A1 (en) * 2007-06-11 2008-12-11 Faraday Technology Corporation Data-retention latch for sleep mode application
JP2009027701A (ja) * 2007-06-20 2009-02-05 Kawasaki Microelectronics Kk 半導体集積回路
JP5327452B2 (ja) * 2009-03-13 2013-10-30 株式会社リコー 情報処理装置
US8390369B2 (en) * 2010-08-05 2013-03-05 Freescale Semiconductor, Inc. Electronic circuit and method for operating a module in a functional mode and in an idle mode
JP2011008819A (ja) * 2010-08-24 2011-01-13 Hitachi Omron Terminal Solutions Corp Ｕｓｂ機器、及びｕｓｂ接続システム
CN104639116B (zh) * 2015-02-06 2016-03-30 中国人民解放军国防科学技术大学 高速低功耗多阈值同步置位复位d型触发器
CN107885267B (zh) * 2016-09-30 2020-01-17 中芯国际集成电路制造(上海)有限公司 用于带隙电压基准电路的操作方法
CN108073209B (zh) * 2016-11-08 2020-04-07 中芯国际集成电路制造(上海)有限公司 一种带隙基准电路

Family Cites Families (12)

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Publication number Priority date Publication date Assignee Title
US3943378A (en) * 1974-08-01 1976-03-09 Motorola, Inc. CMOS synchronous binary counter
US4145761A (en) * 1978-03-09 1979-03-20 Motorola Inc. Ram retention during power up and power down
JPS6267617A (ja) * 1985-09-20 1987-03-27 Hitachi Micro Comput Eng Ltd 半導体集積回路装置
KR950009681B1 (ko) * 1988-06-30 1995-08-26 금성일렉트론주식회사 순서 선택 우선의 임의/순서 선택회로
JP3381875B2 (ja) * 1994-03-25 2003-03-04 日本電信電話株式会社 順序回路
US5528177A (en) * 1994-09-16 1996-06-18 Research Foundation Of State University Of New York Complementary field-effect transistor logic circuits for wave pipelining
JPH09270677A (ja) * 1995-09-05 1997-10-14 Mitsubishi Electric Corp フリップフロップ回路及びスキャンパス並びに記憶回路
US5712826A (en) * 1996-03-26 1998-01-27 Intel Corporation Apparatus and a method for embedding dynamic state machines in a static environment
US6043686A (en) * 1996-05-31 2000-03-28 Texas Instruments Incorporated Apparatus and method for transistor element reduction in circuits comparing serial data signals
JP3465493B2 (ja) * 1996-09-26 2003-11-10 ヤマハ株式会社 半導体集積回路
US5760608A (en) * 1996-10-21 1998-06-02 Hewlett-Packard Co. High speed, low clock load register dump circuit
ID27661A (id) * 1998-02-13 2001-04-19 Monsanto Co Komposisi yang mengandung substansi kimia eksogen dan surfaktan siloksan yang stabil disimpan

Also Published As

Publication number Publication date
DE69904685D1 (de) 2003-02-06
US6310491B1 (en) 2001-10-30
JP2000114935A (ja) 2000-04-21
EP0993116B1 (de) 2003-01-02
EP0993116A1 (de) 2000-04-12

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee