DE69832455D1 - Halbleiterspeicheranordnung - Google Patents
HalbleiterspeicheranordnungInfo
- Publication number
- DE69832455D1 DE69832455D1 DE69832455T DE69832455T DE69832455D1 DE 69832455 D1 DE69832455 D1 DE 69832455D1 DE 69832455 T DE69832455 T DE 69832455T DE 69832455 T DE69832455 T DE 69832455T DE 69832455 D1 DE69832455 D1 DE 69832455D1
- Authority
- DE
- Germany
- Prior art keywords
- storage device
- semiconductor storage
- semiconductor
- storage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/408—Address circuits
- G11C11/4085—Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4094—Bit-line management or control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
- G11C7/1039—Read-write modes for single port memories, i.e. having either a random port or a serial port using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/10—Decoders
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/005—Transfer gates, i.e. gates coupling the sense amplifier output to data lines, I/O lines or global bit lines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/06—Sense amplifier related aspects
- G11C2207/065—Sense amplifier drivers
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Dram (AREA)
Applications Claiming Priority (7)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14540697 | 1997-06-03 | ||
JP14540697 | 1997-06-03 | ||
JP21504797 | 1997-08-08 | ||
JP21504797 | 1997-08-08 | ||
JP33273997 | 1997-12-03 | ||
JP33273997 | 1997-12-03 | ||
PCT/JP1998/002443 WO1998056004A1 (fr) | 1997-06-03 | 1998-06-03 | Memoire a semi-conducteurs |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69832455D1 true DE69832455D1 (de) | 2005-12-29 |
DE69832455T2 DE69832455T2 (de) | 2006-06-29 |
Family
ID=27318986
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69832455T Expired - Lifetime DE69832455T2 (de) | 1997-06-03 | 1998-06-03 | Halbleiterspeicheranordnung |
Country Status (7)
Country | Link |
---|---|
US (3) | US6088291A (de) |
EP (2) | EP1603136B1 (de) |
JP (1) | JP3510638B2 (de) |
KR (1) | KR100285225B1 (de) |
DE (1) | DE69832455T2 (de) |
TW (1) | TW378330B (de) |
WO (1) | WO1998056004A1 (de) |
Families Citing this family (54)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
UA59384C2 (uk) * | 1996-12-20 | 2003-09-15 | Пфайзер, Інк. | Похідні сульфонамідів та амідів як агоністи простагландину, фармацевтична композиція та способи лікування на їх основі |
TW378330B (en) | 1997-06-03 | 2000-01-01 | Fujitsu Ltd | Semiconductor memory device |
AU9693398A (en) * | 1997-10-10 | 1999-05-03 | Rambus Incorporated | Apparatus and method for pipelined memory operations |
JP3362775B2 (ja) * | 1998-12-25 | 2003-01-07 | インターナショナル・ビジネス・マシーンズ・コーポレーション | Dram及びdramのデータ・アクセス方法 |
EP1028429A3 (de) * | 1999-02-12 | 2000-09-13 | Infineon Technologies North America Corp. | Vorausladearchitektur für Daten- und Taktsignale in einer integrierten Schaltung und Verfahren hierfür |
US6529054B1 (en) | 1999-02-12 | 2003-03-04 | Infineon Technologies Ag | Prefetch architectures for data and time signals in an integrated circuit and methods therefor |
US6275435B1 (en) * | 1999-03-31 | 2001-08-14 | Vanguard International Semiconductor Corp. | Bi-directional sense amplifier stage for memory datapath |
JP4270707B2 (ja) | 1999-04-09 | 2009-06-03 | 株式会社東芝 | ダイナミック型半導体記憶装置 |
KR100318264B1 (ko) * | 1999-06-28 | 2001-12-24 | 박종섭 | 패킷명령어 구동형 메모리소자의 로드신호 발생회로 |
JP2001035153A (ja) | 1999-07-23 | 2001-02-09 | Fujitsu Ltd | 半導体記憶装置 |
JP2001067866A (ja) * | 1999-08-30 | 2001-03-16 | Mitsubishi Electric Corp | 同期型半導体記憶装置 |
JP3973066B2 (ja) * | 1999-09-10 | 2007-09-05 | パイオニア株式会社 | 符号誤り訂正回路及び符号誤り訂正方法 |
JP4083944B2 (ja) | 1999-12-13 | 2008-04-30 | 東芝マイクロエレクトロニクス株式会社 | 半導体記憶装置 |
JP4253097B2 (ja) | 1999-12-28 | 2009-04-08 | 東芝マイクロエレクトロニクス株式会社 | 半導体記憶装置及びそのデータ読み出し方法 |
JP4627103B2 (ja) * | 2000-01-18 | 2011-02-09 | 富士通セミコンダクター株式会社 | 半導体記憶装置及びその制御方法 |
JP2001222888A (ja) | 2000-02-08 | 2001-08-17 | Fujitsu Ltd | 半導体記憶装置 |
JP4756724B2 (ja) * | 2000-02-24 | 2011-08-24 | エルピーダメモリ株式会社 | 半導体記憶装置 |
US6826104B2 (en) * | 2000-03-24 | 2004-11-30 | Kabushiki Kaisha Toshiba | Synchronous semiconductor memory |
JP2001283590A (ja) * | 2000-03-31 | 2001-10-12 | Fujitsu Ltd | 半導体集積回路 |
EP1307884A2 (de) * | 2000-07-07 | 2003-05-07 | Mosaid Technologies Incorporated | Hochgeschwindigkeitsarchitektur einer dynamischen halbleiterspeicheranordnung mit wahlfreiem zugriff (dram) mit gleichförmiger zugriffslatenzzeit |
JP5034149B2 (ja) * | 2000-10-05 | 2012-09-26 | 富士通セミコンダクター株式会社 | 半導体メモリおよびその制御方法 |
US6510100B2 (en) | 2000-12-04 | 2003-01-21 | International Business Machines Corporation | Synchronous memory modules and memory systems with selectable clock termination |
EP1227499B1 (de) * | 2001-01-24 | 2006-05-10 | STMicroelectronics S.r.l. | Nichtflüchtiger elektrisch veränderbarer Halbleiterspeicher |
JP4822604B2 (ja) * | 2001-04-10 | 2011-11-24 | 富士通セミコンダクター株式会社 | 半導体集積回路装置 |
US6449202B1 (en) | 2001-08-14 | 2002-09-10 | International Business Machines Corporation | DRAM direct sensing scheme |
KR100414734B1 (ko) * | 2001-12-21 | 2004-01-13 | 주식회사 하이닉스반도체 | 반도체 메모리 장치 |
KR100406543B1 (ko) | 2001-12-24 | 2003-11-20 | 주식회사 하이닉스반도체 | 동기식 메모리의 파이프 래치 제어회로 |
JP3831309B2 (ja) * | 2002-01-29 | 2006-10-11 | 株式会社東芝 | 同期型半導体記憶装置及びその動作方法 |
KR100480597B1 (ko) * | 2002-05-14 | 2005-04-06 | 삼성전자주식회사 | 출력 피드백 신호를 사용하여 오프셋 전압을 조절하는입력 수신기 |
JP2004063023A (ja) * | 2002-07-30 | 2004-02-26 | Renesas Technology Corp | 半導体記憶装置 |
US6738300B2 (en) * | 2002-08-26 | 2004-05-18 | International Business Machines Corporation | Direct read of DRAM cell using high transfer ratio |
JP4077295B2 (ja) | 2002-10-23 | 2008-04-16 | 株式会社東芝 | 同期型半導体記憶装置及びその動作方法 |
KR100490653B1 (ko) * | 2002-10-31 | 2005-05-24 | 주식회사 하이닉스반도체 | 노이즈가 감소된 반도체 메모리 장치 |
JP2004234760A (ja) * | 2003-01-30 | 2004-08-19 | Renesas Technology Corp | 半導体記憶装置 |
DE10319158A1 (de) * | 2003-04-29 | 2004-11-25 | Infineon Technologies Ag | Vorrichtung zum flexiblen Deaktivieren von Wortleitungen von dynamischen Speicherbausteinen und Verfahren hierfür |
US7143257B2 (en) * | 2003-10-14 | 2006-11-28 | Atmel Corporation | Method and apparatus of a smart decoding scheme for fast synchronous read in a memory system |
TWI260019B (en) | 2004-05-21 | 2006-08-11 | Fujitsu Ltd | Semiconductor memory device and memory system |
JP2006059046A (ja) | 2004-08-19 | 2006-03-02 | Nec Computertechno Ltd | メモリの制御方式およびメモリ制御回路 |
US7145822B2 (en) * | 2005-03-03 | 2006-12-05 | Texas Instruments Incorporated | Method and apparatus for optimal write restore for memory |
JP4516483B2 (ja) | 2005-06-07 | 2010-08-04 | 富士通セミコンダクター株式会社 | 半導体記憶装置及び情報処理システム |
US7515482B2 (en) * | 2005-09-29 | 2009-04-07 | Hynix Semiconductor Inc. | Pipe latch device of semiconductor memory device |
KR100735749B1 (ko) | 2005-11-28 | 2007-07-06 | 삼성전자주식회사 | 반도체 메모리 장치, 메모리 시스템, 및 데이터 송수신시스템 |
US7430151B2 (en) * | 2006-03-29 | 2008-09-30 | Freescale Semiconductor, Inc. | Memory with clocked sense amplifier |
KR100738394B1 (ko) * | 2006-08-14 | 2007-07-12 | 삼성전기주식회사 | 카오스 신호 발생장치 및 그 발생방법 |
US8107308B2 (en) * | 2009-01-13 | 2012-01-31 | Samsung Electronics Co., Ltd. | Semiconductor memory device |
US7864620B1 (en) * | 2009-03-19 | 2011-01-04 | Altera Corporation | Partially reconfigurable memory cell arrays |
WO2012114647A1 (ja) * | 2011-02-22 | 2012-08-30 | パナソニック株式会社 | ワード線起動回路、半導体記憶装置、および半導体集積回路 |
JP5795513B2 (ja) * | 2011-09-28 | 2015-10-14 | ピーエスフォー ルクスコ エスエイアールエルPS4 Luxco S.a.r.l. | 半導体装置 |
KR102007364B1 (ko) * | 2012-08-28 | 2019-08-05 | 에스케이하이닉스 주식회사 | 반도체 메모리 장치 |
US9053815B2 (en) * | 2013-05-28 | 2015-06-09 | Nanya Technology Corporation | Circuit in dynamic random access memory devices |
US9070433B1 (en) * | 2014-03-11 | 2015-06-30 | International Business Machines Corporation | SRAM supply voltage global bitline precharge pulse |
KR102491689B1 (ko) * | 2016-03-03 | 2023-01-26 | 에스케이하이닉스 주식회사 | 반도체장치 |
US10162522B1 (en) * | 2016-09-30 | 2018-12-25 | Cadence Design Systems, Inc. | Architecture of single channel memory controller to support high bandwidth memory of pseudo channel mode or legacy mode |
KR20230072282A (ko) * | 2021-11-17 | 2023-05-24 | 삼성전자주식회사 | 메모리 장치, 그것을 포함하는 메모리 시스템 및 그것의 동작 방법 |
Family Cites Families (24)
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JPS6012718B2 (ja) * | 1980-03-28 | 1985-04-03 | 富士通株式会社 | 半導体ダイナミックメモリ |
JPS60689A (ja) * | 1983-06-15 | 1985-01-05 | Hitachi Ltd | Mos記憶装置 |
JPH0758589B2 (ja) * | 1987-04-03 | 1995-06-21 | 三菱電機株式会社 | 半導体記憶装置 |
JPH01286197A (ja) * | 1988-05-13 | 1989-11-17 | Hitachi Ltd | 半導体記憶装置 |
JPH0745067B2 (ja) | 1989-03-14 | 1995-05-17 | 新日本製鐵株式会社 | 金属帯の巻取り装置 |
US5276649A (en) * | 1989-03-16 | 1994-01-04 | Mitsubishi Denki Kabushiki Kaisha | Dynamic-type semiconductor memory device having staggered activation of column groups |
IL96808A (en) | 1990-04-18 | 1996-03-31 | Rambus Inc | Introductory / Origin Circuit Agreed Using High-Performance Brokerage |
JPH04147492A (ja) * | 1990-10-11 | 1992-05-20 | Hitachi Ltd | 半導体メモリ |
JP2740097B2 (ja) * | 1992-03-19 | 1998-04-15 | 株式会社東芝 | クロック同期型半導体記憶装置およびそのアクセス方法 |
JP3186204B2 (ja) * | 1992-05-13 | 2001-07-11 | 日本電気株式会社 | 半導体ダイナミックram |
US5406526A (en) | 1992-10-01 | 1995-04-11 | Nec Corporation | Dynamic random access memory device having sense amplifier arrays selectively activated when associated memory cell sub-arrays are accessed |
JP2956426B2 (ja) * | 1993-07-30 | 1999-10-04 | 日本電気株式会社 | 半導体記憶装置 |
KR970001699B1 (ko) * | 1994-03-03 | 1997-02-13 | 삼성전자 주식회사 | 자동프리차아지기능을 가진 동기식 반도체메모리장치 |
JP2982618B2 (ja) * | 1994-06-28 | 1999-11-29 | 日本電気株式会社 | メモリ選択回路 |
JP2705590B2 (ja) * | 1994-10-28 | 1998-01-28 | 日本電気株式会社 | 半導体記憶装置 |
JPH0963264A (ja) * | 1995-08-18 | 1997-03-07 | Fujitsu Ltd | 同期型dram |
JPH09161471A (ja) | 1995-12-06 | 1997-06-20 | Internatl Business Mach Corp <Ibm> | Dramシステム、dramシステムの動作方法 |
JP3352577B2 (ja) * | 1995-12-21 | 2002-12-03 | インターナショナル・ビジネス・マシーンズ・コーポレーション | 記憶装置 |
JP3843145B2 (ja) * | 1995-12-25 | 2006-11-08 | 株式会社ルネサステクノロジ | 同期型半導体記憶装置 |
KR100247923B1 (ko) | 1997-01-29 | 2000-03-15 | 윤종용 | 스위치신호발생기및이를이용한고속동기형sram |
TW378330B (en) * | 1997-06-03 | 2000-01-01 | Fujitsu Ltd | Semiconductor memory device |
US6240046B1 (en) * | 1999-02-13 | 2001-05-29 | Integrated Device Technology, Inc. | Integrated circuit random access memory capable of reading either one or more than one data word in a single clock cycle |
JP2001101863A (ja) * | 1999-09-27 | 2001-04-13 | Fujitsu Ltd | 半導体集積回路およびその制御方法 |
JP4531892B2 (ja) * | 1999-10-29 | 2010-08-25 | 富士通セミコンダクター株式会社 | 半導体集積回路、半導体集積回路の制御方法、および可変遅延回路 |
-
1998
- 1998-06-02 TW TW087108643A patent/TW378330B/zh not_active IP Right Cessation
- 1998-06-03 US US09/147,600 patent/US6088291A/en not_active Expired - Lifetime
- 1998-06-03 EP EP05017186.7A patent/EP1603136B1/de not_active Expired - Lifetime
- 1998-06-03 DE DE69832455T patent/DE69832455T2/de not_active Expired - Lifetime
- 1998-06-03 EP EP98923094A patent/EP0917153B1/de not_active Expired - Lifetime
- 1998-06-03 JP JP50205799A patent/JP3510638B2/ja not_active Expired - Fee Related
- 1998-06-03 WO PCT/JP1998/002443 patent/WO1998056004A1/ja active IP Right Grant
- 1998-06-03 KR KR1019997000920A patent/KR100285225B1/ko not_active IP Right Cessation
-
2000
- 2000-03-23 US US09/533,759 patent/US6246620B1/en not_active Expired - Lifetime
-
2001
- 2001-04-16 US US09/834,945 patent/US6459641B2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
EP1603136B1 (de) | 2013-10-23 |
WO1998056004A1 (fr) | 1998-12-10 |
EP0917153A1 (de) | 1999-05-19 |
EP0917153A4 (de) | 2000-12-13 |
US6088291A (en) | 2000-07-11 |
KR100285225B1 (ko) | 2001-03-15 |
EP0917153B1 (de) | 2005-11-23 |
EP1603136A3 (de) | 2007-06-06 |
US6246620B1 (en) | 2001-06-12 |
US6459641B2 (en) | 2002-10-01 |
EP1603136A2 (de) | 2005-12-07 |
KR20000068042A (ko) | 2000-11-25 |
US20010021140A1 (en) | 2001-09-13 |
TW378330B (en) | 2000-01-01 |
DE69832455T2 (de) | 2006-06-29 |
JP3510638B2 (ja) | 2004-03-29 |
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Owner name: FUJITSU MICROELECTRONICS LTD., TOKYO, JP |
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Owner name: FUJITSU SEMICONDUCTOR LTD., YOKOHAMA, KANAGAWA, JP |
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Representative=s name: SEEGER SEEGER LINDNER PARTNERSCHAFT PATENTANWAELTE |