DE69728312D1 - Halbleiterspeicheranordnung - Google Patents
HalbleiterspeicheranordnungInfo
- Publication number
- DE69728312D1 DE69728312D1 DE69728312T DE69728312T DE69728312D1 DE 69728312 D1 DE69728312 D1 DE 69728312D1 DE 69728312 T DE69728312 T DE 69728312T DE 69728312 T DE69728312 T DE 69728312T DE 69728312 D1 DE69728312 D1 DE 69728312D1
- Authority
- DE
- Germany
- Prior art keywords
- memory device
- semiconductor memory
- semiconductor
- memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1048—Data bus control circuits, e.g. precharging, presetting, equalising
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Dram (AREA)
- Static Random-Access Memory (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1572796 | 1996-01-31 | ||
JP01572796A JP3277112B2 (ja) | 1996-01-31 | 1996-01-31 | 半導体記憶装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69728312D1 true DE69728312D1 (de) | 2004-05-06 |
DE69728312T2 DE69728312T2 (de) | 2005-02-17 |
Family
ID=11896798
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69728312T Expired - Lifetime DE69728312T2 (de) | 1996-01-31 | 1997-01-29 | Halbleiterspeicheranordnung |
Country Status (6)
Country | Link |
---|---|
US (1) | US5841730A (de) |
EP (1) | EP0788107B1 (de) |
JP (1) | JP3277112B2 (de) |
KR (1) | KR100272142B1 (de) |
DE (1) | DE69728312T2 (de) |
TW (1) | TW374931B (de) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH1186547A (ja) * | 1997-08-30 | 1999-03-30 | Toshiba Corp | 半導体集積回路装置 |
JP3223964B2 (ja) * | 1998-04-03 | 2001-10-29 | 日本電気株式会社 | 半導体記憶装置 |
JP3244048B2 (ja) * | 1998-05-19 | 2002-01-07 | 日本電気株式会社 | 半導体記憶装置 |
US6115308A (en) * | 1999-06-17 | 2000-09-05 | International Business Machines Corporation | Sense amplifier and method of using the same with pipelined read, restore and write operations |
DE19933540C2 (de) * | 1999-07-16 | 2001-10-04 | Infineon Technologies Ag | Synchroner integrierter Speicher |
US6532180B2 (en) | 2001-06-20 | 2003-03-11 | Micron Technology, Inc. | Write data masking for higher speed DRAMs |
US7428168B2 (en) * | 2005-09-28 | 2008-09-23 | Hynix Semiconductor Inc. | Semiconductor memory device sharing a data line sense amplifier and a write driver in order to reduce a chip size |
KR101239226B1 (ko) * | 2007-08-02 | 2013-03-06 | 삼성전자주식회사 | 언먹스드 비트라인 스킴을 위한 기입 구동회로 |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07118196B2 (ja) * | 1988-12-28 | 1995-12-18 | 株式会社東芝 | スタティック型半導体メモリ |
JPH02218092A (ja) * | 1989-02-18 | 1990-08-30 | Sony Corp | 半導体メモリ装置 |
US5416743A (en) * | 1993-12-10 | 1995-05-16 | Mosaid Technologies Incorporated | Databus architecture for accelerated column access in RAM |
JP2906957B2 (ja) * | 1993-12-15 | 1999-06-21 | 日本電気株式会社 | 半導体メモリ装置 |
JP2734957B2 (ja) * | 1993-12-24 | 1998-04-02 | 日本電気株式会社 | 半導体記憶回路の制御方法 |
US5497115A (en) * | 1994-04-29 | 1996-03-05 | Mosaid Technologies Incorporated | Flip-flop circuit having low standby power for driving synchronous dynamic random access memory |
JP2697633B2 (ja) * | 1994-09-30 | 1998-01-14 | 日本電気株式会社 | 同期型半導体記憶装置 |
JP2697634B2 (ja) * | 1994-09-30 | 1998-01-14 | 日本電気株式会社 | 同期型半導体記憶装置 |
JPH08221981A (ja) * | 1994-12-15 | 1996-08-30 | Mitsubishi Electric Corp | 同期型半導体記憶装置 |
-
1996
- 1996-01-31 JP JP01572796A patent/JP3277112B2/ja not_active Expired - Fee Related
-
1997
- 1997-01-29 EP EP97101347A patent/EP0788107B1/de not_active Expired - Lifetime
- 1997-01-29 TW TW086100989A patent/TW374931B/zh active
- 1997-01-29 DE DE69728312T patent/DE69728312T2/de not_active Expired - Lifetime
- 1997-01-29 US US08/790,907 patent/US5841730A/en not_active Expired - Lifetime
- 1997-01-31 KR KR1019970003024A patent/KR100272142B1/ko not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
EP0788107A2 (de) | 1997-08-06 |
TW374931B (en) | 1999-11-21 |
KR970060224A (ko) | 1997-08-12 |
EP0788107B1 (de) | 2004-03-31 |
EP0788107A3 (de) | 1999-06-02 |
JP3277112B2 (ja) | 2002-04-22 |
DE69728312T2 (de) | 2005-02-17 |
KR100272142B1 (ko) | 2000-12-01 |
JPH09213076A (ja) | 1997-08-15 |
US5841730A (en) | 1998-11-24 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
DE69526460D1 (de) | Halbleiterspeicheranordnung | |
DE69623832D1 (de) | Halbleiterspeicheranordnung | |
DE69620149D1 (de) | Halbleiteranordnung | |
DE69430683D1 (de) | Halbleiterspeicheranordnung | |
DE69603632D1 (de) | Halbleiter-Speicheranordnung | |
DE69521159D1 (de) | Halbleiterspeicheranordnung | |
DE69623376D1 (de) | Halbleiterspeicheranordnung | |
DE69422901D1 (de) | Halbleiterspeicheranordnung | |
DE69512700D1 (de) | Halbleiterspeicheranordnung | |
DE69617391D1 (de) | Halbleiterspeicheranordnung | |
DE69615783D1 (de) | Halbleiterspeicheranordnung | |
DE69722133D1 (de) | Nichtflüchtige Halbleiterspeicheranordnung | |
DE69726698T2 (de) | Nichtflüchtige Halbleiterspeicheranordnung | |
DE69629068D1 (de) | Halbleiterspeicheranordnung | |
KR960012510A (ko) | 반도체 메모리 장치 | |
DE69600591D1 (de) | Halbleiterspeicheranordnung | |
DE69731015D1 (de) | Halbleiterspeicheranordnung | |
DE69432882D1 (de) | Halbleiterspeicheranordnung | |
DE69624297D1 (de) | Halbleiterspeicheranordnung | |
DE69525583D1 (de) | Halbleiterspeicheranordnung | |
DE69934853D1 (de) | Halbleiterspeicheranordnung | |
DE69823427D1 (de) | Halbleiterspeicheranordnung | |
DE69530266D1 (de) | Halbleiterspeicheranordnung | |
DE69430944D1 (de) | Halbleiterspeicheranordnung | |
DE69534964D1 (de) | Halbleiterspeicheranordnung |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition |