DE69315370T2 - Herstellung von rauhen Silizium-Oberflächen - Google Patents

Herstellung von rauhen Silizium-Oberflächen

Info

Publication number
DE69315370T2
DE69315370T2 DE69315370T DE69315370T DE69315370T2 DE 69315370 T2 DE69315370 T2 DE 69315370T2 DE 69315370 T DE69315370 T DE 69315370T DE 69315370 T DE69315370 T DE 69315370T DE 69315370 T2 DE69315370 T2 DE 69315370T2
Authority
DE
Germany
Prior art keywords
production
silicon surfaces
rough silicon
rough
silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69315370T
Other languages
English (en)
Other versions
DE69315370D1 (de
Inventor
Stephane Simon Dana
Mariano Anderle
Gary Wayne Rubloff
Alejandro Gabriel Schrott
Michael Liehr
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE69315370D1 publication Critical patent/DE69315370D1/de
Publication of DE69315370T2 publication Critical patent/DE69315370T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/84—Electrodes with an enlarged surface, e.g. formed by texturisation being a rough surface, e.g. using hemispherical grains
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B5/00—Recording by magnetisation or demagnetisation of a record carrier; Reproducing by magnetic means; Record carriers therefor
    • G11B5/62—Record carriers characterised by the selection of the material
    • G11B5/73—Base layers, i.e. all non-magnetic layers lying under a lowermost magnetic recording layer, e.g. including any non-magnetic layer in between a first magnetic recording layer and either an underlying substrate or a soft magnetic underlayer
    • G11B5/7368—Non-polymeric layer under the lowermost magnetic recording layer
    • G11B5/7369—Two or more non-magnetic underlayers, e.g. seed layers or barrier layers
    • G11B5/737—Physical structure of underlayer, e.g. texture
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B5/00—Recording by magnetisation or demagnetisation of a record carrier; Reproducing by magnetic means; Record carriers therefor
    • G11B5/62—Record carriers characterised by the selection of the material
    • G11B5/73—Base layers, i.e. all non-magnetic layers lying under a lowermost magnetic recording layer, e.g. including any non-magnetic layer in between a first magnetic recording layer and either an underlying substrate or a soft magnetic underlayer
    • G11B5/7368—Non-polymeric layer under the lowermost magnetic recording layer
    • G11B5/7377—Physical structure of underlayer, e.g. texture
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0054—Processes for devices with an active region comprising only group IV elements

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Chemical Vapour Deposition (AREA)
DE69315370T 1992-04-10 1993-03-12 Herstellung von rauhen Silizium-Oberflächen Expired - Fee Related DE69315370T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US86671392A 1992-04-10 1992-04-10

Publications (2)

Publication Number Publication Date
DE69315370D1 DE69315370D1 (de) 1998-01-08
DE69315370T2 true DE69315370T2 (de) 1998-05-28

Family

ID=25348238

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69315370T Expired - Fee Related DE69315370T2 (de) 1992-04-10 1993-03-12 Herstellung von rauhen Silizium-Oberflächen

Country Status (3)

Country Link
EP (1) EP0567748B1 (de)
JP (1) JPH0620958A (de)
DE (1) DE69315370T2 (de)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10229231A1 (de) * 2002-06-28 2004-01-15 Osram Opto Semiconductors Gmbh Verfahren zum Herstellen eines Strahlung emittierenden und/oder empfangenden Halbleiterchips mit einer Strahlungsein- und/oder -auskoppel-Mikrostruktur

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69434767T2 (de) * 1993-11-02 2006-11-09 Matsushita Electric Industrial Co., Ltd., Kadoma Halbleiterbauelement mit Aggregat von Mikro-Nadeln aus Halbleitermaterial
US6734451B2 (en) 1993-11-02 2004-05-11 Matsushita Electric Industrial Co., Ltd. Aggregate of semiconductor micro-needles and method of manufacturing the same, and semiconductor apparatus and method of manufacturing the same
US5705287A (en) * 1994-09-20 1998-01-06 International Business Machines Corporation Magnetic recording disk with metal nitride texturing layer
WO1996037885A1 (de) * 1995-05-26 1996-11-28 International Business Machines Corporation Direkt kontaktierbare platte für vertikale magnetische datenspeicherung
DE19632834C2 (de) * 1996-08-14 1998-11-05 Siemens Ag Verfahren zur Herstellung feiner Strukturen und dessen Verwendung zur Herstellung einer Maske und eines MOS-Transistors
DE19632835C1 (de) * 1996-08-14 1998-04-02 Siemens Ag Verfahren zur Herstellung eines Kondensators in einer Halbeiteranordnung
DE19756410A1 (de) * 1997-12-18 1999-06-24 Ibm Steuerung der Oberflächenrauhigkeit von Magnetplatten
US6794704B2 (en) 2002-01-16 2004-09-21 Micron Technology, Inc. Method for enhancing electrode surface area in DRAM cell capacitors
FR2847567B1 (fr) * 2002-11-22 2005-07-01 Commissariat Energie Atomique Procede de realisation par cvd de nano-structures de materiau semi-conducteur sur dielectrique, de tailles homogenes et controlees
KR20040069807A (ko) * 2003-01-30 2004-08-06 아남반도체 주식회사 박막 커패시터 및 그 제조 방법
KR100526463B1 (ko) * 2003-05-07 2005-11-08 매그나칩 반도체 유한회사 반도체 소자의 제조 방법
US7057881B2 (en) * 2004-03-18 2006-06-06 Nanosys, Inc Nanofiber surface based capacitors
US7903786B2 (en) 2008-08-25 2011-03-08 General Electric Company Apparatus for increasing radiative heat transfer in an X-ray tube and method of making same
US20120105385A1 (en) * 2010-11-02 2012-05-03 Qualcomm Mems Technologies, Inc. Electromechanical systems apparatuses and methods for providing rough surfaces
CN109873059A (zh) * 2019-02-26 2019-06-11 苏州晶湛半导体有限公司 发光器件表面粗化的方法与发光器件

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3543254A1 (de) * 1985-12-06 1987-06-11 Siemens Ag Plattenfoermiges aufzeichnungsmedium zur senkrechten magnetisierung
JPS6366720A (ja) * 1986-09-06 1988-03-25 Hitachi Maxell Ltd 磁気記録媒体およびその製造方法
JPH0258729A (ja) * 1988-08-24 1990-02-27 Nec Corp 磁気ディスク基板およびその製造方法
JPH03101261A (ja) * 1989-09-14 1991-04-26 Sony Corp 容量素子の形成方法
JPH03234051A (ja) * 1990-02-09 1991-10-18 Matsushita Electron Corp 容量素子の製造方法
US5102832A (en) * 1991-02-11 1992-04-07 Micron Technology, Inc. Methods for texturizing polysilicon
US5112773A (en) * 1991-04-10 1992-05-12 Micron Technology, Inc. Methods for texturizing polysilicon utilizing gas phase nucleation
JP3192673B2 (ja) * 1991-03-18 2001-07-30 宮崎沖電気株式会社 半導体素子の製造方法

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10229231A1 (de) * 2002-06-28 2004-01-15 Osram Opto Semiconductors Gmbh Verfahren zum Herstellen eines Strahlung emittierenden und/oder empfangenden Halbleiterchips mit einer Strahlungsein- und/oder -auskoppel-Mikrostruktur
DE10229231B4 (de) * 2002-06-28 2005-03-17 Osram Opto Semiconductors Gmbh Verfahren zum Herstellen eines Strahlung emittierenden und/oder empfangenden Halbleiterchips mit einer Strahlungsein- und/oder -auskoppel-Mikrostruktur
DE10229231B9 (de) * 2002-06-28 2006-05-11 Osram Opto Semiconductors Gmbh Verfahren zum Herstellen eines Strahlung emittierenden und/oder empfangenden Halbleiterchips mit einer Strahlungsein- und/oder -auskoppel-Mikrostruktur

Also Published As

Publication number Publication date
JPH0620958A (ja) 1994-01-28
EP0567748B1 (de) 1997-11-26
EP0567748A1 (de) 1993-11-03
DE69315370D1 (de) 1998-01-08

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee