DE69224084D1 - Rechneranordnung mit Mehrfachpufferdatencachespeicher und Verfahren dafür - Google Patents
Rechneranordnung mit Mehrfachpufferdatencachespeicher und Verfahren dafürInfo
- Publication number
- DE69224084D1 DE69224084D1 DE69224084T DE69224084T DE69224084D1 DE 69224084 D1 DE69224084 D1 DE 69224084D1 DE 69224084 T DE69224084 T DE 69224084T DE 69224084 T DE69224084 T DE 69224084T DE 69224084 D1 DE69224084 D1 DE 69224084D1
- Authority
- DE
- Germany
- Prior art keywords
- data cache
- method therefor
- buffer data
- computer arrangement
- multiple buffer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
- G06F12/0846—Cache with multiple tag or data arrays being simultaneously accessible
- G06F12/0848—Partitioned cache, e.g. separate instruction and operand caches
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0862—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3824—Operand accessing
- G06F9/383—Operand prefetching
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
- G06F12/0846—Cache with multiple tag or data arrays being simultaneously accessible
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/60—Details of cache memory
- G06F2212/6028—Prefetching based on hints or prefetch instructions
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Software Systems (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US64123691A | 1991-01-15 | 1991-01-15 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69224084D1 true DE69224084D1 (de) | 1998-02-26 |
DE69224084T2 DE69224084T2 (de) | 1998-07-23 |
Family
ID=24571535
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69224084T Expired - Fee Related DE69224084T2 (de) | 1991-01-15 | 1992-01-06 | Rechneranordnung mit Mehrfachpufferdatencachespeicher und Verfahren dafür |
Country Status (4)
Country | Link |
---|---|
US (1) | US5822757A (de) |
EP (1) | EP0496439B1 (de) |
JP (1) | JP3425158B2 (de) |
DE (1) | DE69224084T2 (de) |
Families Citing this family (29)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06180669A (ja) * | 1992-12-14 | 1994-06-28 | Nec Niigata Ltd | キャッシュシステム |
US5848432A (en) | 1993-08-05 | 1998-12-08 | Hitachi, Ltd. | Data processor with variable types of cache memories |
JPH0895857A (ja) * | 1994-09-29 | 1996-04-12 | Shikoku Nippon Denki Software Kk | 入出力キャッシュ |
US5732242A (en) | 1995-03-24 | 1998-03-24 | Silicon Graphics, Inc. | Consistently specifying way destinations through prefetching hints |
DE19713178A1 (de) * | 1997-03-27 | 1998-10-01 | Siemens Ag | Schaltungsanordnung mit einem Prozessor und einem Datenspeicher |
US7103794B2 (en) * | 1998-06-08 | 2006-09-05 | Cacheflow, Inc. | Network object cache engine |
US6122708A (en) * | 1997-08-15 | 2000-09-19 | Hewlett-Packard Company | Data cache for use with streaming data |
US6393526B1 (en) | 1997-10-28 | 2002-05-21 | Cache Plan, Inc. | Shared cache parsing and pre-fetch |
US6151662A (en) * | 1997-12-02 | 2000-11-21 | Advanced Micro Devices, Inc. | Data transaction typing for improved caching and prefetching characteristics |
US6202129B1 (en) * | 1998-03-31 | 2001-03-13 | Intel Corporation | Shared cache structure for temporal and non-temporal information using indicative bits |
US6401193B1 (en) * | 1998-10-26 | 2002-06-04 | Infineon Technologies North America Corp. | Dynamic data prefetching based on program counter and addressing mode |
WO2000031642A1 (de) * | 1998-11-25 | 2000-06-02 | Fujitsu Siemens Computers Gmbh | Cache-speichereinrichtung |
US6378042B1 (en) * | 1999-08-11 | 2002-04-23 | Fast-Chip, Inc. | Caching associative memory |
WO2001038970A2 (en) * | 1999-11-22 | 2001-05-31 | Ericsson Inc | Buffer memories, methods and systems for buffering having seperate buffer memories for each of a plurality of tasks |
JP2001273137A (ja) * | 2000-03-28 | 2001-10-05 | Toshiba Corp | マイクロプロセッサ |
US6578111B1 (en) * | 2000-09-29 | 2003-06-10 | Sun Microsystems, Inc. | Cache memory system and method for managing streaming-data |
US6668307B1 (en) * | 2000-09-29 | 2003-12-23 | Sun Microsystems, Inc. | System and method for a software controlled cache |
US6598124B1 (en) * | 2000-09-29 | 2003-07-22 | Sun Microsystems, Inc. | System and method for identifying streaming-data |
JP4116413B2 (ja) * | 2002-12-11 | 2008-07-09 | 株式会社日立製作所 | プリフェッチアプライアンスサーバ |
US7284014B2 (en) | 2003-04-07 | 2007-10-16 | Hitachi, Ltd. | Pre-fetch computer system |
JPWO2006109421A1 (ja) * | 2005-04-08 | 2008-10-16 | 松下電器産業株式会社 | キャッシュメモリ |
GB2425030A (en) * | 2005-04-09 | 2006-10-11 | Tenomichi Ltd | Managed network render targets for routing graphical information |
JP2008257508A (ja) * | 2007-04-05 | 2008-10-23 | Nec Electronics Corp | キャッシュ制御方法およびキャッシュ装置並びにマイクロコンピュータ |
US8312219B2 (en) * | 2009-03-02 | 2012-11-13 | International Business Machines Corporation | Hybrid caching techniques and garbage collection using hybrid caching techniques |
CN102141905B (zh) * | 2010-01-29 | 2015-02-25 | 上海芯豪微电子有限公司 | 一种处理器体系结构 |
US10114750B2 (en) | 2012-01-23 | 2018-10-30 | Qualcomm Incorporated | Preventing the displacement of high temporal locality of reference data fill buffers |
US10552329B2 (en) * | 2014-12-23 | 2020-02-04 | Prophetstor Data Services, Inc. | SSD caching system for hybrid storage |
US9772824B2 (en) | 2015-03-25 | 2017-09-26 | International Business Machines Corporation | Program structure-based blocking |
KR20160148952A (ko) * | 2015-06-17 | 2016-12-27 | 에스케이하이닉스 주식회사 | 메모리 시스템 및 메모리 시스템의 동작 방법 |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4437149A (en) * | 1980-11-17 | 1984-03-13 | International Business Machines Corporation | Cache memory architecture with decoding |
JPS5891570A (ja) * | 1981-11-27 | 1983-05-31 | Nec Corp | 情報処理システム |
US4594659A (en) * | 1982-10-13 | 1986-06-10 | Honeywell Information Systems Inc. | Method and apparatus for prefetching instructions for a central execution pipeline unit |
US4719568A (en) * | 1982-12-30 | 1988-01-12 | International Business Machines Corporation | Hierarchical memory system including separate cache memories for storing data and instructions |
US4701844A (en) * | 1984-03-30 | 1987-10-20 | Motorola Computer Systems, Inc. | Dual cache for independent prefetch and execution units |
CA1279731C (en) * | 1986-06-27 | 1991-01-29 | Ruby Bei-Loh Lee | Cache memory with variable fetch and replacement schemes |
US4928239A (en) * | 1986-06-27 | 1990-05-22 | Hewlett-Packard Company | Cache memory with variable fetch and replacement schemes |
US4853846A (en) * | 1986-07-29 | 1989-08-01 | Intel Corporation | Bus expander with logic for virtualizing single cache control into dual channels with separate directories and prefetch for different processors |
US4980823A (en) * | 1987-06-22 | 1990-12-25 | International Business Machines Corporation | Sequential prefetching with deconfirmation |
US4926323A (en) * | 1988-03-03 | 1990-05-15 | Advanced Micro Devices, Inc. | Streamlined instruction processor |
-
1992
- 1992-01-06 EP EP92200014A patent/EP0496439B1/de not_active Expired - Lifetime
- 1992-01-06 DE DE69224084T patent/DE69224084T2/de not_active Expired - Fee Related
- 1992-01-13 JP JP00383592A patent/JP3425158B2/ja not_active Expired - Fee Related
-
1995
- 1995-12-29 US US08/581,670 patent/US5822757A/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
EP0496439B1 (de) | 1998-01-21 |
JP3425158B2 (ja) | 2003-07-07 |
EP0496439A2 (de) | 1992-07-29 |
EP0496439A3 (en) | 1993-07-21 |
JPH04303248A (ja) | 1992-10-27 |
DE69224084T2 (de) | 1998-07-23 |
US5822757A (en) | 1998-10-13 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8327 | Change in the person/name/address of the patent owner |
Owner name: KONINKLIJKE PHILIPS ELECTRONICS N.V., EINDHOVEN, N |
|
8328 | Change in the person/name/address of the agent |
Representative=s name: VOLMER, G., DIPL.-ING., PAT.-ANW., 52066 AACHEN |
|
8339 | Ceased/non-payment of the annual fee |